266 results about "Memory testing" patented technology

A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells. Accordingly, each multi-port memory cell is connected to one word-line and two bit-lines per read/write port. The memory device includes memory testing logic to perform a first memory access operation (e.g., read/write) at a first port of the multi-port memory cell while the memory cell is in a stressed condition. For example, the first memory access operation occurs while a second memory access operation is emulated on a second port. Moreover, the memory access operations occur at a frequency that is substantially equivalent to a maximum operating frequency of the dual-port memory device.

The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.

A system and method for testing a plurality of memory blocks in a System on Chip (SOC) design uses two Test Access Ports (TAPs), a user TAP and an EDA tool TAP, to provide instructions and test data to the SOC. The system includes a glue logic block, a secured logic block and a memory testing module. The glue logic block selects the user TAP at the outset of the testing phase. The secured logic block is coupled with the user TAP and generates a TAP selection signal, which controls the selection of the EDA tool TAP. The memory testing module is used to carry out the process of testing the memory blocks when the EDA tool TAP is selected.

A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.

Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

The embodiment of the invention discloses a system self-test method, equipment and system, which relate to communication application technology and are used for solving the problems of long startup response time when a memory self-test function is started and shut off in power-on self-test and low reliability in a system self-test process. The method comprises the following steps: transmitting a memory test request to management equipment through system self-test equipment; receiving memory testing information generated by the management equipment according to the memory test request; acquiring a memory test parameter by resolving the memory test information, wherein the memory test parameter comprises a memory test target and/or memory test strategy information; and triggering memory detection of a corresponding memory position according to the memory test parameter. The embodiment of the invention is applied to power-on self-test of a server.

Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame generator that arranges the pattern of digits into a packet. The packet is then applied to a plurality of parallel-to-serial converters that convert the packet into a plurality of serial digits of a command/address packet or a write data packet, which are output through a plurality of bit lanes. The system might also include a plurality of serial-to-parallel converters receiving respective sets of digits of a read data packet through respective bit lanes. The read data packet is applied to a frame decomposer that extracts a pattern of read data digits from the packet. An error detecting circuit then determines if any of the received read data digits are erroneous.

A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.

The present invention provides a system and method for performing a memory test algorithm with a static random access memory (SRAM) unit having a read control module with no read enable control and write control module with write enable control. The system and method conduct read and write operations to the SRAM unit by avoiding simultaneously reading and writing to the same memory address. Simultaneously reading and writing to the same memory address is avoided by offsetting the read and write signals provided to the SRAM unit.

A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

The invention discloses a method for automatic testing of a memory of an intelligent mobile terminal, which is applied to the intelligent mobile terminal using an Android operation system. The method comprises two parts, namely automatic testing and judgment of memory leakage problems of resident services of the intelligent mobile terminal, and automatic testing and judgment of memory leakage problems of a single application, so the completeness of the memory leakage testing is guaranteed, the testing frequency each time and the recording frequency of memory values can be set, the stronger memory testing can be performed, and the relevant quality of the memory of the intelligent mobile terminal using the Android operation system is furthest guaranteed. The method has the advantages that the whole testing process is the full-automatic process, so the participation of persons is not needed in the testing process; a testing result report is automatically generated after the testing is finished, so the testing efficiency of the memory is greatly improved.

The invention relates to a memory testing method, wherein it comprises: activating operation system, to make the system enter into protective mode of memory test; building one address transfer page list in memory; judging if the physical address space of memory is over 4GB; if it is, activating address transfer page list, to transform appointed 32-bit linear address to relate with real physical address of memory; controlled by system central processor, based on the address transfer page list, inquiring and accessing the real physical address of memory, and executing the memory test algorism to test memory; if it is not, controlled by system central processor, directly accessing the real physical address of memory relative to the 32-bit linear address of system, and executing memory test algorism to test the memory. The invention can access and test the accidence and failure of memory address space more than 4GB, to improve the memory test range and save test cost.

The invention provides a testing device used for a testing method for remote control buttons. The testing device comprises a signal receiving module, a control judging module and a prompt device which are connected in sequence. The testing device further comprises a memory module and a timing module which are respectively connected with the control judging module. The invention further provides the testing method for the remote control buttons. According to the testing method and the testing device, mistakes caused by relying of manual visual and memory testing are avoided, efficiency is improved, probability of missing detection can be reduced to the greatest extent, products in a large scale are convenient to test, producing and testing efficiency is improved, and product quality is guaranteed.

Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.