149 results about "Memory testing" patented technology

The invention discloses a memory test method and device based on an AI technology and a medium, and the method comprises the following steps: 1) obtaining structure analysis data and memory type description information of a to-be-tested memory, and generating a test intention vector used for expressing a test target; 2) taking the test intention vector as an input to generate a test excitation sequence; 3) executing the test excitation sequence, and performing multi-cycle test on the storage array to form a multi-modal response feature set; 4) inputting the multi-modal response feature set into a graph neural network, performing fault type identification and causal path reasoning, and generating a fault tag sequence and a reasoning path graph; 5) based on the characteristic difference between the inference path diagram and the test excitation sequence, weight parameter updating of the depth generation model is carried out; and 6) generating a test excitation sequence based on the updated depth generation model to test the memory. The intelligent level and the test coverage rate of the memory test can be effectively improved.

The invention discloses a memory read-write consistency testing method and system, and relates to the technical field of memory testing. Comprising the steps of S1, performing crosstalk coupling modeling: constructing an interlayer crosstalk coupling transfer function according to a quantum tunneling current curve and a three-dimensional parasitic parameter matrix; s2, constructing a three-dimensional failure probability model: obtaining a plane coupling error distribution diagram, and generating an interlayer crosstalk coefficient matrix according to the interlayer crosstalk coupling transfer function; and S3, identifying electromagnetic coupling hot spot regions: determining a risk level of each region according to the three-dimensional failure probability, setting test parameters according to the risk levels, and performing read-write test on the to-be-tested memory through the test parameters. According to the method, three-dimensional quantitative modeling of cross-layer interference is realized, so that the detection range is expanded from a plane to a three-dimensional structure, and a blind area of interlayer electromagnetic coupling in a traditional method is solved.

The invention discloses a memory test system and method, a board card and a server. The memory test system comprises an out-of-band management unit and a target chip, the out-of-band management unit sends a pressure test instruction to the target chip through the preset communication interface, the pressure test instruction comprises dynamically adjusted test strength parameters, and the pressure test instruction is generated based on a preset instruction set; the target chip performs calibration verification on the target memory in response to the pressure test instruction; after the calibration verification is passed, a test load is applied to the target memory according to the test strength parameter, and a cyclic pressure test is executed; the target chip collects test data generated in the pressure test process and transmits the test data back to the out-of-band management unit through the preset communication interface, and the out-of-band management unit generates structured test data according to the test data. Compared with the prior art, the situation that normal services are interrupted due to testing in a traditional testing method can be avoided, and the availability and stability of the system in the testing process are guaranteed.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The embodiment of the invention provides a memory controller, an error address positioning method and a computing system. The memory controller comprises an algorithm control circuit, a data generation circuit, a data comparison circuit and a monitoring circuit, and the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm; the data generation circuit is configured to generate test data used for being written into the memory to be tested and expected data obtained after the test data is read; the data comparison circuit is configured to detect whether target data read from the to-be-detected memory is consistent with expected data or not; and the monitoring circuit is configured to respond to the inconsistency of the read target data and the expected data, send a mark for stopping the memory test to the algorithm control circuit so as to stop the memory test and record a test address corresponding to an error and corresponding command data, so that stop and quick positioning are realized when the error occurs, and the repair efficiency is improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention relates to the technical field of memory test, and provides a test system for a parallel interface NOR FLASH memory, which comprises the following steps of: acquiring verification information of test data of a test data block in a storage area and verification operation in a test process of the NOR FLASH memory, and judging whether the test data block has an error or not; dividing the test data blocks with errors, and determining secondary to-be-analyzed test data blocks; the method comprises the following steps: marking target test data, identifying high-frequency error test data, dividing a secondary to-be-analyzed test data block needing to be adjusted into a tertiary to-be-analyzed test data block, and repeatedly judging and dividing until the data block cannot be continuously divided or the judgment result of the data block is that the data block is not divided, thereby realizing the setting of a block verification mode of a full-step method. And evaluating the durability of the NOR FLASH memory of the parallel interface by using a one-step method. According to the invention, a block verification mode can be adaptively set, and the accuracy of a durability test result is improved.

The invention provides a memory built-in self-test method, a controller and a circuit, and relates to the technical field of memory testing, and the test method comprises the following steps: S1, starting to write 0 in an ascending order from the lowest address; s2, reading 0 for the lowest address, and then writing 1 and reading 1 in an ascending order; s3, reading 1 for the lowest address, and then writing 0 and reading 0 in an ascending order; s4, reading 0 for the lowest address, and then writing 1 in an ascending order; s5, reading 1 for the highest address, and then writing 0 and reading 0 in a descending order; s6, reading 0 for the lowest address, and then writing 0 in an ascending order; s7, reading 0 for the highest address, and then writing 1 and reading 1 in a descending order; and S8, reading 1 from the lowest address in an ascending order. The invention also provides a memory built-in self-test controller and a memory built-in self-test circuit. Based on the newly proposed March-E algorithm, the test speed and the fault coverage rate can be improved and the power consumption can be reduced with relatively low area overhead.

An integrated circuit includes a memory having an array and a memory built-in self test (MBIST) controller. The MBIST controller is configured to perform memory testing rungs on the memory and includes a first counter and a repair control circuit. The first counter is configured to count uncorrectable errors during each memory testing run. The repair control circuit is configured to, in response to an error found during a memory testing run, determine whether at least one of row repair or column repair can be applied to repair the error.

The invention relates to the field of memory testing, and discloses a memory read-write test acceleration system and method and a storage medium. The system comprises a CPU and an SOC chip. The SOC chip comprises a read-write accelerator, a DDR (Double Data Rate) memory controller and a comparator; the CPU is used for continuously outputting a write instruction carrying a target address and target data when a read-write test in the SLT mode is executed; the read-write accelerator is used for sending target data to the comparator and sending a target address to the DDR memory controller when determining that the write instruction is a read instruction, so that the DDR memory controller initiates memory access to the to-be-tested memory to obtain read-back data; and the comparator is used for comparing the read-back data with the target data to obtain a comparison result. When the read-write test of the memory is executed in the SLT test mode, the CPU only issues the write instruction, and the read-write accelerator converts and issues the write instruction, so that the load of the CPU is reduced, and the test efficiency of the memory is improved.

The invention relates to a memory test method and device, computer equipment and a storage medium, a test file is loaded to a to-be-verified memory and a mirror image memory of the to-be-verified memory, and the mirror image memory is located in a local verification environment; synchronously accessing the to-be-verified memory and the mirror image memory based on the operation instruction to respectively obtain first feedback data and second feedback data; comparing the first feedback data with the second feedback data, and determining whether the access path of the to-be-verified memory is normal or not according to a comparison result; and the efficiency and the flexibility of memory testing are improved.

This invention provides a memory testing system, comprising: a host computer; at least one card reader communicatively connected to the host computer, each card reader having a corresponding memory under test (MDT) communicatively connected to it; and a temperature chamber, in which the MDT and the card readers are placed. The host computer controls each MDT to perform a corresponding test and simultaneously controls the temperature chamber to adjust its internal temperature, enabling parallel testing of all MDTs under different ambient temperatures. This memory testing system solves the current technical problem of achieving low-cost and high-efficiency testing for memory.

The invention provides a high-efficiency memory repair system and method based on a pooling memory. The method comprises the following steps: a memory test module performs UCE error address detection on a memory bank by taking cache as granularity; the management module is used for converting the memory error address into a memory page address to which the memory error address belongs, and issuing a repair command for the memory page address; the address routing module replaces and adds a memory page address into a routing table by utilizing a routing table look-up algorithm according to the repair command so as to finish address repair, performs corresponding address conversion according to a repair state of an accessed host memory address, and routes the address to a port where the memory bank or the out-of-band storage module is located; and the out-of-band storage module is an out-of-band memory pool independent of the system memory pool and is used for repairing the damaged memory by taking the memory page as the granularity. According to the method, the effects of improving the utilization efficiency and compatibility of the memory and enhancing the RAS system of the memory are achieved through the high-efficiency memory repair system which is provided with the out-of-band memory module and takes the memory page capable of being dynamically configured as the granularity.

Various embodiments provide for estimating power consumption by one or more memory components of a circuit design during memory testing, which can be used as part of an electronic design automation (EDA) software.

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

The utility model relates to the technical field of memory bank testing, and provides a memory testing temperature control mechanism which comprises a housing used for covering a testing mainboard, the housing is divided into a plurality of temperature control areas which are in one-to-one correspondence with and matched with slot areas of the testing mainboard, and a temperature control assembly used for providing temperature conditions is arranged in each temperature control area. The temperature control assembly comprises a temperature control substrate, a plurality of TEC temperature control sheets and a plurality of temperature control fins, one functional surface of each TEC temperature control sheet is attached to the temperature control substrate, the plurality of temperature control fins are arranged in parallel, and a space between every two adjacent temperature control fins is a temperature control grid used for accommodating a memory bank during testing; integrated refrigeration / heating is achieved through the TEC temperature control pieces, the temperature in the temperature control grid is correspondingly controlled to be the target temperature, the temperature condition is provided for memory bank testing, the structure is simple, the space occupancy rate is small, and therefore the testing space layout is optimized.

The present invention discloses a hierarchical testing method for three-dimensional stacked memories, which relates to the technical field of memory testing. Initialize each memory layer where the three-dimensional stacked memory is located. According to the structural type of the memory layer, formulate a hierarchical testing mode for the current three-dimensional stacked memory, and test each memory layer of the three-dimensional stacked memory. If a storage anomaly is detected in a certain memory layer, mark it as a memory layer to be inspected in detail, record its storage location and storage type, and perform a global test on the memory layer to be inspected in detail. If no storage anomaly is detected in all memory layers, end the test. According to the test results of the global test, locate all abnormal storage domains of the corresponding memory layer of the three-dimensional stacked memory, and perform diagnosis and repair, thereby converting the abnormal storage domains into normal storage domains.

The invention provides a network security equipment memory test method and device and processing equipment, which are used for constructing a set of standardized and systematized network security equipment memory test architecture, ensuring the scientificity and accuracy of memory test, effectively improving the reliability of test results, and timely finding out memory abnormal conditions. The method has the advantages that problems can be quickly positioned and analyzed, the performance and the stability of the network security equipment can be favorably improved, equipment faults and security risks caused by memory problems can be reduced, the operability and the practicability are high, the method is suitable for memory testing of various network security equipment, and powerful support is provided for research, development and maintenance of the network security equipment.

Embodiments of the present application provide a memory testing device and a memory testing method, which are applied to an electronic device including a first control module and a memory module. The memory testing device includes: a register module for storing test parameters; a second control module for storing a memory test flag; the memory test flag for instructing the first control module to send test initiation information to the second control module; a function selection module for controlling the first control module to be isolated from the memory module and the second control module to be connected to the memory module after the second control module receives the test initiation information, so that the memory testing device is in a test mode; the second control module is further configured to test the memory module according to the test parameters after the memory testing device is in the test mode to obtain a test result. The memory testing device of the embodiments of the present application can improve the efficiency of memory testing.

The invention provides a memory testing method and device. The method comprises the following steps of: after a plurality of crystal grains are idle for a first time, performing a first-stage test on the crystal grains, and setting a plurality of flags corresponding to the crystal grains which do not pass the first-stage test as first logic levels; after the crystal grains are idle for a second time, carrying out a second-stage test on the crystal grains, and taking the crystal grains which pass through the second-stage test and of which the corresponding flags are set to be the first logic level as a plurality of suspected good crystal grains to be idle continuously; and after the suspected good crystal grains are left unused for a third time, third-stage testing is carried out on the suspected good crystal grains.

The present invention provides a memory testing method, system, device, and storage medium. The method includes: obtaining test input data based on the bit width of the memory to be tested; constructing test elements based on the test input data according to preset timing rules; and sequentially executing each test element on the memory to be tested; the preset timing rules satisfy the following conditions: after reading the previous address, writing the current address, the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, and the previous address and the current address are adjacent in both logical address sequence and physical address sequence. By adding test elements with insufficient timing margin, the present invention can prevent missed detection of the memory to be tested, thereby improving the test coverage of the memory testing method, increasing the qualified rate of produced memory, and reducing the user's losses caused by unqualified chips.

The utility model belongs to the field of memory testing, and discloses a memory accurate power consumption testing device which comprises a memory testing mainboard, the memory testing mainboard comprises a memory slot and a power supply module, and the output end of the power supply module is electrically connected with the power supply input end of the memory slot; the sampling end of the current acquisition module is connected in series in a power supply loop between the output end of the power supply module and the power supply input end of the memory slot, and the current acquisition module is used for acquiring the working current of the to-be-tested memory after the to-be-tested memory is inserted into the memory slot; the signal input end of the controller is connected with the signal output end of the current acquisition module, and the controller is used for outputting the total power consumption of the memory to be tested after the working current, acquired by the current acquisition module, of the memory to be tested is input. According to the utility model, the power consumption test accuracy of the memory to be tested is improved.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The present invention discloses a method for generating a March - type algorithm for memory testing. First, a memory access operation state transition descriptor is constructed. Then, the simplest detection sequence corresponding to a fault primitive is determined and a simplest detection sequence table is constructed. Finally, the simplest detection sequences are used to synthesize a March - type algorithm adapted to the fault type: list the faults, find the simplest detection sequences, group them, perform intra - group merging, inter - group merging, splicing to obtain the March - type algorithm, obtain the March - type algorithm with the opposite address increment direction, and finally splice the two parts of the March - type algorithms together to obtain the final March - type algorithm. In this way, a suitable March - type algorithm for a given fault dictionary is obtained, making the use of the March algorithm more flexible.

A method and an apparatus for memory testing are provided. The method includes following steps: after multiple dies are idle for a first time, performing a first stage test on the dies, and setting multiple flags corresponding to the dies that fail the first stage test to a first logic level; after the dies are idle for a second time, performing a second stage test on the dies, and regarding the dies that pass the second stage test and have the corresponding flags set to the first logic level as suspected good dies and keeping the suspected good dies idle; and after the suspected good dies are idle for a third time, performing a third stage test on the suspected good dies.

The invention provides a data acquisition system and a data acquisition method for self-adaptive memory testing, and belongs to the technical field of memory testing. The system comprises a test decision engine built in or connected with a memory test model and an uncertainty evaluation module, the model outputs a memory test strategy and analyzes a test result, and the evaluation module quantifies the confidence of the memory test strategy and identifies a test information demand gap; the dynamic acquisition controller is used for receiving the acquisition request sent by the test decision engine and analyzing the acquisition request into a hardware control instruction; the multi-mode sensor array is used for executing data acquisition of the memory according to the instruction; the edge feature extraction and compression module is used for processing the collected original data in real time and generating a test feature vector; and the data fusion and association database is used for receiving and storing the test feature vectors and uniformly marking timestamps and event tags for the test decision engine to call. According to the method, accurate tracing from logic errors to physical roots is realized, and the memory testing efficiency is improved.

The application discloses a memory test system, and relates to the technical field of computers, which comprises a control device, a first type of network device, second type of network devices, a hardware debugging device and a device to be tested connected with each second type of network device respectively, the control device is connected with each second type of network device through the first type of network device, each second type of network device, the hardware debugging device and the device to be tested corresponding to the second type of network device are in the same local area network, different second type of network devices are in different local area networks, the control device is used for issuing a test task, and a target hardware debugging device is used for adjusting memory test parameters so that a target device to be tested generates a memory test result. Through the application, memory test is simultaneously performed on multiple devices to be tested through the same control device, test efficiency is improved, and the multiple devices to be tested are in different local area networks, so that the test environments of the devices to be tested are independent.

This invention relates to the field of power board heat dissipation technology, specifically disclosing a heat dissipation structure for a high-power power board used in memory testing. The structure includes a water-cooled plate installed between a lower and upper circuit board. A housing is installed outside the lower and upper circuit boards, and a circulating water tank is installed outside the housing. The circulating water tank is connected to the water-cooled plate. Two sets of flow channels are formed within the water-cooled plate, corresponding to the lower and upper circuit boards respectively. Several heat dissipation slots are formed at the top and bottom of the water-cooled plate. An exhaust fan is rotatably installed within each heat dissipation slot. Heat dissipation fins are provided within the heat dissipation slots, close to the flow channels. Several air vents are formed on the water-cooled plate, communicating with the heat dissipation slots. During heat dissipation, the exhaust fan draws heat generated on the upper and lower circuit boards into the heat dissipation slots through airflow. The high-temperature airflow contacts the heat dissipation fins, thereby achieving heat dissipation.

This application discloses a memory testing method and electronic device, relating to the field of memory testing technology. The method includes: dynamically configuring the testing environment based on the serial presence detection parameters of the memory under test, ensuring precise matching of testing criteria with memory specifications, significantly improving the accuracy and relevance of the test; simultaneously, by comparing power supply parameters and serial presence detection parameters in real time, dynamic adjustment of the protection threshold is achieved, which avoids accidental interruptions, ensures test continuity, and can respond promptly to real anomalies, effectively improving testing efficiency and reducing the risk of memory damage.