204 results about "Memory testing" patented technology

The invention discloses a memory test method and device based on an AI technology and a medium, and the method comprises the following steps: 1) obtaining structure analysis data and memory type description information of a to-be-tested memory, and generating a test intention vector used for expressing a test target; 2) taking the test intention vector as an input to generate a test excitation sequence; 3) executing the test excitation sequence, and performing multi-cycle test on the storage array to form a multi-modal response feature set; 4) inputting the multi-modal response feature set into a graph neural network, performing fault type identification and causal path reasoning, and generating a fault tag sequence and a reasoning path graph; 5) based on the characteristic difference between the inference path diagram and the test excitation sequence, weight parameter updating of the depth generation model is carried out; and 6) generating a test excitation sequence based on the updated depth generation model to test the memory. The intelligent level and the test coverage rate of the memory test can be effectively improved.

The invention discloses a memory read-write consistency testing method and system, and relates to the technical field of memory testing. Comprising the steps of S1, performing crosstalk coupling modeling: constructing an interlayer crosstalk coupling transfer function according to a quantum tunneling current curve and a three-dimensional parasitic parameter matrix; s2, constructing a three-dimensional failure probability model: obtaining a plane coupling error distribution diagram, and generating an interlayer crosstalk coefficient matrix according to the interlayer crosstalk coupling transfer function; and S3, identifying electromagnetic coupling hot spot regions: determining a risk level of each region according to the three-dimensional failure probability, setting test parameters according to the risk levels, and performing read-write test on the to-be-tested memory through the test parameters. According to the method, three-dimensional quantitative modeling of cross-layer interference is realized, so that the detection range is expanded from a plane to a three-dimensional structure, and a blind area of interlayer electromagnetic coupling in a traditional method is solved.

The invention discloses a memory test system and method, a board card and a server. The memory test system comprises an out-of-band management unit and a target chip, the out-of-band management unit sends a pressure test instruction to the target chip through the preset communication interface, the pressure test instruction comprises dynamically adjusted test strength parameters, and the pressure test instruction is generated based on a preset instruction set; the target chip performs calibration verification on the target memory in response to the pressure test instruction; after the calibration verification is passed, a test load is applied to the target memory according to the test strength parameter, and a cyclic pressure test is executed; the target chip collects test data generated in the pressure test process and transmits the test data back to the out-of-band management unit through the preset communication interface, and the out-of-band management unit generates structured test data according to the test data. Compared with the prior art, the situation that normal services are interrupted due to testing in a traditional testing method can be avoided, and the availability and stability of the system in the testing process are guaranteed.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The present invention discloses a semiconductor memory test system and test method, which relates to the field of memory test technology. The system includes: a test board for directly inserting at least one semiconductor memory to be tested; a microclimate chamber placed on the test board for regulating the temperature environment of the test board; an offline software / test converter for writing a long vector test mode and downloading it to a vector tester to perform the test; the vector tester includes a controller and a multiplexer, a comparison logic device and a pin electronic device connected in sequence, which are used to generate a test signal according to the downloaded long vector test mode, send the test signal to the corresponding at least one semiconductor memory to be tested, and perform a logical comparison judgment according to the test feedback signal fed back by the semiconductor memory to be tested, so as to obtain the final test result. The present invention can realize semiconductor memory testing with lower cost and higher precision.

The embodiment of the invention provides a memory controller, an error address positioning method and a computing system. The memory controller comprises an algorithm control circuit, a data generation circuit, a data comparison circuit and a monitoring circuit, and the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm; the data generation circuit is configured to generate test data used for being written into the memory to be tested and expected data obtained after the test data is read; the data comparison circuit is configured to detect whether target data read from the to-be-detected memory is consistent with expected data or not; and the monitoring circuit is configured to respond to the inconsistency of the read target data and the expected data, send a mark for stopping the memory test to the algorithm control circuit so as to stop the memory test and record a test address corresponding to an error and corresponding command data, so that stop and quick positioning are realized when the error occurs, and the repair efficiency is improved.

The invention relates to the technical field of memory training, in particular to a memory grading training algorithm and system, and the algorithm comprises the steps: carrying out the memory test of a to-be-trained person, and obtaining a first memory curve; matching the analysis information, the training target and a plurality of algorithm containers to obtain a first algorithm container; performing memory training on the to-be-trained person according to the first algorithm container; testing the trained to-be-trained person to obtain a second memory curve; and updating the first algorithm container according to a comparison result of the first memory curve and the second memory curve. According to the invention, the memory basis and characteristics of each to-be-trained person can be accurately grasped by performing memory analysis on the to-be-trained person. On the basis, the analysis information is matched with the training target and the algorithm container, the first algorithm container is selected for each to-be-trained person, personalized memory training is achieved, the training is more suitable for the personal actual situation, and the pertinence and effectiveness of the training are remarkably improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention provides a memory testing method and device and testing equipment, and is applied to the technical field of integrated circuit manufacturing. The memory testing method comprises the steps that a data writing instruction is responded, the numerical value of one or more target address bits is obtained, the data writing instruction comprises a row address and a column address, and the target address bit is a certain bit of the row address or a certain bit of the column address; determining a target register in one or more registers according to the numerical values of the one or more target address bits, each register pre-storing test data, and different registers storing different test data; and writing the test data in the target register into the storage units corresponding to the row address and the column address. The embodiment of the invention can improve the memory test efficiency.

The invention provides a memory bank testing method and device, equipment and a storage medium, relates to the technical field of computers, is applied to a server, and comprises the following steps: screening a current to-be-tested target address from a preset serial in-place detection address set when a to-be-tested memory bank on a memory slot is tested, the memory slot is controlled to be connected to a current target pull-down resistor corresponding to the current to-be-tested target address through a preset switching chip; testing the compatibility between the memory bank to be tested and the current target address to be tested; if the test is not passed, directly judging that the memory bank to be tested has function abnormality; and if the test is passed, screening out the next current target address to be tested, and skipping to the step of controlling the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested through the preset switching chip until the test is passed, and judging that the function of the memory bank to be tested is normal. Therefore, the memory testing efficiency is improved, and the influence on the service life of the memory is reduced.

The invention relates to the technical field of chip verification, and discloses an RAM (Random Access Memory) test method and device, computer equipment and a storage medium, and the method comprises the following steps: generating a test instruction set by utilizing an error correction function verification platform matched with a to-be-tested RAM; controlling the to-be-tested RAM to execute a corresponding test operation based on the test instruction set, and correcting error data generated in the execution process to obtain a first error correction result; a second error correction result output by a reference model is obtained, and the reference model is a benchmark model which has the same error detection function and error correction function as the RAM to be tested; and analyzing the first error correction result and the second error correction result, and generating a test report of the RAM memory to be tested. According to the invention, the problem of low efficiency caused by repeated environment establishment and test instruction writing during chip EDA verification due to different characteristics of RAM memory function modules is solved.

The invention provides an automatic testing system and method for a memory module, and belongs to the technical field of memory testing. The automatic testing system comprises an automatic feeding and discharging system, a mainboard testing system and a machine testing system which are integrated on the same testing platform; the mainboard test system is used for performing function test or performance test on a memory module installed on a mainboard; the machine test system is used for performing function test or performance test on the memory module installed on the machine; the automatic feeding and discharging system is used for automatically feeding and discharging the memory modules for the mainboard testing system or the machine testing system. According to the invention, the mainboard test and the machine test are carried out on the same test platform, so that on one hand, the test requirements of multiple types of memory modules on the same test platform are met, and on the other hand, the requirements of multiple function tests and performance tests of the memory modules on the same test platform are met; and the test platform does not need to be frequently replaced, thereby facilitating test operation.

The invention relates to the technical field of memory test, and provides a test system for a parallel interface NOR FLASH memory, which comprises the following steps of: acquiring verification information of test data of a test data block in a storage area and verification operation in a test process of the NOR FLASH memory, and judging whether the test data block has an error or not; dividing the test data blocks with errors, and determining secondary to-be-analyzed test data blocks; the method comprises the following steps: marking target test data, identifying high-frequency error test data, dividing a secondary to-be-analyzed test data block needing to be adjusted into a tertiary to-be-analyzed test data block, and repeatedly judging and dividing until the data block cannot be continuously divided or the judgment result of the data block is that the data block is not divided, thereby realizing the setting of a block verification mode of a full-step method. And evaluating the durability of the NOR FLASH memory of the parallel interface by using a one-step method. According to the invention, a block verification mode can be adaptively set, and the accuracy of a durability test result is improved.

The invention provides a memory testing method. The memory testing method comprises the step of performing repeated addressing testing on a memory based on an intrinsic initial value of the memory. According to the memory testing method provided by the invention, the problems that all addressing faults cannot be detected by an existing fault testing method with a simple algorithm and the fault testing method with a complex algorithm needs too many testing vectors and the testing time is too long are solved.

The invention provides a depth evaluation method and system for an on-die ECC (Error Correction Code) memory, and the method and system for depth evaluation for the on-die ECC memory are characterized in that an ECS (Error Correction System) is introduced to record the number of actual repairs and errors in the memory; the method comprises the following steps: performing multi-round cyclic ECS test on an on-die ECC memory according to gradually-rigorous test parameters by opening and closing a manual ECS mode of the on-die ECC memory so as to obtain a fault frequency evolution table; and comparing the fault frequency evolution table with a pre-obtained natural test fault table of the on-die ECC memory to obtain the test parameter margin of the on-die ECC memory, the maximum tolerable fault number and the residual percentage of the maximum tolerable fault number, so that the real evaluation condition of the on-die ECC memory is reflected, the condition of test distortion caused by ECC self-repairing is avoided, and the test efficiency is improved. And the accuracy and authenticity of memory testing are improved.

The invention provides a memory built-in self-test method, a controller and a circuit, and relates to the technical field of memory testing, and the test method comprises the following steps: S1, starting to write 0 in an ascending order from the lowest address; s2, reading 0 for the lowest address, and then writing 1 and reading 1 in an ascending order; s3, reading 1 for the lowest address, and then writing 0 and reading 0 in an ascending order; s4, reading 0 for the lowest address, and then writing 1 in an ascending order; s5, reading 1 for the highest address, and then writing 0 and reading 0 in a descending order; s6, reading 0 for the lowest address, and then writing 0 in an ascending order; s7, reading 0 for the highest address, and then writing 1 and reading 1 in a descending order; and S8, reading 1 from the lowest address in an ascending order. The invention also provides a memory built-in self-test controller and a memory built-in self-test circuit. Based on the newly proposed March-E algorithm, the test speed and the fault coverage rate can be improved and the power consumption can be reduced with relatively low area overhead.

An integrated circuit includes a memory having an array and a memory built-in self test (MBIST) controller. The MBIST controller is configured to perform memory testing rungs on the memory and includes a first counter and a repair control circuit. The first counter is configured to count uncorrectable errors during each memory testing run. The repair control circuit is configured to, in response to an error found during a memory testing run, determine whether at least one of row repair or column repair can be applied to repair the error.

The invention relates to the field of memory testing, and discloses a memory read-write test acceleration system and method and a storage medium. The system comprises a CPU and an SOC chip. The SOC chip comprises a read-write accelerator, a DDR (Double Data Rate) memory controller and a comparator; the CPU is used for continuously outputting a write instruction carrying a target address and target data when a read-write test in the SLT mode is executed; the read-write accelerator is used for sending target data to the comparator and sending a target address to the DDR memory controller when determining that the write instruction is a read instruction, so that the DDR memory controller initiates memory access to the to-be-tested memory to obtain read-back data; and the comparator is used for comparing the read-back data with the target data to obtain a comparison result. When the read-write test of the memory is executed in the SLT test mode, the CPU only issues the write instruction, and the read-write accelerator converts and issues the write instruction, so that the load of the CPU is reduced, and the test efficiency of the memory is improved.

The invention relates to a memory test method and device, computer equipment and a storage medium, a test file is loaded to a to-be-verified memory and a mirror image memory of the to-be-verified memory, and the mirror image memory is located in a local verification environment; synchronously accessing the to-be-verified memory and the mirror image memory based on the operation instruction to respectively obtain first feedback data and second feedback data; comparing the first feedback data with the second feedback data, and determining whether the access path of the to-be-verified memory is normal or not according to a comparison result; and the efficiency and the flexibility of memory testing are improved.

The invention discloses a memory testing method, a memory testing device, a storage medium and electronic equipment, and the memory testing method comprises the steps: traversing each storage unit of a to-be-tested memory, performing data read-write operation on the traversed target storage unit and an adjacent storage unit adjacent to the target storage unit according to a preset advancing rule; performing logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value; if the actual logic relation value is not consistent with the standard logic relation value, it is determined that the to-be-tested memory has a fault, by adopting the method, the fault condition of the memory can be detected through the actual logic relation value, the reliability of a test algorithm is high, meanwhile, the fault coverage rate and the test complexity are both considered, and the fault test efficiency is high.

This invention provides a memory testing system, comprising: a host computer; at least one card reader communicatively connected to the host computer, each card reader having a corresponding memory under test (MDT) communicatively connected to it; and a temperature chamber, in which the MDT and the card readers are placed. The host computer controls each MDT to perform a corresponding test and simultaneously controls the temperature chamber to adjust its internal temperature, enabling parallel testing of all MDTs under different ambient temperatures. This memory testing system solves the current technical problem of achieving low-cost and high-efficiency testing for memory.

A memory testing method and a computer system based on wafer stacking architecture are disclosed. The memory testing method is applied to a computer system based on wafer stacking architecture. The computer system is a three-dimensional wafer product formed by a memory wafer layer, a logic circuit layer and a substrate. When performing memory testing, the memory devices in the memory wafer layer are divided into a plurality of memory sub-blocks, each of which is tested separately. First, a data table is established in one memory sub-block. Then, a plurality of different initial values prepared in advance are provided, and a proof-of-work operation is performed to generate a plurality of operation results corresponding to each initial value by performing multiple read / write operations on the data table. The judgment module obtains the operation results from the operation module and compares them with the corresponding known solutions to calculate the error rate of the tested memory sub-block.

The invention provides a high-efficiency memory repair system and method based on a pooling memory. The method comprises the following steps: a memory test module performs UCE error address detection on a memory bank by taking cache as granularity; the management module is used for converting the memory error address into a memory page address to which the memory error address belongs, and issuing a repair command for the memory page address; the address routing module replaces and adds a memory page address into a routing table by utilizing a routing table look-up algorithm according to the repair command so as to finish address repair, performs corresponding address conversion according to a repair state of an accessed host memory address, and routes the address to a port where the memory bank or the out-of-band storage module is located; and the out-of-band storage module is an out-of-band memory pool independent of the system memory pool and is used for repairing the damaged memory by taking the memory page as the granularity. According to the method, the effects of improving the utilization efficiency and compatibility of the memory and enhancing the RAS system of the memory are achieved through the high-efficiency memory repair system which is provided with the out-of-band memory module and takes the memory page capable of being dynamically configured as the granularity.

Various embodiments provide for estimating power consumption by one or more memory components of a circuit design during memory testing, which can be used as part of an electronic design automation (EDA) software.

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

The utility model relates to the technical field of memory bank testing, and provides a memory testing temperature control mechanism which comprises a housing used for covering a testing mainboard, the housing is divided into a plurality of temperature control areas which are in one-to-one correspondence with and matched with slot areas of the testing mainboard, and a temperature control assembly used for providing temperature conditions is arranged in each temperature control area. The temperature control assembly comprises a temperature control substrate, a plurality of TEC temperature control sheets and a plurality of temperature control fins, one functional surface of each TEC temperature control sheet is attached to the temperature control substrate, the plurality of temperature control fins are arranged in parallel, and a space between every two adjacent temperature control fins is a temperature control grid used for accommodating a memory bank during testing; integrated refrigeration / heating is achieved through the TEC temperature control pieces, the temperature in the temperature control grid is correspondingly controlled to be the target temperature, the temperature condition is provided for memory bank testing, the structure is simple, the space occupancy rate is small, and therefore the testing space layout is optimized.

The present invention discloses a hierarchical testing method for three-dimensional stacked memories, which relates to the technical field of memory testing. Initialize each memory layer where the three-dimensional stacked memory is located. According to the structural type of the memory layer, formulate a hierarchical testing mode for the current three-dimensional stacked memory, and test each memory layer of the three-dimensional stacked memory. If a storage anomaly is detected in a certain memory layer, mark it as a memory layer to be inspected in detail, record its storage location and storage type, and perform a global test on the memory layer to be inspected in detail. If no storage anomaly is detected in all memory layers, end the test. According to the test results of the global test, locate all abnormal storage domains of the corresponding memory layer of the three-dimensional stacked memory, and perform diagnosis and repair, thereby converting the abnormal storage domains into normal storage domains.

The invention provides a network security equipment memory test method and device and processing equipment, which are used for constructing a set of standardized and systematized network security equipment memory test architecture, ensuring the scientificity and accuracy of memory test, effectively improving the reliability of test results, and timely finding out memory abnormal conditions. The method has the advantages that problems can be quickly positioned and analyzed, the performance and the stability of the network security equipment can be favorably improved, equipment faults and security risks caused by memory problems can be reduced, the operability and the practicability are high, the method is suitable for memory testing of various network security equipment, and powerful support is provided for research, development and maintenance of the network security equipment.

Embodiments of the present application provide a memory testing device and a memory testing method, which are applied to an electronic device including a first control module and a memory module. The memory testing device includes: a register module for storing test parameters; a second control module for storing a memory test flag; the memory test flag for instructing the first control module to send test initiation information to the second control module; a function selection module for controlling the first control module to be isolated from the memory module and the second control module to be connected to the memory module after the second control module receives the test initiation information, so that the memory testing device is in a test mode; the second control module is further configured to test the memory module according to the test parameters after the memory testing device is in the test mode to obtain a test result. The memory testing device of the embodiments of the present application can improve the efficiency of memory testing.