43results about How to "Development period" patented technology

The present invention relates to a dual zone type air conditioner for vehicles, which includes two air volume controlling doors mounted on an air inflow port of an air-conditioning case where the cross section of an air passageway is uniform and a flow of air is relatively uniform, a sealing wall mounted between the air volume controlling doors, and a controlling part mounted for selecting a more air volume side as a level of a blower when an air volume set by a driver and an air volume set by a passenger are different from each other and controlling the air volume controlling doors to supply the set air volumes to a driver's seat side and a passenger's seat side.

An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.

An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch circuit connects the output of the input circuit to the one end of the evaluation wiring. A third switch circuit connects the other end of the evaluation wiring to the input of the latch circuit. By turning on, off, and off the first to third switch circuits, respectively, the output of the input circuit is directly connected to only the input of the latch circuit. In this state, the input circuit writes an expected value, and a logic level is read from the latch circuit. Accordingly, failure of the evaluation wiring can be easily discriminated from other failure.

Whether a safety function unit having a safety function of a desired standard is correctly mounted in a safety device having a configuration in which a basic control function and safety function are separated is accurately determined. The safety device includes a controller and the safety function unit. The controller is provided with a unit which selects a category for identifying a safety function unit which should be connected, a unit which transmits a reference signal to the safety function unit, a unit which determined, based on a category identification signal returned from the safety function unit, whether or not the category of the connected safety function unit coincides with a selected category, and a unit which, in the event that the result of the determination is such that the category of the connected safety function unit and the selected category do not coincide, prohibits the output of a control signal. The safety function unit is provided with a unit which, based on the reference signal transmitted from the controller, generates the category identification signal in accordance with a process appropriate to the category of the safety function unit, and returns it to the controller.

Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.

In order to provide a built-in self testing function, a one-chip microcomputer is equipped with an activation register for activating the test operation and a built-in self test activation pattern generator for setting initial values at test control circuits (pseudo random number generator, logical circuit testing compressor, pattern generator, and memory testing compressor). In accordance with an instruction from the CPU, a built-in self test is activated so that the results of tests of the memory and the group of logical circuits are read from the memory testing compressor and the logical circuit testing compressor, and respectively compared with expected values preliminarily stored in the memory in the one-chip microcomputer; thus, the results are diagnosed. Thus, it is possible to carry out a built-in self test without using a plurality of exclusively-used test terminals.

In lower hierarchy design in which a plurality of circuit blocks are independently designed, a reset adjustment circuit propagating deactivation transition of a reset signal to flip-flops in synchronization with a clock signal is inserted immediately after a reset input pin in each circuit block, and timing adjustment using the clock signal as a reference is implemented for signal paths of the reset signal from the reset adjustment circuit to the flip-flops. In upper hierarchy design in which an entire semiconductor integrated circuit is designed, timing adjustment using the clock signal as a reference is implemented for signal paths of the reset signal, according to setup times and hold times of the reset signal that are prescribed respectively for the reset input pins of the circuit blocks.

To provide a sensitive antenna with simple pattern, there is provided an antenna comprising: a core-side element connected to a core-side feed point; and a ground-side element connected to a ground-side feed point, wherein: the core-side element extends from the core-side feed point in a predetermined direction; the ground-side element includes: a first element which is connected to the ground-side feed point and extends in parallel to the core-side element; and a second element which is connected to the ground-side feed point and extends in parallel to the first element; and the first element is located close to a body flange to capacitively couple with the body flange.

An accepting unit (110) accepts various parameters required to create a program from a setting apparatus (500) through a network. A producing unit (112) loads a model of a program code from a model storing unit (128) on the basis of the parameters and replaces a part of the program code with the parameters to produce a source code. An instructing unit (120) detects that the producing unit (112) produces the source code to start a compiling unit (114). The compiling unit (114) compiles the source code produced by the producing unit (112) to create a research program. In this manner, a research program can be automatically created without advanced special knowledge.

An accepting unit (110) accepts various parameters required to create a program from a parameter managing unit (109). A producing unit (112) loads a model of a program code from a model storing unit (128) on the basis of the parameters and replaces a part of the program code with the parameters to produce a source code. An instructing unit (120) detects that the producing unit (112) produces the source code to start a compiling unit (114). The compiling unit (114) compiles the source code produced by the producing unit (112) to create a research program. In this manner, a research program can be automatically created without advanced special knowledge.

An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

An information processing apparatus includes: an operation unit which receives an operation; a first detection unit which detects a direction of the operation unit; an input and output conversion unit which converts an input of the operation received by the operation unit into an output based on a first regulation, when the direction of the operation unit is in a first state, and converts the input into an output based on a second regulation which is different from the first regulation, when the direction of the operation unit is in a second state; a second detection unit which detects an apparatus state which is at least one of a position and a direction of the information processing apparatus; and a control processing unit which performs a control process of the information processing apparatus, based on the output from the input and output conversion unit and the apparatus state.

An accepting unit (110) accepts various parameters required to create a program from a parameter managing unit (109). A producing unit (112) loads a model of a program code from a model storing unit (128) on the basis of the parameters and replaces a part of the program code with the parameters to produce a source code. An instructing unit (120) detects that the producing unit (112) produces the source code to start a compiling unit (114). The compiling unit (114) compiles the source code produced by the producing unit (112) to create a research program. In this manner, a research program can be automatically created without advanced special knowledge.

A data processing system includes a general-purpose data processing unit (PU) including an instruction issuing unit that fetches and decodes an instruction in a program and issues the instruction and an execution unit that executes general-purpose processing according to a general-purpose instruction in the program; a special-purpose data processing unit (VU), including a data path unit for special-purpose data processing, that executes special-purpose data processing according to a special-purpose instruction in the program; and a first clock supply unit for stopping, based on a wait signal that is issued by the VU and shows that the PU is waiting for processing of the VU, a first clock signal for a part of the PU.

The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus comprises an input information storage unit 1 that stores input information, an analytic model creation unit 12 that creates an analytic model of an electronic circuit on the basis of the input information, an analysis unit 3 that calculates an analysis result of the electronic circuit using the analytic model, a partial model reliability value database 21 that defines the accuracy of each part of the analytic model and stores the accuracy value as a partial model reliability value, a partial model influence database 22 that defines the magnitude of influence of each part of the analytic model and stores the influence value as a partial model influence, a reliability value evaluation unit 23 that calculates an analysis result reliability value, i.e. the reliability value of the analysis result, on the basis of the partial model reliability value and partial model influence, an analysis result determination unit 14 that determines whether the analysis result is good or bad, and a display unit 15 that displays the analysis result reliability value and the result of the good / bad determination.

There is disclosed a sound source separating apparatus (100) including: a sound pressure detecting unit which detects a sound pressure in which fluid sound generated due to fluctuations in fluid pressure and oscillation sound generated due to oscillation of a solid are mixed; an oscillation detecting unit (2) which detects oscillation of the solid; and a sound source separating unit (3) which separates the sound pressure detected by the sound pressure detecting unit into a fluid sound component and an oscillation sound component for output by using the sound pressure detected by the sound pressure detecting unit and the oscillation detected by the oscillation detecting unit (2). By separating into the fluid sound and the oscillation sound, it is possible to effectively and rapidly implement oscillation and noise control and reduce a development period of a noise-free product.

In lower hierarchy design in which a plurality of circuit blocks are independently designed, a reset adjustment circuit propagating deactivation transition of a reset signal to flip-flops in synchronization with a clock signal is inserted immediately after a reset input pin in each circuit block, and timing adjustment using the clock signal as a reference is implemented for signal paths of the reset signal from the reset adjustment circuit to the flip-flops. In upper hierarchy design in which an entire semiconductor integrated circuit is designed, timing adjustment using the clock signal as a reference is implemented for signal paths of the reset signal, according to setup times and hold times of the reset signal that are prescribed respectively for the reset input pins of the circuit blocks.

A method of designing a machine on which a drive motor, a fuel cell stack, and a secondary battery are mounted includes: determining a maximum output of the drive motor to be a first output value and an output of the drive motor when a vehicle travels under a cruise condition to be a second output value; determining the number of fuel cell stacks to be mounted to be n; and determining a maximum output of the secondary battery to be a value obtained by subtracting a value obtained by multiplying a maximum output of the fuel cell stack by the n, from the first output value. A value obtained by multiplying the third output value by the n is equal to or larger than the second output value, and a value obtained by multiplying the third output value by (n−1) is less than the second output value.

The invention proposes a method for managing random access memory in a computer system, with said computer system comprising a processor, a first static random access memory, and a second dynamic random access memory, the method comprising the steps of:—receiving at least one instruction to be executed by the processor,—determining a priority level for the execution of the instruction by the processor, and—loading the instruction into the first memory for its execution by the processor if its priority level indicates that it is a high priority instruction, or if not—loading the instruction into the second memory for its execution by the processor.

The present invention relates to a method of selecting high producer clones by using an expression vector, the expression vector comprising: (i) a gene expression cassette comprising a selectable marker gene to which polyA has been inoperably linked; and (ii) a gene expression cassette which encodes a recombinant protein of interest and to which polyA has been operably linked. According to the invention, high producer clones can be selected from cell populations at least 10 times fewer than in the existing methods of selecting cell lines. Particularly, high producer clones can be selected using a low concentration of MTX compared to a conventional stepwise gene amplification strategy which comprises carrying out multiple amplification steps while increasing the concentration of MTX. Accordingly, the development period of cell lines can be shortened and the labor and cost required for selection of high-productivity cell clones can be reduced, whereby more efficient production of proteins is possible even when general selectable marker genes other than MTX are used.

In order to cancel an offset caused by a variation of a signal inputted from an optical pickup, variations of elements in an integrated circuit, etc., a calibration circuit which generates and feeds back an offset adjustment amount that makes the offset zero by a comparison with a reference value, and an offset adjustment circuit that makes the offset zero using the fed-back control signal are provided in an analog front-end LSI. The offset adjustment by the calibration circuit is automatically done in response to commands supplied from a digital signal processing LSI, a host control device, etc. On the other hand, as for a signal on which arithmetic processing such as gain control, addition and subtraction, is performed, the offset adjustment is performed by sending the offset adjustment amount obtained by an arithmetic operation performed by software processing of the digital signal processing LSI to the analog front-end.

A climate management system for a power supply system including a plurality of cabinets is disclosed. The climate management system comprises a plurality of climate control units connected and in communication with each other, wherein each climate control unit is disposed in a corresponding cabinet to monitor, manage and control the corresponding cabinet, wherein one of the climate control units is defined as a master climate control unit and the other of the climate control units are defined as slave climate control units; and a control system unit connected and in communication with the master climate control unit. The master climate control unit is configured to collect, process and integrate the information transmitted from the slave climate control units and report the collected, processed and integrated information to the control system unit.

Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch circuit connects the output of the input circuit to the one end of the evaluation wiring. A third switch circuit connects the other end of the evaluation wiring to the input of the latch circuit. By turning on, off, and off the first to third switch circuits, respectively, the output of the input circuit is directly connected to only the input of the latch circuit. In this state, the input circuit writes an expected value, and a logic level is read from the latch circuit. Accordingly, failure of the evaluation wiring can be easily discriminated from other failure.

Inner panels including at least one built-in heat pipe connected in a circumferential direction are provided. In a heat pipe panel including the built-in heat pipe, apparatuses are mounted on the outer side of the plural inner panels connected in the circumferential direction to diffuse generated heat of the apparatuses to the circumferential direction of the inner panels. Webbed panels including a built-in heat pipe horizontally arranged and having heat radiation surfaces are radially arranged at corners of the inner panels as well as a heat pipe is horizontally built in and heat radiation surfaces are arranged also on outer panels facing the inner panels to thermally connect the heat pipes to one another.

Blower, including a housing having a cavity, a wind wheel, a motor, an air inlet, and an air outlet. The housing and the wind wheel are made of steel plates, enamel materials are coated on surfaces of the steel plates, the wind wheel is disposed in the cavity of the housing, the air inlet is disposed at the bottom of the housing, and the air outlet is disposed on one side of the housing in a radial direction. The blower is capable of operating under a high-temperature (below 100° C.) and high-humidity environment, and features simple structure, easy manufacturing and low production cost.