5results about "Microprogram loading" patented technology

A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Techniques and mechanisms for communicating information between clusters of a processor. In an embodiment, a processor core comprises circuitry to identify a condition wherein a first micro-operation (uop) of a uop sequence is to produce a value of an operand, a second uop of the uop sequence is to use the value of the operand, and different respective clusters of processor resources are to execute the first uop and the second uop. Based on the condition, the processor core supplements a strand of uops with a cross-cluster communication uop, wherein the strand comprises one of the first uop or the second uop. In another embodiment, one of the clusters executes the cross-cluster communication uop to provide a value of the operand to another cluster via a cross-cluster network.

Computer device (100) comprising the following: a primary printed circuit board (110); one or more computer components mounted on the primary printed circuit board (110); a Baseboard Management Controller (140), hereinafter referred to as BMC, which is mounted on the primary printed circuit board (110); a power subsystem with a power controller (151) comprising a first logic pin (138); and a logic device (150) coupled to the primary circuit board (110) and connected to the first logic pin (138), wherein the logic device (150) is configured to program the power controller (151) by placing the power controller (151) into a programming mode and inputting programming information into the power controller (151) via the first logic pin (138), wherein the power subsystem comprises a voltage regulator (130), hereinafter referred to as VR, attached to the primary circuit board (110), the VR (130) comprising a VR converter (131) configured to supply electrical power to one of the computer components, and a VR controller (135) configured to control the VR converter (131), and the power controller (151) includes the VR controller (135).

The application discloses a controller, a program execution method and an electronic device, and belongs to the technical field of integrated circuit design. A first storage area of the controller is configured to store first instruction codes of an application program, the first instruction codes include at least one target function position, a function at the target function position is a function to be updated, and a function pointer corresponding to the function to be updated is further configured at the target function position. A processor of the controller is configured to acquire second machine codes, store the second machine codes in a second storage area, and the second machine codes are results after the function to be updated at the at least one target function position is updated. The first machine codes are executed, and in the case that the first machine codes are executed to the target function position, the second machine codes in the second storage area matched with the function pointer are executed according to the function pointer at the target function position. Therefore, the flexibility of program updating can be improved.

Embodiments of a processor for MAD training comprise: decode circuitry to decode instructions into uops, including a plurality of load and store uops; memory execution circuitry executes the plurality of load uops to load data from a memory subsystem and to execute the plurality of store uops to store data to the memory subsystem; and memory alias disambiguation (MAD) prediction circuitry to make a prediction as to whether a first load uop of the plurality of load uops can be executed prior to execution of a first one or more store uops of the plurality of store uops without causing a conflict, the MAD circuitry to make the prediction based on first prediction circuitry when a first confidence value indicated by the first prediction circuitry is above a threshold and to make the prediction based on second prediction circuitry when the first confidence value is at or below the threshold.