22results about "Microprogram loading" patented technology

The utility model discloses a serial port burning circuit, which comprises an MCU (Microprogrammed Control Unit) module, a serial port communication module and a conversion module, two ends of the conversion module are respectively connected with the serial port communication module and the MCU module; the serial port communication module is also connected to the MCU module; the conversion module is used for controlling the MCU module to be switched between a burning state and a working state; and the serial port communication module is used for receiving a control signal from an external communication interface so as to control the conversion module according to the control signal, and is used for transmitting burning information to the MCU module in a burning state. According to the serial port burning circuit, convenient switching between a burning state and a working state is realized through division and cooperation of the conversion module and the serial port communication module, the circuit state does not need to be changed by manually pulling pins with pliers, the burning stability and safety are improved, and the burning efficiency is improved.

The application discloses a data processing device and a data processing method, the data processing device comprises: at least two processing cores; a synchronous scheduler, configured to generate and send a configuration signal in response to a program update signal of each processing core connected to the synchronous scheduler; and a direct memory access controller, configured to read a program corresponding to each processing core from an external storage unit based on the configuration signal and send the program to the corresponding processing core. On the one hand, the data processing device provided by the embodiment of the application does not need the processing core to read data from the external storage unit, avoids the delay caused by the reading of data by multiple processing cores, and improves the computing power of the chip. On the other hand, the data processing device provided by the embodiment of the application can flexibly allocate tasks and fully exert the computing power of each processing core to further improve the computing power of the chip, since the programs executed by each processing core can be the same or different and the updating of the programs of multiple processing cores is responded by the synchronous scheduler.

Novel systems and methods for canvas sanitization are provided. In various embodiments, a system and method include: receiving a request to open a web page from a client device; replacing, via an agent, a first function with a second function, the agent being loaded to a browser; loading the web page from a web server to the browser; in response to an attempt to perform the first function on the web page, performing, via the browser, the second function corresponding to the first function to generate a drawing for a predetermined period of time; converting, via the agent, the drawing to an image; and transmitting the image to the client device. Other aspects, embodiments, and features are also claimed and described.

A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Systems and methods provide native browser features in Cloud Browser Isolation (CBI) environments. In various embodiments, steps include initiating a Cloud Browser Isolation (CBI) session between a user device and a remote browser; receiving one or more inputs from the user device for performing one of a plurality of native browser functions; and performing the native browser function based on the one or more inputs received from the user device. Supported native browser features include find in page functionality, right click, print, and zoom.

The present disclosure provides an instruction transmitting unit, an instruction executing unit, related devices and methods. The instruction transmitting unit comprises: an instruction splitter configured to split a vector instruction to be executed into micro-instructions; a micro-instruction index obtainer configured to obtain an effective element number index of the micro-instruction based on an element range involved by the split micro-instruction; an index comparison subunit configured to compare the obtained effective element number index with a first index, the first index being an effective element number index of a fault-only-first micro-instruction which has not been processed completely; and a micro-instruction transmitting controller configured to transmit the split micro-instruction to a vector executing unit for execution in a case where the effective element number index is smaller than the first index. The present disclosure improves the running efficiency of subsequent vector instructions when a fault-only-first vector load instruction is involved in chain execution.

The present invention relates to a method for modifying memory contents of a main memory (1) of a microcontroller without a separate memory management unit, wherein a part of the main memory (1) is occupied by a base firmware (2). The method according to the invention is characterized in that when the base firmware (2) is introduced into the main memory (1), at least one component block (3) is written into the main memory (1) together, the component block (3) comprising code elements and memory management information for providing at least one firmware component and / or at least one application program component, and in that in order to modify at least a part of the code elements of the at least one component block (3), a processor of the microcontroller processes the memory management information and writes the written information into a location in the main memory (1) defined by the memory management information, and the memory management information of the modified component block (3) is updated.

A mobile terminal, a power adapter, and an upgrade method are disclosed. The method includes: downloading firmware upgrade information data of the power adapter by a mobile terminal; and sending the firmware upgrade information data to a processor of the power adapter by the mobile terminal through a data line in a charging port when the mobile terminal is coupled to the power adapter through the charging port to facilitate the processor to upgrade the firmware of the power adapter according to the firmware upgrade information data. The mobile terminal downloads the firmware upgrade information data, and the most updated firmware upgrade information data is transmitted to the power adapter during the process that the mobile terminal connects to the power adapter, the power adapter is upgraded to solve the problem that the power adapter is difficult to upgrade.

Techniques and mechanisms for communicating information between clusters of a processor. In an embodiment, a processor core comprises circuitry to identify a condition wherein a first micro-operation (uop) of a uop sequence is to produce a value of an operand, a second uop of the uop sequence is to use the value of the operand, and different respective clusters of processor resources are to execute the first uop and the second uop. Based on the condition, the processor core supplements a strand of uops with a cross-cluster communication uop, wherein the strand comprises one of the first uop or the second uop. In another embodiment, one of the clusters executes the cross-cluster communication uop to provide a value of the operand to another cluster via a cross-cluster network.

Systems and methods are disclosed for macro-op fusion in pipelined architectures. For example, some methods include detecting a sequence of macro-ops stored in an instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op; determining a micro-op that is equivalent to the first macro-op combined with the last macro-op; and forwarding the micro-op to one or more execution resource circuitries for execution.

Computer device (100) comprising the following: a primary printed circuit board (110); one or more computer components mounted on the primary printed circuit board (110); a Baseboard Management Controller (140), hereinafter referred to as BMC, which is mounted on the primary printed circuit board (110); a power subsystem with a power controller (151) comprising a first logic pin (138); and a logic device (150) coupled to the primary circuit board (110) and connected to the first logic pin (138), wherein the logic device (150) is configured to program the power controller (151) by placing the power controller (151) into a programming mode and inputting programming information into the power controller (151) via the first logic pin (138), wherein the power subsystem comprises a voltage regulator (130), hereinafter referred to as VR, attached to the primary circuit board (110), the VR (130) comprising a VR converter (131) configured to supply electrical power to one of the computer components, and a VR controller (135) configured to control the VR converter (131), and the power controller (151) includes the VR controller (135).

The invention discloses a hardware upgrading method of a server, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, and the method comprises the following steps: determining to-be-upgraded second hardware in a plurality of pieces of first hardware through a first file used for upgrading the first hardware, and upgrading the second hardware after the second hardware is upgraded. In the embodiment of the invention, only the power pack connected with the second hardware is controlled to carry out power-off reset on the server, so that the problem of service interruption caused by restarting after the whole server is powered off can be effectively avoided, and the technical problem that the system availability is reduced due to the fact that the running continuity of the server is damaged by upgrading operation is solved; the technical effects of ensuring normal operation of other non-upgraded hardware of the server while completing the upgrading of the first hardware, realizing non-stop online upgrading and improving the reliability of the server are achieved.

Examples described herein relate to computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: access a kernel source written in a shading language; select a compiler from a plurality of compilers based on the shading language; generate a kernel instruction set architecture and an associated runtime binding based on the kernel source and the selected compiler; and adapt state information to configure a graphics processing unit (GPU) based on the runtime binding to target any API runtime of choice.

According to one embodiment of the present disclosure, a semiconductor system may be disclosed. The semiconductor system according to the one embodiment may include, for example, a plurality of electronic devices and a host apparatus. The host apparatus may simultaneously initialize the plurality of electronic devices in units of group.

Systems and methods are disclosed for macro-op fusion in pipelined architectures. For example, some methods include detecting a sequence of macro-ops stored in an instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op; determining a micro-op that is equivalent to the first macro-op combined with the last macro-op; and forwarding the micro-op to one or more execution resource circuitries for execution.

Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

An arrangement includes a matrix with a plurality of programmable logic units and a plurality of first one bit clocked storage elements, the programmable logic units and first one bit clocked storage elements being arranged in an array, the arrangement being adapted for sequential execution of at least two tasks, whereby for each of the first one bit clocked storage elements a data store and restore circuit is provided for local storing or restoring the respective values as computed during the tasks per task of the first one bit clocked storage elements;a data memory, external to the matrix, wherein the data store and restore circuit is provided for pre-loading values related to one task from the data memory into the data store and restore circuit and post-storing of values related to one task in the data store and restore circuit to the data memory, whereby the pre-loading and / or post-storing can be performed while another task is executed without disturbing the task execution; andan output circuit, required to ensure safe operation in case of task switching.

The application discloses a controller, a program execution method and an electronic device, and belongs to the technical field of integrated circuit design. A first storage area of the controller is configured to store first instruction codes of an application program, the first instruction codes include at least one target function position, a function at the target function position is a function to be updated, and a function pointer corresponding to the function to be updated is further configured at the target function position. A processor of the controller is configured to acquire second machine codes, store the second machine codes in a second storage area, and the second machine codes are results after the function to be updated at the at least one target function position is updated. The first machine codes are executed, and in the case that the first machine codes are executed to the target function position, the second machine codes in the second storage area matched with the function pointer are executed according to the function pointer at the target function position. Therefore, the flexibility of program updating can be improved.

Embodiments of a processor for MAD training comprise: decode circuitry to decode instructions into uops, including a plurality of load and store uops; memory execution circuitry executes the plurality of load uops to load data from a memory subsystem and to execute the plurality of store uops to store data to the memory subsystem; and memory alias disambiguation (MAD) prediction circuitry to make a prediction as to whether a first load uop of the plurality of load uops can be executed prior to execution of a first one or more store uops of the plurality of store uops without causing a conflict, the MAD circuitry to make the prediction based on first prediction circuitry when a first confidence value indicated by the first prediction circuitry is above a threshold and to make the prediction based on second prediction circuitry when the first confidence value is at or below the threshold.

The invention relates to the field of computers, and discloses a management method of computing equipment and the computing equipment, and the method comprises the following steps: starting a BIOS (Basic Input Output System), and starting a first in-band management module through the BIOS; obtaining an in-band management task through a first in-band management module; under the condition that the in-band management task comprises a first management task which can be executed by the first in-band management module, executing the first management task through the first in-band management module; and when the in-band management tasks are all the first management tasks and the first in-band management module executes the first management tasks, starting an operating system of the computing device through the BIOS. According to the method, the convenience of the management efficiency of the computing equipment can be improved.

Systems, methods, and non-transitory computer readable media configured for launching a micro app associated with a user interface are provided. At least one processor may provide for display a user interface associated with a digital record. The processor may determine an age of the digital record and set a first flag responsive if the age of the digital record exceeds a first threshold and may set a second flag if a first parameter in the digital record is beneath a second threshold. An interactive element may persist until the at least one processor detects a user selection of the interactive element, or the processor determines that the age of the digital record exceeds a third threshold higher than the first threshold. If the age of the digital record exceeds a fourth threshold higher than the third threshold and the second flag remains set, the processor may terminate the digital record.

The invention applies to the context of an electric machine system where the digital control is handled with a FPCU component. This applies to application domains like but not limited to the automotive domain. The invention enables fast and safe time sliced context switching for application tasks mapped in FLU e FPGA matrix, similar as for the task context switching in a microprocessor, with the goal to maximize the usage of all computation resources of the FLU over time.