A SATA controller based on FPGA comprises a
cyclic redundancy check module for executing
cyclic redundancy check calculation on data, a scrambling / descrambling
code module for executing scrambling / descrambling code calculation on data, a frame generating module for finishing the packaging of frame, a frame sending module for controlling the sending, pausing and ending of frame, a frame receiving module for finishing the analysis of frame, a register group for storing the control and state information of the controller, a subscriber interface module for realizing the information and data switching between a processor and the controller, and between a memory and the controller through PLB and NPI interfaces, an out-of-band-
signal control module for controlling the
electricity and hardware resetting process on a rigid disk and founding the
communication link between the controller and the rigid disk, an interface transfer rate select module for automatically selecting the interface transfer rate of the rigid disk, a reset module for generating the reset
signal of each submodule, a
gigabit-grade
transceiver mainly for finishing 8B / 10B coder and decoder, deserializing,
clock amending and the like and an LED indication modular for indicating the working condition of the rigid disk.