35 results about "Hardware reset" patented technology

The application relates to the technical field of network card configuration, and discloses a PCIe reset linkage network card configuration method and device, wherein the method comprises the following steps: listening to change events of a plurality of configuration items, and writing the first configuration state of the configuration item which is changed into a special snapshot storage partition; monitoring a PCIe bus hardware reset signal in real time, and within a hardware time sequence window before a network card chip enters a reset state, forcibly writing full-amount configuration states of the plurality of configuration items into the special snapshot storage partition; after the network card chip completes PCIe reset, reading snapshot data packets and performing validity checking, loading the snapshot data packets which pass the checking into an on-chip SRAM; and respectively performing configuration recovery on each functional module in the network card, and the total time length of the configuration recovery does not exceed a preset time length, so that the technical problems that configuration saving depends on a host operating system and a drive and configuration is completely lost in an uncontrollable reset scene in the prior art are solved.

Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

According to an embodiment, a storage device (204) may comprise at least one processor (223) and a memory (231) for storing instructions. According to an embodiment, the instructions may be configured to, when executed individually or collectively by the at least one processor, cause the storage device to: identify whether a time for storing error-related information generated in the storage device is set in a state in which power supplying from a host device (201) is maintained after a signal for hardware reset is received from the host device (201); and when the time for storing the error-related information is set, store the error-related information in a designated area of the memory within the time for storing the error-related information, and then perform an initialization operation within an initialization time.

The utility model discloses a reset circuit and image forming device, overcome the defect that communication cannot be recovered after communication failure in high speed transmission in the prior art. The reset circuit includes main control chip and memory, and the reset pin of main control chip is connected the reset pin of memory through reset line, when main control chip and memory communication anomaly, main control chip passes through reset line and outputs reset signal to memory, to make main control chip with memory execute reset operation and communicate normally, wherein, reset signal is the first level signal conversion for the second time second level signal of first time, to make main control chip and memory can recover normal communication after communication anomaly through hardware reset mode.

In some implementations, a memory device may receive, from a host device, a hardware reset signal. The memory device may determine that a level associated with the hardware reset signal satisfies a threshold for a period of time. The memory device may determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device. The memory device may complete an ongoing memory operation within a remaining time period based on the determination that the host device is expected to power down the memory device.

This invention specifically relates to a fault location method for distribution lines based on a primary and secondary integrated pole-mounted circuit breaker, falling within the field of distribution line fault detection and location technology. The method includes: after the primary and secondary integrated circuit breaker detects a line fault and trips, it classifies the fault type using edge computing, blocks conventional reclosing, and completes hardware reset and line parameter preloading before distance measurement. In this invention, the phase-selective closing function of the primary and secondary integrated circuit breaker actively injects a standardized high-frequency transient excitation signal, avoiding the randomness problem of the traditional traveling wave method relying on natural fault traveling waves, thus improving the signal-to-noise ratio and feature saliency of the transient signal. Simultaneously, the core of the distance measurement relies on the transient oscillation frequency, which is dominated by the line inductance and capacitance and minimally affected by high-resistance grounding resistance, naturally adapting to high-resistance fault scenarios. Furthermore, the Prony algorithm's accurate extraction of transient parameters and iterative correction strategy for transition resistance solve the problem of large errors in high-resistance scenarios using traditional impedance methods.

The utility model discloses a program control hard reset circuit which comprises an LDO chip U1, a pin Vi of the LDO chip U1 is respectively connected with one end of a resistor R2, one end of a capacitor C1 and a charging interface, a pin CE of the LDO chip U1 is respectively connected with the other end of the resistor R2 and a collector electrode of a triode Q1, and a base electrode of the triode Q1 is respectively connected with one end of a resistor R3, one end of a resistor R6 and an electronic product MCU through a resistor R4. The other end of the resistor R3 is connected with the other end of the capacitor C1, the other end of the resistor R6, an emitting electrode of the triode Q1 and a pin G of the LDO chip U1 are respectively grounded, a pin Vo of the LDO chip U1 is connected with an electronic product MCU and outputs a power supply VCC to supply power, and whether the electronic product needs to be subjected to hardware reset or not when the electronic product is inserted into a USB charging line to be charged is determined according to the input or output state of an IO port CRTRST of the electronic product MCU. The stability of the product is enhanced, and the user experience is not affected.

The invention provides a method for upgrading IC (integrated circuit) firmware by adopting GPIO (general purpose input / output) interface communication. The method comprises the following steps: initializing GPIO resources, applying and exclusively occupying a specified GPIO pin for simulating a JTAG (joint test action group) interface from an operating system kernel, and performing initialization configuration on the GPIO pin; the target IC reset and upgrade mode enters, and a reset pin of the master control SOC is controlled to execute hardware reset operation on the to-be-upgraded IC on the board level; issuing and burning firmware data; verifying the upgrade data; after the upgrade is completed, the mode is recovered and all firmware data are verified successfully, the instruction is sent to the IC to be upgraded again through the GPIO pin, the JTAG state machine of the IC to be upgraded is driven to exit the upgrade mode, then the reset pin is controlled to reset the IC for the second time, the IC is made to load new firmware and enter the normal working mode, and the upgrade of the IC to be upgraded is completed. The method has the beneficial effect that the GPIO interface can be adopted to simulate the JTAG interface for communication to upgrade the IC firmware.

The invention relates to the technical field of power distribution network relay protection equipment filtering algorithms, and provides a multichannel sampling deadlock abnormity processing method and system, and the method comprises the steps: S1, collecting the electrical quantity data of N channels in real time; s2, performing consistency judgment on the electrical quantity data; s3, judging whether data meeting the consistency condition in the electrical quantity data of the current N channels is normal data or not, automatically triggering ADC hardware reset when the data is abnormal, and forcibly recovering a channel non-switching function caused by interference; s4, during a reset period, based on historical electrical quantity data and steady-state characteristics of the power system, inserting a virtual sampling value generated in real time to compensate sampling data during the reset period; and S5, after resetting is completed, verifying whether the total standard deviation of the electrical quantity data of each channel returns to normal or not, comparing the compensation data with the data deviation after resetting, and if the deviation exceeds a specified threshold value, entering protection locking. The protection misoperation of the power distribution terminal can be avoided.

The invention relates to the technical field of hardware safe starting, in particular to a CPU hardware starting measurement method, system and equipment based on a TPCM and a power-on time sequence, and the method comprises the steps that S1, the system is powered on, and an ATX power module triggers a trusted platform control module TPCM to complete self initialization; s2, the TPCM outputs a PWREN signal to enable the CPU core to supply power, and continuously outputs an nRESET signal to enable the CPU to keep a hardware reset state; s3, the TPCM controls the SPI Switch module to switch a channel so as to exclusively access the BIOS / U-Boot FLASH and the interior of the CPU, a starting code is read, and integrity measurement calculation is carried out; s4, the TPCM verifies and judges the measurement result; if the verification and judgment are passed, CPU reset is relieved, and an SPI channel is switched to the CPU; if not, the CPU core power supply is cut off, and hardware alarm is triggered. According to the method, a safety verification blind area at the initial starting stage is eliminated from the hardware level, and a trusted starting chain which cannot be bypassed is constructed.

A hardware reset method, a configuration method for hardware reset, an electronic device and a storage medium. The hardware reset method comprises: converting a plurality of reset events for a plurality of hardware abstractions into a plurality of interrupt events; determining, by a micro control unit, a target hardware abstraction corresponding to a target interrupt event in the plurality of interrupt events and a reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event. The hardware reset method can modify the reset timing of the target interrupt event by updating the micro control unit after chip tape-out is completed, thereby improving the reliability and flexibility of hardware reset. Since the control path delay of the micro control unit to other hardware abstractions is small, the real-time performance when controlling complex reset timing is improved.

The invention relates to the technical field of fiber to the room (FTTR), in particular to a method and a system for providing sub-gateway registration for an MCU-free MINI OLT module of an FTTR main gateway. Comprising the following steps that a main gateway SOC resets an ASIC chip in a MINI OLT module through a GPIO interface so as to initialize the hardware state of the ASIC chip. According to the invention, the MINI OLT module architecture without the MCU chip is constructed, the main gateway SOC directly carries out cooperative control on the ASIC chip and the downlink PON BOB chip through the GPIO interface, the I2C bus and the SPI bus, redundant components are removed from the hardware level, the system cost is obviously reduced, and the hardware design is simplified. In the initialization process, the main gateway SOC sequentially completes hardware reset of the ASIC chip, parameter configuration of the downlink PON BOB chip and function initialization of the ASIC chip, interaction loss between the main SOC and the MCU chip in a traditional scheme is avoided, and the module initialization efficiency is improved.

The utility model provides an aerosol generating device. A reset circuit of the device comprises a key input assembly, a long key working assembly and a hardware reset assembly. A key switch element in the key input assembly responds to the operation of a user on the external key to switch the on-off state. And the long key working assembly is electrically connected with the key switch element. The control end of a first switch element in the hardware reset assembly is electrically connected with the long key working assembly, and the input end of the first switch element is electrically connected with the hardware reset end of the micro-control unit; when the micro-control unit works normally, the first switch element is switched on under the action of the switch-on control signal, so that the hardware reset end has a first level, and the reset activation of the micro-control unit is realized, and the circuit can generate a function signal to the micro-control unit according to user operation when the micro-control unit works normally; and the micro-control unit can be reset and activated according to the long-press operation of the user when the micro-control unit crashes, so that the influence of equipment crashes on the user is reduced, and the reliability of the aerosol generating device is greatly improved.

The invention relates to the field of computers, and discloses a multi-level protection system and method. The system comprises a processor, a first protection unit, a second protection unit and a power management unit, the processor is used for periodically sending a first heartbeat signal to the first protection unit, and the first heartbeat signal is used for determining that processor core scheduling is normal; the first protection unit is used for continuously receiving the first heartbeat signal and sending a reset signal to the processor if it is determined that the first heartbeat signal is interrupted; the processor is used for responding to the reset signal and executing hardware reset operation; the second protection unit is used for monitoring whether hardware reset of the processor fails or not, and if the hardware reset fails, a power supply restart signal is sent to the power supply management unit; and the power management unit is used for responding to the power restart signal and restarting a processor related power supply. According to the technical scheme, the reliability and the self-recovery capability of long-term operation of the system are greatly improved.

This disclosure relates to host recovery for a stuck condition. A host system can transmit a first command for a memory system to transition from a first power mode to a second power mode (e.g., a low power mode). In some cases, the host system can transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system can activate a timer associated with a timeout condition for exiting the second power mode and can determine that a duration indicated by the timer expires. In some examples, the host system can transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

The embodiment of the invention discloses a field firmware updating method, embedded storage equipment and a computer program product, and the method comprises the steps: responding to a write command from a host, writing a target firmware mirror image into a preset firmware storage area, and after a jump pointer in a reset vector address is modified to point to the target firmware, writing the target firmware mirror image into the preset firmware storage area; setting a firmware updating mark in the current firmware; in the running process of the current firmware, responding to a soft reset command from a host, and checking whether the firmware updating mark exists in the current firmware or not; and if yes, skipping to the reset vector address, starting to execute the target firmware pointed by the skipping pointer, and completing activation of the target firmware, otherwise, executing the soft reset command, and entering an idle state. According to the method, the new firmware can be activated in the continuous operation state of the embedded storage device, hardware reset or power-off and power-on are not needed, and the reliability, the service continuity and the data security of the updating process are effectively guaranteed.

The invention provides a reset control circuit, a circuit board and equipment, relates to the technical field of electronic circuits, solves the problem that a watchdog is difficult to reliably disable in a system kernel loading process in the related art, and can be realized through hardware, only one IO pin is used, interface resources can be saved, and the system performance is improved. And when the system kernel is abnormal in the loading process, hardware reset operation can be carried out on a product, and the high reliability requirement of an industrial system is met.

To cope with a communication error while suppressing erroneous detection of the communication error in a system having no communication error detection function.SOLUTION: The communication device includes a memory that stores a program, a reception buffer that stores reception data, a transfer destination buffer to which the reception data is transferred from the reception buffer, and a first control unit that erases the reception data from the reception buffer when the reception data is transferred from the reception buffer to the transfer destination buffer, and performs a hardware reset for erasing and initializing the program when an abnormality is detected. After transmitting data to the communication device, the second control unit checks whether data transmitted after a lapse of a predetermined time shorter than a time until a hardware reset when an abnormality occurs in data transmission is stored in the reception buffer. Then, the control unit causes the communication device to execute the software reset when at least a part of the transmitted data is stored in the reception buffer.SELECTED DRAWING: Figure 5

The utility model relates to electronic circuit technical field discloses a kind of externally-hung watchdog circuit and electronic equipment, through the PWM conversion module and hardware reset module of ingenious design, when MCU normal operation, PWM conversion module can accurately identify and convert PWM signal, maintain the high level state of RST pin, ensure system stable operation, and when detecting PWM signal exception, RST pin can be quickly pulled low, and trigger MCU to carry out software reset. In addition, hardware reset module as backup guarantee, when software reset is invalid, can intervene in time, to carry out hardware reset, ensure that equipment can be reliably recovered under abnormal condition, to significantly improve the reliability and stability of equipment, avoid the equipment paralysis even scrap due to abnormality, reduce the maintenance cost and failure risk of equipment, simultaneously, the circuit structure is simple, low in cost, easy to integrate and popularize, with higher practicality and market application value.

The invention discloses an embedded system reset and restart circuit, electronic equipment and a control method thereof, and the circuit comprises a power supply control circuit which is used for controlling an enable signal of a system power supply; the processor system is provided with at least two GPIO (General Purpose Input / Output) pins which are used for respectively outputting a watchdog enable signal and an active power failure restart signal; the watchdog and reset circuit is used for outputting a dog timeout signal when the watchdog timeout is caused by abnormal operation of the processor system, and generating a reset release signal after the output of the system power supply is normal; when the power supply control circuit receives the active power failure restart signal or the watchdog timeout signal, the system power supply enable signal is pulled down so as to turn off the system power supply; and then, the system power supply enable signal is automatically reset and pulled up due to the closing of the system power supply, and the system power supply is enabled again, so that the power-down self-weight start of the system is realized. System power supply enabling is directly controlled, the whole system power supply is forcibly closed, software and hardware resetting is ensured, and the problem that software resetting is possibly invalid is solved.

According to the hardware reset circuit for system abnormity detection provided by the utility model, the working voltage output by the control module is subjected to two-stage signal processing of the first signal receiving module and the second signal receiving module, and is combined with superposition control of external trigger signals, so that accurate detection and timely reset of system abnormity are realized, and the problem of false triggering is avoided; besides, the external trigger signal is generated when the terminal equipment is charged, the charging process is combined with a system reset trigger mechanism, when the system crash abnormity is detected, the system reset can be quickly and automatically triggered only by charging the equipment, and the user operation process is simplified; furthermore, a system power supply control module is adopted to automatically execute reset operation, manual intervention is not needed, the automation degree of exception handling is improved, and the circuit is simple in structure, convenient to maintain and high in practical value.

This utility model relates to the field of electronic product technology, specifically to a fast reset circuit for an MCU that has crashed. The fast reset circuit includes a timer chip U1, with pin 1 connected to an external button and pin 6 connected to the MCU's reset pin NRST. The external button is used to input a trigger signal to pin 1 of the timer chip U1. When the external button is continuously pressed for a preset time, pin 6 of the timer chip U1 outputs a low-level signal, pulling the MCU's reset pin NRST low, thus achieving a hardware reset. This pure hardware reset, achieved through an external button and timer chip, eliminates the need to disassemble the device casing, avoiding the structural damage of traditional reset methods. The long-press trigger mechanism and automatic timer reset function effectively prevent accidental operation, ensuring that the reset is triggered only under strict conditions.

The invention discloses a USB (Universal Serial Bus) equipment compatibility processing system and method based on hardware reset. The system comprises a domestic CPU (Central Processing Unit) processor, a CPLD (Complex Programmable Logic Device) and a USB peripheral, the CPU processor is connected with the CPLD through an SPI interface, and the CPLD controls the on-off of the power supply of the USB peripheral; when the CPU processor detects that enumeration of the USB peripheral fails, the CPLD is instructed to execute power-off and re-power-on operations on the USB peripheral, the USB controller is synchronously disabled and re-enabled, and hard reset and re-enumeration are completed through cooperation of the CPLD and the USB controller. According to the invention, through a collaborative reset mechanism of a hardware level, the problem of unstable USB equipment identification caused by bottom layer compatibility or time sequence difference is effectively solved, and the reliability and stability of the system in the aspect of peripheral compatibility are improved.

The utility model belongs to the related technical field of BMS hardware key expansion circuit technology, and particularly relates to a reset circuit. A trigger circuit is arranged on a reset circuit and comprises a trigger module, a first trigger circuit and a second trigger circuit, the trigger module is connected with the first trigger circuit and the second trigger circuit, the trigger module is used for receiving an external trigger action and outputting a trigger signal, and a delay circuit and a first switch circuit are arranged for delayed on-off, the first trigger circuit is connected with the timing end of the controlled module so as to detect the rising edge of the trigger signal and achieve software reset. Hardware resetting is performed through the first trigger circuit, and software resetting of the second trigger circuit is set at the same time, so that a hardware resetting circuit is added on the basis of original software resetting of the circuit, and software jamming is avoided. And resetting can be realized only by unpacking.

The invention relates to the technical field of industrial operation and maintenance, and discloses a cloud edge collaborative architecture-oriented fault root cause positioning and hardware reset system, which comprises a graph construction module for constructing a component association graph containing power supply dependence and reset wave and span; the mapping module is used for converting the record set before and after protective reset into abnormal data residuals of a component domain; the boundary extraction module is used for calculating a data retention fall value of adjacent component domains so as to extract a maximum record abrupt change boundary; the root cause positioning module is used for determining a root cause component domain by combining the distance to the mutation boundary and the fault interpretation degree; the reset selection module is used for selecting a controlled hardware reset instruction with the minimum cost for the abnormal spreading component set; the reset execution module is used for executing domain-by-domain release according to a power supply sequence and under the condition that observable data is read for the first time after extraction record hosting; and the verification write-back module generates a reset validity index. According to the invention, misjudgment of reset by-products is avoided, and accurate positioning and height retention of field clues are realized.

The embodiment of the application provides a kind of identification method of USB device, terminal equipment and system, applied to electronic technology field.The method can first carry out software reset to USB device when determining that USB device has been inserted but is not successfully identified, and when still cannot identify USB device after software reset, then carries out hardware reset to USB device.Through software reset and hardware reset, the operation of manually plugging and unplugging USB device is simulated, and it is possible to restore the identification of USB device without manual intervention, simplify the operation of user, improve the use experience of user.

The invention discloses a hardware self-weight starting circuit for an event capture module, a microprocessor and a self-weight starting method thereof, and the circuit comprises an event capture unit which is configured to latch an event timestamp and generate an internal capture completion signal when an external event is captured at a single time; the programmable timing unit is coupled with the event capture unit and is configured to respond to the internal capture completion signal and automatically start countdown of a preset duration; the hardware state recovery unit is coupled with the programmable timing unit and the event capture unit, and is configured to generate a hardware reset signal and send the hardware reset signal to the event capture unit when the countdown is finished; wherein the hardware reset signal is used for automatically resetting capture state logic of the event capture unit and clearing related flag bits, so that the event capture unit is recovered to a ready state without software intervention, and a self-sustaining hardware self-weight starting loop is formed.

A reset request is set in advance to be transmitted to a host device through a hardware configuration of a controller when an unrecoverable error occurs in a storage device. Therefore, it is possible to provide a storage device capable of quickly and stably receiving a hardware reset signal from a host device and performing a fast recovery operation, and an operating method thereof.