52 results about "Hardware reset" patented technology

The present disclosure describes apparatuses and methods for implementing secure verification of a physical unclonable function (PUF). In various aspects, a PUF verifier generates a PUF reagent value by obtaining a key from a PUF and a message value useful for PUF verification. The PUF verifier computes a digest value of the PUF key and the message value and selects a portion of the hash digest as a PUF reagent value. The PUF verifier writes the PUF reagent value to a non-volatile memory to enable subsequent verification of the PUF. The PUF verifier may also generate error-correction code information for the PUF reagent value and write this information to the non-volatile memory to enable error correction. Upon device hardware reset, the PUF verifier can securely verify PUF operation by generating a PUF key hash digest and comparing the hash digest with the PUF reagent value without exposing the PUF key.

The application relates to the technical field of network card configuration, and discloses a PCIe reset linkage network card configuration method and device, wherein the method comprises the following steps: listening to change events of a plurality of configuration items, and writing the first configuration state of the configuration item which is changed into a special snapshot storage partition; monitoring a PCIe bus hardware reset signal in real time, and within a hardware time sequence window before a network card chip enters a reset state, forcibly writing full-amount configuration states of the plurality of configuration items into the special snapshot storage partition; after the network card chip completes PCIe reset, reading snapshot data packets and performing validity checking, loading the snapshot data packets which pass the checking into an on-chip SRAM; and respectively performing configuration recovery on each functional module in the network card, and the total time length of the configuration recovery does not exceed a preset time length, so that the technical problems that configuration saving depends on a host operating system and a drive and configuration is completely lost in an uncontrollable reset scene in the prior art are solved.

The invention relates to the technical field of digital system reset, and discloses a combined reset device, a display system and a combined reset method.The combined reset device comprises a watchdog chip and a first AND logic gate chip; the input end of the watchdog chip is connected with a pulse width modulation output pin of the microprocessor, and the output end of the watchdog chip is connected with the first input end of the first AND logic gate chip; the second input end of the first AND logic gate chip is connected with a hardware reset signal output pin, the output end of the first AND logic gate chip is connected with a reset pin of the microprocessor, and the hardware reset signal output pin is further connected with a reset pin of the field programmable gate array chip. And the first AND logic gate chip is used for outputting a third reset signal when receiving the first reset signal and / or the second reset signal so as to indicate the microprocessor to perform reset operation. According to the invention, the microprocessor not only has a function of simultaneously resetting external hardware with the FPGA, but also has a watchdog function.

Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

According to an embodiment, a storage device (204) may comprise at least one processor (223) and a memory (231) for storing instructions. According to an embodiment, the instructions may be configured to, when executed individually or collectively by the at least one processor, cause the storage device to: identify whether a time for storing error-related information generated in the storage device is set in a state in which power supplying from a host device (201) is maintained after a signal for hardware reset is received from the host device (201); and when the time for storing the error-related information is set, store the error-related information in a designated area of the memory within the time for storing the error-related information, and then perform an initialization operation within an initialization time.

The utility model discloses a reset circuit and image forming device, overcome the defect that communication cannot be recovered after communication failure in high speed transmission in the prior art. The reset circuit includes main control chip and memory, and the reset pin of main control chip is connected the reset pin of memory through reset line, when main control chip and memory communication anomaly, main control chip passes through reset line and outputs reset signal to memory, to make main control chip with memory execute reset operation and communicate normally, wherein, reset signal is the first level signal conversion for the second time second level signal of first time, to make main control chip and memory can recover normal communication after communication anomaly through hardware reset mode.

In some implementations, a memory device may receive, from a host device, a hardware reset signal. The memory device may determine that a level associated with the hardware reset signal satisfies a threshold for a period of time. The memory device may determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device. The memory device may complete an ongoing memory operation within a remaining time period based on the determination that the host device is expected to power down the memory device.

This invention specifically relates to a fault location method for distribution lines based on a primary and secondary integrated pole-mounted circuit breaker, falling within the field of distribution line fault detection and location technology. The method includes: after the primary and secondary integrated circuit breaker detects a line fault and trips, it classifies the fault type using edge computing, blocks conventional reclosing, and completes hardware reset and line parameter preloading before distance measurement. In this invention, the phase-selective closing function of the primary and secondary integrated circuit breaker actively injects a standardized high-frequency transient excitation signal, avoiding the randomness problem of the traditional traveling wave method relying on natural fault traveling waves, thus improving the signal-to-noise ratio and feature saliency of the transient signal. Simultaneously, the core of the distance measurement relies on the transient oscillation frequency, which is dominated by the line inductance and capacitance and minimally affected by high-resistance grounding resistance, naturally adapting to high-resistance fault scenarios. Furthermore, the Prony algorithm's accurate extraction of transient parameters and iterative correction strategy for transition resistance solve the problem of large errors in high-resistance scenarios using traditional impedance methods.

When an unrecoverable error occurs in a storage device that receives a command from a host device, the storage device transmits a hint requesting transmission of a hardware reset signal to the host device, and the storage device performs a reset operation by receiving the hardware reset signal corresponding to the hint from the host device. Using a fast recovery operation, delay time due to occurrence of the error may be reduced, and the operational performance of the storage device may be improved.

The invention discloses a double-level watchdog control system with high reliability, which relates to the technical field of embedded system reliability design, and comprises three core modules, after a watchdog initialization and start control module is powered on, a hardware watchdog is immediately forbidden, and a forbidden period of 60 seconds is maintained; the watchdog hierarchical operation control module carries out differential control on a soft watchdog and a hardware watchdog, the soft watchdog feeds the dog through a user process in a period of 5 seconds, and the hardware watchdog feeds the dog through GPIO pulses executed by an independent thread of an application layer in a period of 30 seconds. The fault collaborative response and traceability module monitors a timeout state, soft timeout triggers a kernel panic to execute soft reset, and hard timeout executes hardware reset; a fault code is output before resetting, soft faults are 3 times of 1Hz short flash, hard faults are 5 times of 1Hz short flash, a dog feeding process ID is recorded to an EEPROM, fault grading recovery and accurate traceability are achieved, and system reliability and operation and maintenance efficiency are improved.

The utility model discloses a program control hard reset circuit which comprises an LDO chip U1, a pin Vi of the LDO chip U1 is respectively connected with one end of a resistor R2, one end of a capacitor C1 and a charging interface, a pin CE of the LDO chip U1 is respectively connected with the other end of the resistor R2 and a collector electrode of a triode Q1, and a base electrode of the triode Q1 is respectively connected with one end of a resistor R3, one end of a resistor R6 and an electronic product MCU through a resistor R4. The other end of the resistor R3 is connected with the other end of the capacitor C1, the other end of the resistor R6, an emitting electrode of the triode Q1 and a pin G of the LDO chip U1 are respectively grounded, a pin Vo of the LDO chip U1 is connected with an electronic product MCU and outputs a power supply VCC to supply power, and whether the electronic product needs to be subjected to hardware reset or not when the electronic product is inserted into a USB charging line to be charged is determined according to the input or output state of an IO port CRTRST of the electronic product MCU. The stability of the product is enhanced, and the user experience is not affected.

The invention provides a method for upgrading IC (integrated circuit) firmware by adopting GPIO (general purpose input / output) interface communication. The method comprises the following steps: initializing GPIO resources, applying and exclusively occupying a specified GPIO pin for simulating a JTAG (joint test action group) interface from an operating system kernel, and performing initialization configuration on the GPIO pin; the target IC reset and upgrade mode enters, and a reset pin of the master control SOC is controlled to execute hardware reset operation on the to-be-upgraded IC on the board level; issuing and burning firmware data; verifying the upgrade data; after the upgrade is completed, the mode is recovered and all firmware data are verified successfully, the instruction is sent to the IC to be upgraded again through the GPIO pin, the JTAG state machine of the IC to be upgraded is driven to exit the upgrade mode, then the reset pin is controlled to reset the IC for the second time, the IC is made to load new firmware and enter the normal working mode, and the upgrade of the IC to be upgraded is completed. The method has the beneficial effect that the GPIO interface can be adopted to simulate the JTAG interface for communication to upgrade the IC firmware.

The invention relates to the technical field of power distribution network relay protection equipment filtering algorithms, and provides a multichannel sampling deadlock abnormity processing method and system, and the method comprises the steps: S1, collecting the electrical quantity data of N channels in real time; s2, performing consistency judgment on the electrical quantity data; s3, judging whether data meeting the consistency condition in the electrical quantity data of the current N channels is normal data or not, automatically triggering ADC hardware reset when the data is abnormal, and forcibly recovering a channel non-switching function caused by interference; s4, during a reset period, based on historical electrical quantity data and steady-state characteristics of the power system, inserting a virtual sampling value generated in real time to compensate sampling data during the reset period; and S5, after resetting is completed, verifying whether the total standard deviation of the electrical quantity data of each channel returns to normal or not, comparing the compensation data with the data deviation after resetting, and if the deviation exceeds a specified threshold value, entering protection locking. The protection misoperation of the power distribution terminal can be avoided.

The invention relates to the technical field of hardware safe starting, in particular to a CPU hardware starting measurement method, system and equipment based on a TPCM and a power-on time sequence, and the method comprises the steps that S1, the system is powered on, and an ATX power module triggers a trusted platform control module TPCM to complete self initialization; s2, the TPCM outputs a PWREN signal to enable the CPU core to supply power, and continuously outputs an nRESET signal to enable the CPU to keep a hardware reset state; s3, the TPCM controls the SPI Switch module to switch a channel so as to exclusively access the BIOS / U-Boot FLASH and the interior of the CPU, a starting code is read, and integrity measurement calculation is carried out; s4, the TPCM verifies and judges the measurement result; if the verification and judgment are passed, CPU reset is relieved, and an SPI channel is switched to the CPU; if not, the CPU core power supply is cut off, and hardware alarm is triggered. According to the method, a safety verification blind area at the initial starting stage is eliminated from the hardware level, and a trusted starting chain which cannot be bypassed is constructed.

A hardware reset method, a configuration method for hardware reset, an electronic device and a storage medium. The hardware reset method comprises: converting a plurality of reset events for a plurality of hardware abstractions into a plurality of interrupt events; determining, by a micro control unit, a target hardware abstraction corresponding to a target interrupt event in the plurality of interrupt events and a reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event. The hardware reset method can modify the reset timing of the target interrupt event by updating the micro control unit after chip tape-out is completed, thereby improving the reliability and flexibility of hardware reset. Since the control path delay of the micro control unit to other hardware abstractions is small, the real-time performance when controlling complex reset timing is improved.

The invention relates to the technical field of fiber to the room (FTTR), in particular to a method and a system for providing sub-gateway registration for an MCU-free MINI OLT module of an FTTR main gateway. Comprising the following steps that a main gateway SOC resets an ASIC chip in a MINI OLT module through a GPIO interface so as to initialize the hardware state of the ASIC chip. According to the invention, the MINI OLT module architecture without the MCU chip is constructed, the main gateway SOC directly carries out cooperative control on the ASIC chip and the downlink PON BOB chip through the GPIO interface, the I2C bus and the SPI bus, redundant components are removed from the hardware level, the system cost is obviously reduced, and the hardware design is simplified. In the initialization process, the main gateway SOC sequentially completes hardware reset of the ASIC chip, parameter configuration of the downlink PON BOB chip and function initialization of the ASIC chip, interaction loss between the main SOC and the MCU chip in a traditional scheme is avoided, and the module initialization efficiency is improved.

This application provides a quick start method. When a software fault occurs in a device, a restart request is called through a customized interface that complies with an instruction set specification, to indicate firmware to restart system software; and an image of the system software such as an operating system, a hypervisor, or a Trusted Execution Environment (TEE) is loaded to restart the system software, without resetting hardware. This skips a hardware initialization process, and shortens time required for restarting the device. When a hardware fault occurs in the device, a suspend request is triggered to indicate to freeze a process of system software, and indicate firmware to store a snapshot of status information of a hardware device and perform a hardware reset operation. After the hardware is reset, the hardware device is restored to a status before reset based on the snapshot.

The utility model provides an aerosol generating device. A reset circuit of the device comprises a key input assembly, a long key working assembly and a hardware reset assembly. A key switch element in the key input assembly responds to the operation of a user on the external key to switch the on-off state. And the long key working assembly is electrically connected with the key switch element. The control end of a first switch element in the hardware reset assembly is electrically connected with the long key working assembly, and the input end of the first switch element is electrically connected with the hardware reset end of the micro-control unit; when the micro-control unit works normally, the first switch element is switched on under the action of the switch-on control signal, so that the hardware reset end has a first level, and the reset activation of the micro-control unit is realized, and the circuit can generate a function signal to the micro-control unit according to user operation when the micro-control unit works normally; and the micro-control unit can be reset and activated according to the long-press operation of the user when the micro-control unit crashes, so that the influence of equipment crashes on the user is reduced, and the reliability of the aerosol generating device is greatly improved.

The present invention relates to a method, device, computer equipment, and storage medium for testing the Block SID conversion state of a solid-state drive. The method comprises: reading and maintaining the original states of the Block SID, hardware reset, and Locking SP; setting the Block SID enable bit to 1, the SID value state to 0, and the hardware reset bit to 0 to form a 100 combination state; executing a power cycle event; determining whether the 100 combination state changes to 000; and if so, calculating conversion state test results. The present invention can quickly and efficiently verify the correctness of the Block SID conversion state of a solid-state drive after events such as power-on and power-off, recovery methods, PCI hot reset, and NVMe subsystem reset.

The invention relates to the field of computers, and discloses a multi-level protection system and method. The system comprises a processor, a first protection unit, a second protection unit and a power management unit, the processor is used for periodically sending a first heartbeat signal to the first protection unit, and the first heartbeat signal is used for determining that processor core scheduling is normal; the first protection unit is used for continuously receiving the first heartbeat signal and sending a reset signal to the processor if it is determined that the first heartbeat signal is interrupted; the processor is used for responding to the reset signal and executing hardware reset operation; the second protection unit is used for monitoring whether hardware reset of the processor fails or not, and if the hardware reset fails, a power supply restart signal is sent to the power supply management unit; and the power management unit is used for responding to the power restart signal and restarting a processor related power supply. According to the technical scheme, the reliability and the self-recovery capability of long-term operation of the system are greatly improved.

The application discloses an AC108 audio chip control system and method based on an FPGA module, and comprises a clock and reset management module, an I2S / PCM drive control module, a register configuration module and a FIFO module, wherein the clock and reset management module is used for generating a stable clock signal and synchronizing a reset signal; the I2S / PCM drive control module is responsible for controlling a hardware reset signal of a chip and managing transmission and counting of audio data; the register configuration module is responsible for reading register data from a ROM and sending the register data to the I2S / PCM drive control module; the FIFO module is used for temporarily storing register configuration data; and the I2S / PCM protocol bottom layer drive is used for processing audio data and generating an effective signal. The system provides accurate clock and reset management, flexible register configuration capability and a function of supporting 4-channel data acquisition and analysis. Through self-defined parameter configuration and a soft reset function, the application significantly improves portability and applicability of a drive program, and meets efficient control and optimization requirements of the AC108 chip on an FPGA platform.

This disclosure relates to host recovery for a stuck condition. A host system can transmit a first command for a memory system to transition from a first power mode to a second power mode (e.g., a low power mode). In some cases, the host system can transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system can activate a timer associated with a timeout condition for exiting the second power mode and can determine that a duration indicated by the timer expires. In some examples, the host system can transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

The embodiment of the invention discloses a field firmware updating method, embedded storage equipment and a computer program product, and the method comprises the steps: responding to a write command from a host, writing a target firmware mirror image into a preset firmware storage area, and after a jump pointer in a reset vector address is modified to point to the target firmware, writing the target firmware mirror image into the preset firmware storage area; setting a firmware updating mark in the current firmware; in the running process of the current firmware, responding to a soft reset command from a host, and checking whether the firmware updating mark exists in the current firmware or not; and if yes, skipping to the reset vector address, starting to execute the target firmware pointed by the skipping pointer, and completing activation of the target firmware, otherwise, executing the soft reset command, and entering an idle state. According to the method, the new firmware can be activated in the continuous operation state of the embedded storage device, hardware reset or power-off and power-on are not needed, and the reliability, the service continuity and the data security of the updating process are effectively guaranteed.

The invention relates to the technical field of satellite communication, in particular to a satellite communication module dual-mode dynamic start-up and security upgrade collaboration method, which comprises the following steps: an application processor sends an upgrade instruction to a communication processor, and the communication processor sets an upgrade flag bit at a Flash fixed address and triggers hardware reset; after resetting, the secondary bootstrap program detects the flag bit and notifies the application processor that the flag bit is ready, the two parties adaptively negotiate parameters through a baud rate, and the application processor transmits an upgrade mirror image packet; the communication processor performs verification and programming on the mirror image package, and updates the U-Boot environment variable partition of the corresponding starting mode; and when the communication processor is started, the secondary bootstrap program selects a starting mode according to the level state of the GPIO pin, loads corresponding starting parameters, and dynamically loads the firmware mirror image to a specified DDR address for operation. According to the method, the dynamic switching of the high and low rail modes is realized, and the method does not depend on hardware replacement and safe and reliable OTA firmware upgrading.

The invention provides a PCIe link burst interrupt processing method of an NVMe controller, and a data monitoring processing unit is arranged between the NVMe controller and a PCIe interface and is used for monitoring a PCIe link between the NVMe controller and the PCIe interface. When the PCIe link is disconnected, the data monitoring processing unit generates corresponding compensation data for an uncompleted equipment host reading request, and returns the compensation data to the NVMe controller; when the data is written, a receiving signal of the PCIe interface is pulled up, data transmission to the PCIe interface is stopped, and all data sent to the equipment by the host is discarded by the data monitoring processing unit. According to the invention, a mode that hardware carries out data discarding and data compensation on the PCIe interface is adopted, and meanwhile, after all data are transmitted, a mode of soft resetting of the NVMe controller is adopted for processing, so that the situation that Reset occurs during transmission due to the fact that a hardware Reset NVMe mode is directly used, data transmission between the NVMe controller and the outside cannot be completed, and the data transmission efficiency is improved is avoided. And normal starting cannot be carried out after restarting.

Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

The invention provides a reset control circuit, a circuit board and equipment, relates to the technical field of electronic circuits, solves the problem that a watchdog is difficult to reliably disable in a system kernel loading process in the related art, and can be realized through hardware, only one IO pin is used, interface resources can be saved, and the system performance is improved. And when the system kernel is abnormal in the loading process, hardware reset operation can be carried out on a product, and the high reliability requirement of an industrial system is met.

The utility model provides a hardware reset circuit. The hardware reset circuit comprises a first diode, a first capacitor, a second diode and a first resistor, the anode of the first diode is connected with a first power supply end, the cathode of the first diode is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the anode of the second diode, and the cathode of the second diode is connected with the first resistor. The cathode of the second diode is connected with the second power supply end, and the first end of the first capacitor is connected to the reset end of the controller. The reliability of the reset circuit can be improved.

To cope with a communication error while suppressing erroneous detection of the communication error in a system having no communication error detection function.SOLUTION: The communication device includes a memory that stores a program, a reception buffer that stores reception data, a transfer destination buffer to which the reception data is transferred from the reception buffer, and a first control unit that erases the reception data from the reception buffer when the reception data is transferred from the reception buffer to the transfer destination buffer, and performs a hardware reset for erasing and initializing the program when an abnormality is detected. After transmitting data to the communication device, the second control unit checks whether data transmitted after a lapse of a predetermined time shorter than a time until a hardware reset when an abnormality occurs in data transmission is stored in the reception buffer. Then, the control unit causes the communication device to execute the software reset when at least a part of the transmitted data is stored in the reception buffer.SELECTED DRAWING: Figure 5