114 results about "Tape-out" patented technology

The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

A power operated tape measure enables extension of a tape via a drive mechanism, as well as retraction of the tape through a mechanical decoupling within the drive mechanism. The tape measure has a housing within which is positioned a spring-biased tape assembly, the drive mechanism and a clutch. The spring-biased tape assembly includes an annular reel onto which is wound a tape having indicia for taking length measurements. The drive mechanism includes a driving gear and a driven gear, and is adapted to engage with a bottom surface of the tape to extend the tape out of the housing. The clutch is adapted to displace the driven gear out of engagement with the driving gear and thereby decouple the driving and braking force provided by the drive mechanism from acting upon the bottom surface of the tape to permit the spring-biasing of the tape assembly to retract the tape into the housing.

The invention provides an integrated circuit testing method, which comprises the steps of design index parameter determination, circuit diagram input, pre-simulation, layout design, layout verification and parasitic parameter extraction, post-simulation and tape-out. The integrated circuit testing method is characterized in that both the pre-simulation and the post-simulation use a transistor-level SPICE netlist, which can be converted to documents required for an automatic testing platform. The testing method provided by the invention can be used to greatly shorten the original test vector writing time for chip testing personnel, speed up the progress of the test, avoid understanding deviation between designers and testers and achieve seamless butting.

Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog / mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and / or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).

A technique for enhancing the frequency tuning range for monolithic RF source generation using fully-integrated coupled Voltage-Controlled-Oscillator (VCO) arrays that contain an odd number of VCOs. Fully-monolithic SiGe VCO arrays using on-chip inductor and varactor with on-chip bias current sources have been carefully designed and simulated in IBM 7HP 0.18 μm BiCMOS technology and taped out for fabrication. The SPICE simulated frequency and phase tuning of the 1-D VCO×5 array is dependent on the edge VCOs termination impedance, the tuning voltages, and the VCO coupling strength. The simulated data suggests that the enhanced tuning range and beam steering can be accomplished using coupled-VCO arrays without needing complex and bulky phase shifters. This design technique imposes no apparent phase noise penalty but can provide simulated RF frequency tuning range of ˜40% and also ˜+ / −25° beam steering for active antennas applications.

The present invention discloses an integrated circuit structure and a design method thereof, in which a circuit passageway is arranged at each circuit element terminal in circuit design stage. The arranged circuit passageway does not only increase layout flexibility in circuit simulation stage but also simplify layout difficulty when the circuit layout needs to be modified after taping out stage. Also, the circuit passageway can minimize modified metal layers, i.e. the number of modified masks is minimized. Because the expense of fab is based on the utilized layers and number of masks instead of designs of masks, the present invention will not increase the expense in taping out stage and can save the cost of research and development when modifications are required.

The invention discloses a two-point wireless transmitter and a frequency offset correcting method of the two-point wireless transmitter. Improvement is conducted based on a circuit structure of a traditional two-point transmitter, and frequency offset correction is achieved by conducting data interaction by means of two wireless communication chips which have the complete functional design and are successfully taped out. During implementation, the two chips are respectively provided with a microcontroller, a register, a transmitting module, a receiving module, an antenna and a change-over switch; transmitted data are input to the wireless transmitter through two paths, one path of data are input to a voltage-controlled oscillator through a branch switch S2 of the first chip and a DAC to be transmitted in an out-band mode, and the other path of data are input to a multi-mode frequency divider through a branch switch S1 of the first chip and a delta-sigma modulator for modulation and frequency division and then are transmitted in an in-band mode. According to the two-point wireless transmitter and the frequency offset correcting method of the two-point wireless transmitter, through the data interaction between the two chips and software processing of the microcontroller of the first chip, the frequency offset of the transmitted data can be corrected effectively, and high-quality smooth transmission of data is achieved; the two-point wireless transmitter and the frequency offset correcting method of the two-point wireless transmitter have the advantages that energy consumption is low, the number of hardware resources is small, cost is low and stability is high.

Techniques for masking unknown and irrelevant response values that may be produced by a BIST process. Masking circuitry is provided for selectively masking the response values obtained from a BIST process. The operation of the selective masking circuitry is controlled by a programmable mask circuitry controller that can be programmed after the integrated circuit has been manufactured. A user can analyze an integrated circuit after it has been manufactured to identify irrelevant and unknown data values in a BIST process. After the irrelevant and unknown data values have been identified, the user can program the programmable mask controller to have the selective masking circuitry mask the identified irrelevant and unknown data values.

The invention relates to a soft reset device for integrated circuit chip and is inserted into the integrated circuit chip. The utility model consists of a ring shape oscillator(11), a reset pulse signal that has certain cycle and meets the reset request under the action of trigger signal according to the software control; a first edge detecting unit(12) that receives the reset pulse signal and outputs reset ending signal, a reset module(13) that receives the reset ending signal and outputs reset signal to start-up reset while outputs reset closing signal to the ring shape oscillator to stop the output of the reset pulse signal. The static power consumption of the module is around zero; the area is small and can prevent the filtering of high frequency input signal caused by the low pass property of the RC; compatible to meet more than one trigger method; clear design concept and can be realized by standard CMOS technique approved by tape-out inspection needless of adding mask.

The invention provides a processor with a polymorphic instruction set architecture. The processor comprises a scalar processing unit (101), at least one polymorphic instruction processing unit (100), at least one multi-granularity parallel memory (102) and a direct memory access (DMA) controller (103). Each of the polymorphic instruction processing units (100) comprises at least one function unit (202), the polymorphic instruction processing units (100) are used for explaining and executing polymorphic instructions, and the function units (202) are used for executing specific data operation tasks; the scalar processing unit (101) is used for calling the polymorphic instructions and inquiring execution states of the polymorphic instructions; and the DMA controller (103) is used for transmitting configuration information of the polymorphic instructions and transmitting data required by the polymorphic instructions to the multi-granularity parallel memories (102). According to the processor, programmers can still redefine the instruction set of the processor according to characteristics of an application algorithm after tape-out production of the processor.