Jitter tolerance simulation verification method of clock data recovery circuit

Abstract

The invention discloses a jitter tolerance simulation verification method of a clock data recovery circuit. The jitter tolerance simulation verification method is implemented through the following three modules: a test data generating module, a clock data recovery (CDR) circuit and an error code detection module, wherein the test data generating module generates a pseudo random sequence superposed with jitter information as an input of the CDR circuit, consists of a jitter modulating clock and a pseudo random code generating module, and is implemented via VerilogA language design; the error code detection module performs an error code detection on an output data file of CDR simulation, and is implemented through Python scripts. The jitter tolerance simulation verification method comprises the following two steps: first, simulating the test data generating module and the CDR circuit to obtain the output data file of the CDR; then, performing the error code detection on the output data file by using the error code detection module. By the jitter tolerance simulation verification method, the jitter resistance of the CDR is evaluated in a design stage, so that tape-out risks are effectively reduced; in addition, the jitter tolerance simulation verification method is easy to implement and short in verification time and has relatively strong practicability.

Description

technical field [0001] The invention discloses a method for simulating and verifying the jitter tolerance of a clock data recovery circuit, which can evaluate the anti-jitter performance of the receiving end in the design stage. Specifically, by adding jitter to the clock of the pseudo-random code generation module, the pseudo-random code with jitter is obtained as the serial input data of the CDR, and then the circuit simulation is performed to obtain the output data file of the CDR, and then the output data file of the CDR is processed. Error detection processing. Background technique [0002] With the rapid development of digital communication technology and the continuous improvement of data processing capabilities, the amount of information exchanged between chips, boards and systems has become larger and larger, which has resulted in I / O transmission rates becoming the bottleneck that limits system performance. Due to the impact of clock skew, crosstalk, coupling and ...

AI Technical Summary

Problems solved by technology

You can refer to the idea of ​​testing when implementing simulation verification, but because superimposed jitter can only delay data backwards on the time axis during simulation verification, and cannot delay the superimposition in the opposite direction of the time axis, it is difficult to achieve the ideal jitter superposition effect

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