55 results about "Data recovery circuit" patented technology

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The present application relates to electronic endoscope technical field, specifically, it relates to a kind of endoscope multiplexing line built-in MIPI-CSI signal long-distance transmission isolation enhancement device.It includes the control end module, receiving end module and power management unit integrated in multiplexing line, and power management unit is used to power control end module, receiving end module.Power management unit in the present application, by the high integration of control end module, receiving end module and power management unit in multiplexing line, signal conditioning and isolation enhancement unit of control end can effectively process original signal and inhibit common-mode interference, then with the equalization compensation and clock data recovery circuit of receiving end repair signal attenuation and timing distortion problem caused by long-distance transmission, to realize in complex electromagnetic environment still can stable output low jitter, high integrity video signal, fundamentally solve the problem of affecting diagnostic accuracy due to image delay, quality decline.

The application discloses a decision feedback equalizer for PAM4 encoding band infinite impulse response filter, belongs to the field of signal processing, and comprises a high-pass filter and a linear equalizer, a decision feedback adder, and an infinite impulse response filter coefficient feedback control module; noise filtering is performed on a high-speed signal, low-frequency attenuation of the high-speed signal is compensated, a tailing effect in a frequency response is eliminated, high-speed inter-symbol interference is suppressed and eliminated, and an offline post-cursor in the frequency response is fed back and compensated; meanwhile, aiming at PAM4 encoded data, an RLM (Level separation mismatch ratio) calibration module and a clock data recovery circuit are added, which are used for improving the speed of clock receiving and recovery, and due to the addition of more high-speed modules, the load of the equalization adder is increased; the application uses a layout planning of a double-difference six-port mutual inductance bridge type (T-coil) inductive network, and bandwidth is expanded by using inductive peaking technology.

A pulse amplitude modulation transition density trigger in a test and measurement instrument is provided. A test and measurement instrument comprises: an input for receiving a pulse amplitude modulated n-level (PAMn) signal; an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal; an acquisition memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform; a trigger circuit coupled to the ADC and the acquisition memory and configured to generate a trigger signal to cause the test and measurement instrument to trigger acquisition of waveforms; a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal; and a conversion detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit, and configured to detect a symbol conversion based on the decoded bits, and to cause the trigger circuit to generate a trigger signal in response to detecting a particular symbol conversion.

An ultra wide band receiver with enhanced signal detection capability is provided. In one example, the receiver includes a first processing path including a first despreading circuit that despreads a received UWB signal based on a first bit value to generate a first amplitude value; a second processing path comprising a second despreading circuit, the second despreading circuit despreading the received UWB signal based on a second bit value to generate a second amplitude value; and a data recovery circuit. The data recovery circuit is configured to compare the first amplitude value with the second amplitude value and output a bit value based on a result of the comparison.

An ultra-wideband receiver (500) with enhanced signal detection capabilities is provided. In an example, the receiver (500) includes a first processing path comprising a first spread-out circuitry (522) that spreads a received UWB signal based on a first bit value to generate a first magnitude value; a second processing path comprising a second spread-out circuitry (532) that spreads the received UWB signal based on a second bit value to generate a second magnitude value; and a data recovery circuitry (568). The data recovery circuitry (568) is designed to compare the first magnitude value with the second magnitude value and output a bit value based on the comparison.

A test and measurement instrument comprises an input for receiving a pulse-amplitude modulated n-level signal (PAMn), an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal, a capture memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform, a trigger circuit coupled to the ADC and the capture memory to generate a trigger signal to cause the test and measurement instrument to initiate waveform acquisition, a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal, and a transition detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit to detect symbol transitions based on the decoded bits and to initiate the trigger circuit.The trigger signal is designed to generate a response to the detection of a specific symbol transition.

The invention discloses a clock data recovery circuit applied to a multi-channel array high-speed SerDes receiver. A half-rate decision feedback equalizer carries out signal recovery processing on an original analog signal input in a current period according to a first target sampling clock output from a clock network in a previous period and outputs a digital serial signal; the target sampler carries out sampling processing on the digital serial signal according to a second target sampling clock output from the clock network in the previous period and outputs serial judgment data; the demultiplexer carries out parallel processing on the digital serial signals and the serial judgment data according to a third target sampling clock output from the clock network in the previous period and outputs multiple paths of parallel signals; the clock recovery module generates a target four-phase clock according to the local clock signal and the multi-path parallel signal; and the clock network generates a first target sampling clock, a second target sampling clock and a third target sampling clock of the next period according to the target four-phase clock. The clock data recovery circuit has the advantages of low power consumption and high speed.

This invention provides a circuit including a phase-locked loop (PLL) and a clock-redirecting circuit (CDR). The CDR circuit includes a phase detector, a loop filter, an SSC demodulator, a control code generator, and a phase interpolator. The PLL is configured to generate a clock signal and an SSC direction signal with SSC modulation. The phase detector compares the phase of the input signal with that of the output clock signal to generate a detection result, wherein the input signal has SSC modulation. The loop filter filters the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator generates a control code based on the filtered signal and the control signal to control the phase interpolator to adjust the phase of the clock signal to generate an output clock signal. Using this scheme, the static phase error between the input signal and the output clock signal can be reduced.

The application discloses a clock data recovery circuit and a method for preventing false locking or non-locking of the clock data recovery circuit. The method uses a locking detector in the clock data recovery circuit to judge four kinds of information, i.e. clock advance, clock lag, clock error 1 and clock error 2, detected by a phase detector in the clock data recovery circuit, so that whether the input data rate of the current clock recovery circuit matches the sampling clock can be effectively judged. When the input data rate is high, the clock data recovery circuit is prevented from running off-center and being non-locked, and when the input data rate is low, the clock data recovery circuit is prevented from being false-locked. Meanwhile, the upper protocol layer is rapidly informed. Compared with a traditional speed negotiation mechanism based on the upper protocol layer, the efficiency is improved, and the clock data recovery circuit is effectively prevented from being non-locked.

The embodiment of the invention provides a burst data recovery circuit, an integrated circuit, equipment and a method. The burst data recovery circuit comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator, a first charge injection circuit of the first voltage-controlled oscillator is used for receiving recovered data; the positive output end of the first voltage-controlled oscillator is connected with the positive input end of the second charge injection circuit of the second voltage-controlled oscillator, and the negative output end of the first voltage-controlled oscillator is connected with the negative input end of the second charge injection circuit; the positive output end of the first voltage-controlled oscillator is connected with the negative input end of the third charge injection circuit of the second voltage-controlled oscillator, and the negative output end of the first voltage-controlled oscillator is connected with the positive input end of the third charge injection circuit; and the differential output end of the second voltage-controlled oscillator is used for outputting a clock signal corresponding to the recovered data. Since the polarities of the two pairs of injection signals of the second voltage-controlled oscillator are opposite, the phase noise can be counteracted, so that the phase noise of the clock can be effectively suppressed, the clock jitter can be reduced, and the clock of the data can be accurately recovered.

A clock and data recovery circuit includes a voltage-controlled oscillator (VCO), a frequency detector, and a control circuit. The VCO generates a clock signal based on a voltage signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a first rising control signal accordingly. The control circuit is coupled to the VCO and the frequency detector and adjusts the voltage signal based on the first rising control signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in a data recovery mode, and the frequency detector detects whether the frequency of the clock signal needs to be increased in the data recovery mode.

A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

A clock data recovery (CDR) circuit includes a phase detector circuit, a proportional path, an integral path, and an oscillator circuit. The phase detector circuit is configured to receive input data and detect the input data based on an oscillation signal to output a detection result. The proportional path is configured to output a proportional control signal based on the detection result. The proportional path includes a charge pump circuit and a variable capacitor. The charge pump circuit generates a voltage control signal based on the detection result. The variable capacitor generates the proportional control signal based on the voltage control signal. The integral path is configured to output an integral control signal based on the detection result. The oscillator circuit is coupled to the proportional path and the integral path and configured to generate the oscillation signal based on the proportional control signal and the integral control signal.

The invention provides a source electrode driving chip, a display device and a bias current adjusting method of the display device. The source electrode driving chip comprises an equalizer, a clock and data recovery circuit and a bias current adjusting circuit, the input end of the equalizer is configured to receive differential signals, the clock and data recovery circuit is electrically connected with the output end of the equalizer, and the input end of the bias current adjusting circuit is electrically connected with the output end of the equalizer; the output end of the bias current adjusting circuit is electrically connected with the clock and data recovery circuit, and the bias current adjusting circuit is configured to detect the swing variation of the differential signal and adjust the target bias current output to the clock and data recovery circuit according to the swing variation. Linkage adjustment of the differential signal swing and the bias current is realized through the bias current adjustment circuit, the anti-interference capability of the source electrode driving chip is improved, the power consumption is optimized, and the manufacturing cost is reduced.

The application provides a clock phase error calibration device and method, which comprises a delay chain, a clock data recovery circuit, a phase error detection circuit and a calibration logic circuit; the delay chain is used for outputting a plurality of delay clock signals with different phases under the control of a control code value; the clock data recovery circuit selects two delay clock signals with a desired phase error of a set error value from the plurality of delay clock signals in sequence; the phase error detection circuit is used for detecting a detection phase error between the two delay clock signals selected by the clock data recovery circuit; and the calibration logic circuit is used for outputting a control code value for adjusting the delay of the delay clock signal by the delay chain according to a direct current voltage point corresponding to the detection phase error, so that the delay clock signal and the real phase error of two delay clock signals thereof are close to the set error value.

The present invention relates to a clock data recovery circuit and method of operation thereof. The technology of the present invention is used to implement a clock data recovery circuit with improved tendencies, such as pull-up and / or pull-down tendencies. In various embodiments, the clock data recovery circuit includes a phase detector for receiving an input signal and outputting a reference clock signal. The phase detector then outputs two signals to a charge pump. The output of the charge pump drives an oscillator control voltage up or down depending on the current from the charge pump. A lock detector detects whether lock has occurred by comparing the oscillator control voltage to a preset threshold voltage. When the circuit has stabilized to a frequency substantially close to that of the input signal and the oscillator control voltage is substantially close to the threshold voltage, lock is said to have occurred. A controller circuit can control the scanning of the frequency range available to the circuit until lock occurs.

The application discloses a clock data recovery circuit for half-rate data re-timing, comprising a switched capacitor module, a filter capacitor, a two-stage differential ring oscillator, a clock buffer, a four same OR gate module and a re-timer module, wherein the switched capacitor module controls a sampling period and a sampling frequency by using input binary random data, samples a clock signal and outputs a sampling voltage signal; the filter capacitor filters the sampling voltage signal and outputs a control voltage; the two-stage differential ring oscillator generates four clock signals according to the control voltage; the clock buffer obtains the four square wave clock signals; the four same OR gate module outputs a double frequency clock signal and feeds back to the switched capacitor module; and the re-timer module samples binary random data according to two square wave clock signals. The application can significantly reduce power consumption, reduce area, save cost, and has good jitter performance of recovered clock and jitter tolerance performance of recovered data.

The application belongs to the field of electronic technology and relates to a burst mode clock data recovery circuit and method of baud rate sampling structure. The clock data recovery circuit comprises a sampling comparator circuit, a polarity flip detection circuit, a Mueller-Muller phase detector, a phase control state machine and a phase interpolator circuit. The sampling comparator circuit samples an input signal and a threshold amplitude to obtain a decision data signal and samples the input signal and a reference amplitude to obtain a decision error signal. The polarity flip detection circuit receives the decision data signal and outputs a phase lock signal. The Mueller-Muller phase detector receives the decision data signal and the decision error signal and outputs a phase too early / too late signal. The phase control state machine receives the phase lock signal and the phase too early / too late signal, and outputs a phase control code to the phase interpolator circuit to adjust the phase of a sampling clock. The application reduces the clock data recovery from three times oversampling to baud rate sampling, thereby reducing the power consumption and area of the circuit.

This application relates to a phase detector circuit, a phase detector chip, and a clock data recovery circuit. Under a preset level of the second sampling clock signal, a logic decision circuit directly generates a decision result based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal, instead of generating two intermediate signals first and then merging them. Subsequently, the second synchronization circuit latches the output after being synchronized by the second sampling clock signal. This scheme, because the entire decision process has only one combinational logic path, eliminates the problem of delay matching between the two signals, thus completely eliminating output transient fluctuations caused by inconsistent path delays. Simultaneously, the output is updated only at the edge of the second sampling clock signal, maintaining a constant output and avoiding additional phase differences introduced by delay mismatch, significantly improving the alignment accuracy of the clock and data. Furthermore, the phase detector circuit structure of this application is simpler than traditional structures, resulting in relatively smaller power consumption and area.

The present disclosure relates to a frequency reduction circuit, a cascaded frequency reduction circuit and a clock data recovery circuit, the frequency reduction circuit comprising: a frequency division module configured to perform frequency division processing on an input clock signal to obtain a frequency division clock signal, the frequency division clock signal having a frequency of half of that of the input clock signal, and the frequency division clock signal being an output clock signal after frequency reduction of the input clock signal; a first synchronization module configured to sample an input data signal based on the input clock signal to obtain a first data signal; and a data frequency reduction module configured to perform frequency reduction processing on the first data signal based on both the frequency division clock signal and an inverted frequency division clock signal which is synchronized with the frequency division clock signal and has an inverted phase, to obtain an output data signal having a frequency synchronized with that of the frequency division clock signal. Thus, correct locking of a loop of the clock data recovery circuit can be ensured.

An ultra-wideband receiver with enhanced signal detection capabilities is provided. In one example, the receiver includes a first processing path comprising first de-spreading circuitry that de-spreads a received UWB signal based on a first bit value to generate a first magnitude value, a second processing path comprising second de-spreading circuitry that de-spreads the received UWB signal based on a second bit value to generate a second magnitude value, and data recovery circuitry. Data recovery circuitry is configured to compare the first magnitude value to the second magnitude value and output a bit value based on the comparison.

The utility model provides a clock data recovery circuit, a chip and electronic equipment, and the clock data recovery circuit comprises a clock extraction unit which extracts a first clock signal in an input data signal according to a first selection window signal; the voltage-controlled delay unit outputs a second clock signal according to the control signal, the second selection window signal and the output signal thereof; the reference clock generator is used for outputting multiple paths of reference clock signals required by other modules according to the second clock signal; the adjusting unit and the locking detection unit respectively output a control signal and a locking indication signal according to the frequency and phase difference of the first clock signal and the feedback clock signal; the sampler outputs data in the input data signal according to the sampling clock signal. According to the scheme, the CDR circuit is based on the MDLL first-order system, the system design is simple, the whole CDR circuit does not have the stability problem, the large bandwidth can be achieved, and the loop locking efficiency is improved.

This invention discloses an aperiodic data frequency acquisition and lock detection circuit and method, comprising: a frequency detection circuit configured to use a single flip-flop to sample a voltage-controlled oscillator (VCO) clock signal via the rising edge of aperiodic data, generating a pulse signal related to the frequency difference, wherein the duty cycle of the pulse signal monotonically changes during frequency acquisition; a frequency scanning circuit connected to the frequency detection circuit, configured to generate an oscillation frequency control signal based on the pulse signal to control the oscillation frequency of the VCO in the clock data recovery circuit to increase or decrease; and a lock detection circuit connected to the frequency detection circuit, configured to perform lock detection based on the duty cycle change of the pulse signal, and output a lock indication signal when lock is determined. This invention can expand the frequency acquisition range, achieve higher reliability, and reduce power consumption and area.

The invention provides a display driving circuit, a display driving chip and display equipment, and belongs to the technical field of display. According to the display driving circuit, the data swing detection circuit can flexibly control the bias signal provided for the analog front end based on the locking indication signal output by the clock data recovery circuit so as to adjust the bias current in the analog front end, so that when the swing of the display signal received by the analog front end is relatively small, the display signal can be locked by increasing the bias current, and the display signal can be accurately displayed. The amplification effect of the analog front end on the received display signal is ensured, the bias current is reduced when the swing of the display signal received by the analog front end is large, and the working power consumption of the analog front end is reduced. Therefore, the purpose of flexibly adjusting the bias current based on the display signals with different swing amplitudes and enabling the amplification capability of the analog front end to be dynamically adapted along with the change of the swing amplitudes can be achieved, and various time schedule controllers for outputting the display signals with different swing amplitudes can be flexibly compatible.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog- front-end (ATE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

The invention provides a digital clock data recovery circuit and method. The digital clock data recovery circuit comprises an analog-to-digital converter used for sampling an analog input signal under the control of a sampling clock signal and converting the sampled signal into a digital signal; the error detector is used for carrying out phase error detection according to the digital signal to obtain a phase error estimation value; the frequency deviation detector is used for acquiring a frequency deviation estimation value according to the phase error estimation value; the loop filter is used for filtering according to the phase error estimation value and the frequency deviation estimation value and outputting a filtering signal; the phase code generator is used for generating a phase code according to the filtering signal; and the phase interpolator is used for generating the sampling clock signal according to the phase code so as to control the sampling phase of the analog-to-digital converter. The digital clock data recovery circuit can quickly capture clock frequency deviation.

An interface circuit has a data recovery circuit, a protocol interface circuit, and a controller or processor that can be implemented using a finite state machine. The data recovery circuit may be configured to receive a stream of symbols through three wires of a serial bus according to a high speed mode defined by a Mobile Industry Processor Interface Alliance (C-PHY) protocol. The protocol interface circuit may be coupled to an output of the data recovery circuit and configured to receive data from the data recovery circuit. The finite state machine may be configured to disable the data recovery circuit when an end of transmission is indicated in a first end of transmission signal received from the protocol interface circuit.