133 results about "Data recovery circuit" patented technology

The invention discloses a reference-clock-free clock and data recovery circuit, a use method and an integrated circuit. The circuit comprises a first circuit and a second circuit, the first circuit comprises a voltage-controlled oscillator, the second circuit comprises a comparison module and a frequency capture module, and the comparison module is used for comparing a first clock signal with a high-speed serial data signal, generating a first signal and outputting the first signal to the frequency capture module. The frequency capture module outputs a first control signal, the first control signal is used for adjusting the first oscillation frequency so as to enable the frequency deviation between the first oscillation frequency and the second oscillation frequency to be smaller than a first deviation threshold value, and the second circuit generates a second clock signal and outputs the second clock signal to the first circuit; the first circuit adjusts the voltage-controlled oscillator using a second clock signal such that the frequency offset is less than a second offset threshold. According to the invention, the CDR and PLL functions are fused and an external reference clock is replaced by the CDR recovery clock, so that a clock and data recovery system without an external clock is realized.

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

A circuit and method for data recovery comprises clock generation, data reception, data oversampling, and data selection circuits; wherein, clock generation circuits are used to output data reception clock signals and data processing clock signals; data reception circuits are used to receive original transmission data from the data transmitter in accordance with the data reception clock signals, and transmit data based on its output; data oversampling circuits are used for multiple oversampling of at least one bit of transmission data corresponding to at least one data processing cycle according to the data processing clock signal and outputting corresponding parallel sample data; data selection circuits are used for transition detection on the corresponding parallel sample data for each data processing cycle and selecting sample data from the corresponding parallel sample data to output based on the transition detection results. The embodiments of the present application use a simple structure to implement data recovery, reducing layout area and circuit power consumption.

The invention relates to a digital pre-distortion high-precision phase interpolator with a constant input load. The digital pre-distortion high-precision phase interpolator comprises a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit and a control code decoder circuit. The two pre-filter circuits are used for converting the two full-swing square wave signals into two sine clocks; and the phase interpolation core circuit is used for carrying out nonlinear interpolation on the two paths of sine clocks according to the two paths of weight control codes by using a constant input load, and outputting a small-swing signal. According to the phase interpolator, the interpolation precision is greatly improved, digital pre-distortion of the interpolation weight can be realized by adjusting the control code decoder, the precision of the phase interpolator is further improved, a high-speed and high-precision output clock is realized, and the phase interpolator is suitable for clock generation modules such as a clock data recovery circuit and a phase-locked loop in a high-speed SerDes system.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit, and a phase control circuit. The phase detector samples an input data signal according to a first clock signal to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device to generate a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device to generate a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates a plurality of second clock signals according to the frequency control signal. The phase control circuit controls a phase of the second clock signals according to the phase control signal to generate the first clock signal.

A method of reducing bit error rate in a PAM4 clock data recovery circuit is described. The method includes determining a first target value of a slicing level, sweeping down from an upper voltage threshold to determine a first reference voltage value, and detecting a first filtered analog output associated with the first reference voltage value. The method also includes sweeping up from a lower voltage threshold to determine a second reference voltage value and detecting a second filtered analog output associated with the second reference voltage value. The first reference voltage value and the second reference voltage value are averaged to determine a calculated threshold value.

The invention relates to a clock data recovery circuit and method and electronic equipment, and belongs to the field of data recovery. The clock data recovery circuit comprises a synchronous sampling module, a jump edge detection module and a latch delay module, the synchronous sampling module is configured to perform synchronous sampling on a received data symbol transmitted by each data transmission line in the plurality of data transmission lines by using an oversampling clock signal to obtain a first data symbol transmitted by each data transmission line; the jump edge detection module is configured to output a jump indication signal after detecting that the first data symbol has a jump edge; the latch delay module is configured to perform delay latch on the hopping indication signal, delay the hopping indication signal for a specified time length and then output the hopping indication signal to obtain a recovery clock signal, and the recovery clock signal is used for performing data recovery on the first data symbol. According to the invention, the processing delay of the CDR circuit can be shortened, and more line delay time is reserved for state switching of equipment at the transmitting end and the receiving end.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The invention discloses a high-robustness pulse position modulation signal receiver, and the receiver comprises a clock data recovery circuit which receives a PPM signal, carries out the continuous frequency division processing, and generates two clock signals CLKB and CLKJZ; the PPM decoding circuit is used for outputting demodulation data and feedback signals; the self-calibration current feedback circuit is used for receiving clock signals CLKB and CLKJZ and a feedback signal, selecting one of the CLKB and the CLKJZ to be output to the PPM decoding circuit based on judgment on the feedback signal, and outputting a control word ICTRL to the current digital-to-analog converter; and the current digital-to-analog converter is used for inputting a reference current IBG and the control word ICTRL from a band-gap reference and outputting a current ICP to the PPM decoding circuit. The decoding circuit has the advantages of being simple in structure, low in power consumption, high in robustness and the like, and data demodulation of PPM signals can be achieved more reliably.

The present invention discloses a clock data recovery circuit, processing chip, and display device, wherein a phase detector compares a reference clock signal and a data signal to generate an initial pulse signal; a pulse width adjustment circuit performs shift register processing on the initial pulse signal to generate a shift pulse signal, and generates a target pulse signal based on a current operating mode selection signal, the shift pulse signal, and a reference clock signal; a charge pump circuit charges and discharges according to the target pulse signal to output a voltage signal; and a voltage-controlled oscillator outputs a reference clock signal based on the voltage signal. Because the clock data recovery circuit includes a pulse width adjustment circuit capable of adjusting the initial pulse signal, and because the circuit adjusts the initial pulse signal based on the reference clock signal, the pulse width of the pulse signal can be adjusted as needed without using additional signals, thereby improving the flexibility of the clock data recovery circuit.

The present application relates to electronic endoscope technical field, specifically, it relates to a kind of endoscope multiplexing line built-in MIPI-CSI signal long-distance transmission isolation enhancement device.It includes the control end module, receiving end module and power management unit integrated in multiplexing line, and power management unit is used to power control end module, receiving end module.Power management unit in the present application, by the high integration of control end module, receiving end module and power management unit in multiplexing line, signal conditioning and isolation enhancement unit of control end can effectively process original signal and inhibit common-mode interference, then with the equalization compensation and clock data recovery circuit of receiving end repair signal attenuation and timing distortion problem caused by long-distance transmission, to realize in complex electromagnetic environment still can stable output low jitter, high integrity video signal, fundamentally solve the problem of affecting diagnostic accuracy due to image delay, quality decline.

Embodiments of the present application provide a receiving circuit, a source driver chip, a display device, and a data channel selection method. The receiving circuit includes a first receiving module, a second receiving module, a detection circuit, and a selection circuit; the first receiving module corresponds to a first data channel; the second receiving module corresponds to a second data channel; the first receiving module includes a first analog front end and a first clock data recovery circuit connected electrically; the second receiving module includes a second analog front end and a second clock data recovery circuit connected electrically; the detection circuit is connected to the first analog front end, the second analog front end, and the first clock data recovery circuit respectively, and is configured to output a channel selection signal based on the received first signal, second signal, and frequency lock signal. By adopting the embodiments of the present application, automatic detection and control of the data channel can be performed without consuming additional chip pins, thereby reducing the number of chip pins and reducing the dependence on the timing control chip.

The application discloses a decision feedback equalizer for PAM4 encoding band infinite impulse response filter, belongs to the field of signal processing, and comprises a high-pass filter and a linear equalizer, a decision feedback adder, and an infinite impulse response filter coefficient feedback control module; noise filtering is performed on a high-speed signal, low-frequency attenuation of the high-speed signal is compensated, a tailing effect in a frequency response is eliminated, high-speed inter-symbol interference is suppressed and eliminated, and an offline post-cursor in the frequency response is fed back and compensated; meanwhile, aiming at PAM4 encoded data, an RLM (Level separation mismatch ratio) calibration module and a clock data recovery circuit are added, which are used for improving the speed of clock receiving and recovery, and due to the addition of more high-speed modules, the load of the equalization adder is increased; the application uses a layout planning of a double-difference six-port mutual inductance bridge type (T-coil) inductive network, and bandwidth is expanded by using inductive peaking technology.

A pulse amplitude modulation transition density trigger in a test and measurement instrument is provided. A test and measurement instrument comprises: an input for receiving a pulse amplitude modulated n-level (PAMn) signal; an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal; an acquisition memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform; a trigger circuit coupled to the ADC and the acquisition memory and configured to generate a trigger signal to cause the test and measurement instrument to trigger acquisition of waveforms; a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal; and a conversion detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit, and configured to detect a symbol conversion based on the decoded bits, and to cause the trigger circuit to generate a trigger signal in response to detecting a particular symbol conversion.

Clock data recovery system with: a feedforward equalizer configured to equalize a first input signal received from an analog-to-digital controller based on a plurality of received tap coefficients, thereby producing a first output signal; an adder configured to add the first output signal and a feedback signal from a decision feedback equalizer, thereby producing a second output signal; a double limiter configured to receive the second output signal and provide a first group of preliminary decisions to a decision feedforward equalizer, the decision feedforward equalizer providing an equalized output signal; a second adder configured to generate a first error signal based on the equalized output signal from the decision feedforward equalizer, wherein the plurality of received tap coefficients are based on the error signal; and a clock data recovery circuit configured to receive the first output signal and provide a setting signal for the analog-to-digital controller.

A phase selector / phase interpolator circuit which includes two phase selector circuits and one phase interpolator circuit, each phase selector circuit includes N first tail current tubes, N phase selector units, a current source circuit and a comparison circuit. The current source circuit is selected as a load of the phase selector circuit. The comparison circuit compares a common-mode voltage of the two output clock signals output from the phase selector unit with a reference voltage, and performs negative feedback regulation on the first bias voltage of the first tail current tubes, so that the common-mode voltage can be controlled to be equal to the reference voltage, a tail current of the first tail current tubes is controlled to be equal to the current of the current source circuit, and the output waveform becomes a linear triangular wave.

A receiver circuit includes an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on an equalization coefficient, a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, generate a data sample signal including a plurality of data bits by sampling the equalized signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalized signal in synchronization with the edge clock signal, and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

The present application discloses a clock data recovery circuit system and a clock recovery operation method based thereon. The clock data recovery circuit system includes: a data detection control module, a phase detector, a filter, and a voltage-controlled oscillator. The first input of the phase detector is used to receive a signal to be processed, and the second input of the phase detector is connected to the output of the voltage-controlled oscillator, which is the output of the clock data recovery circuit system. The filter includes: a gain module, an integration module, and an adder. The input of the gain module and the input of the integration module are both connected to the output of the phase detector. The clock data recovery circuit system and the clock recovery operation method based thereon solve the problem in the prior art that when the clock data recovery circuit system is started, the integration module is simultaneously started. Due to a large initial frequency difference and insufficient gain of the gain circuit, the integration module is locked into an error interval state, resulting in frequency tracking errors.

A 1-bit digital-to-analog converter includes a clock and data recovery circuit configured to output a recovered clock signal and a recovery signal, based on a 1-bit digital input signal; and a switch to which an analog pulse train based on the recovered clock signal is given. The switch is on / off controlled by the recovery signal, and outputs an analog pulse signal in which the analog pulse train is made intermittent according to the recovery signal.

The present invention discloses a clock data recovery circuit, comprising: a control logic encoder, for converting an S signal into coordinates (si, sq, siq) according to a preset lookup table; a phase-locked loop, for generating a four-phase quadrature clock and providing it to a phase rotator; the phase rotator, for performing phase interpolation on the four-phase quadrature clock by changing the coordinates (si, sq, siq), to obtain a center sampling clock and an edge sampling clock; a data sampling circuit, for sampling the center position of data according to the center sampling clock, to obtain a first sampling result; an edge sampling circuit, for sampling the edge position of data according to the edge sampling clock, to obtain a second sampling result; a phase detector, for judging whether the center position and the edge position of the data are sampled, and generating a preset signal; a loop filter, for generating an S signal after performing a logic operation on the preset signal, and outputting the S signal to the control logic encoder; the present invention can improve the linearity of the phase rotator.

An ultra wide band receiver with enhanced signal detection capability is provided. In one example, the receiver includes a first processing path including a first despreading circuit that despreads a received UWB signal based on a first bit value to generate a first amplitude value; a second processing path comprising a second despreading circuit, the second despreading circuit despreading the received UWB signal based on a second bit value to generate a second amplitude value; and a data recovery circuit. The data recovery circuit is configured to compare the first amplitude value with the second amplitude value and output a bit value based on a result of the comparison.

The application discloses an anti-radiation reinforced digital controlled oscillator, a clock data recovery circuit and equipment. The anti-radiation reinforced digital controlled oscillator is connected with an anti-radiation reinforced circuit unit between a digital-analog converter (DAC) and a voltage controlled oscillator (VCO). The anti-radiation reinforced circuit unit comprises a voltage replication unit and a multiplexer. The voltage replication unit is used for replicating a control voltage signal output by the digital-analog converter (DAC) and generating a replication voltage signal to be sent to the multiplexer. When the digital-analog converter (DAC) is subjected to single particle bombardment, the output of the multiplexer is switched from the control voltage signal to the replication voltage signal. The application aims to solve the problem that the traditional DCO type clock data recovery circuit is easily affected by single particles when running in a radiation environment, resulting in single particle function interruption and causing space task failure. The anti-radiation reinforced ability of the DCO type clock data recovery circuit when running in a radiation environment is improved.

Example embodiments describe a CDR, circuitry (400) for sampling a burst serial data signal (401) characterized by a data symbol period; the burst serial data signal containing at least a preamble and data portion (401b); the CDR circuitry is configurable in a first mode (403a) for detecting (440) a sampling position when receiving the preamble portion, and in a second mode (403b) for sampling (410) the data portion. The CDR comprises i) a sampling circuitry (410) to sample the signal by at least one sampling clock (404); ii) a sampling clock generator (450) to generate from a reference clock signal (405) with a configurable phase shift (408) one first and one second sampling clock (404a, 404b) for sampling the burst serial data signal by the sampling circuitry when in the respective first and second mode, and to generate the second sampling clock (404b) for sampling times per data symbol period, and to generate the first sampling clock (404a) such that the sampling circuitry samples different sampling positions within an equivalent data symbol period during data symbol periods by adjusting the sampling period of the at least one first sampling clock signal by a sampling offset,, during the sampling of the data symbol periods; and iii) an edge detection circuitry (440) configured to, in the first mode, determine a sampling position from the sampled predefined pattern, and configured to derive the configurable phase shift from the determined sampling position and the applied sampling offset.

An ultra-wideband receiver (500) with enhanced signal detection capabilities is provided. In an example, the receiver (500) includes a first processing path comprising a first spread-out circuitry (522) that spreads a received UWB signal based on a first bit value to generate a first magnitude value; a second processing path comprising a second spread-out circuitry (532) that spreads the received UWB signal based on a second bit value to generate a second magnitude value; and a data recovery circuitry (568). The data recovery circuitry (568) is designed to compare the first magnitude value with the second magnitude value and output a bit value based on the comparison.

An interface circuit has a data recovery circuit, a protocol interface circuit and a controller or processor that can be implemented using a finite state machine. The data recovery circuit may be configured to receive a stream of symbols over three wires of a serial bus according to a high-speed mode defined by a Mobile Industry Processor Interface Alliance C-PHY protocol. The protocol interface circuit may be coupled to an output of the data recovery circuit and configured to receive data from the data recovery circuit. The finite state machine may be configured to cause the data recovery circuit to be disabled when an end of transmission is indicated in a first end-of-transmission signal received from the protocol interface circuit.

A test and measurement instrument comprises an input for receiving a pulse-amplitude modulated n-level signal (PAMn), an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal, a capture memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform, a trigger circuit coupled to the ADC and the capture memory to generate a trigger signal to cause the test and measurement instrument to initiate waveform acquisition, a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal, and a transition detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit to detect symbol transitions based on the decoded bits and to initiate the trigger circuit.The trigger signal is designed to generate a response to the detection of a specific symbol transition.