18results about "Oscillations comparator circuits" patented technology

Phase detectors are provided. The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Systems and methods are provided for a phase locked loop. A phase / frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase / frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase / frequency detector.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.

Systems and methods are provided for a phase locked loop. A phase / frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase / frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase / frequency detector.

A high frequency alternating current, HFAC, power supply system is disclosed herein. The HFAC power supply system comprises: at least two inverters configured to provide a redundancy in supply of HFAC power, wherein the at least two inverters are each coupled to provide an HFAC voltage to shared HFAC output supply connections; and a phase error controller configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference, the phase error controller comprising: a phase error detector configured to output a first intermediate signal based on the first input signal and a second intermediate signal based on the second input signal; and a differencing circuit configured to provide the phase control signal based on a difference between the first intermediate signal and the second intermediate signal; wherein the first input signal corresponds to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal corresponds to a timing of the HFAC voltage provided by a second one of the at least two inverters; wherein the phase control signal has a pulse width and a polarity, the pulse width corresponding to a magnitude of the phase difference and the polarity indicating a direction of the phase difference; the system further comprising a controller configured to control a pulse width modulation of the at least two inverters based on the phase control signal.

Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.

A circuit for an edge-based Phase Frequency Detector (PFD) (200) comprising two edge detectors (103), two SR latches (104), one NAND gate (106), and one NOR gate (107). A reference (Ref) (101) and feedback signals (Fb) (102) are provided to the two edge detector (103) which generates a pulse of active low logic. The output of the edge detector (103) is provided to the two SR latches (104), which provide output signals of the phase frequency detectors. The output of two SR latch (104) is buffered though two invertors (201) and additionally connected to a pair of cross-coupled inverters (202) to generate complementary up (UP and UPb) and down (DN and DNb) signals (105). Phase Frequency Detector (PFD) circuit (200) minimize the number of gates, reducing noise and Random Jitter (RJ), enhance dead zone performance and also reduce the duty cycle of the reference (Ref) (101) and feedback (Fb) signal (102) to a minimal 10%.

Circuitry on an integrated circuit has performance characteristics that depend on a combination of configuration parameters (e.g., PLL loop filter cutoff frequency, PLL loop divider ratio, etc.) and a reference clock signal frequency. A frequency of the input signal is measured. Based on the frequency measurement, the circuit is configured with first parameters associated with a first frequency band that the measured frequency lies within. Based on the measured frequency lying within the first frequency band, the range of the first frequency band is adjusted. In particular, the range of the first frequency band is enlarged. This enlargement of the first frequency band introduces hysteresis into the selection of the frequency band. In this manner, the measurement errors of measured frequencies that lie near a frequency band boundary will result in the selection of the first frequency band and use of the first parameters.

Disclosed is an apparatus (100) for high sensitivity phase detection of an electric signal by means of a local oscillator. The apparatus (100) comprises a first mixer unit (110) with a first electric signal connector (111), a first local oscillator connector (112), a first output connector (113), and a first reference connector (114), and the apparatus (100) comprises a second mixer unit (120) with a second electric signal connector (121), a second local oscillator connector (122), a second output connector (123), and a second reference connector (124). The first mixer unit (110) and the second mixer unit (120) are each configured to mix the electric signal with the local oscillator and based thereon produce an output with respect to a potential at the first reference connector (114) or second reference connector (124), respectively. The apparatus comprises a link (140) between the first output connector (113) and the second reference connector (124). The link (140) is configured to provide an input to the second reference connector (124) which is based on an output of the first output connector (113).

Systems and methods disclosed herein include a correction circuit. The correction circuit may include a signal conditioning circuit configured to condition the received reference signal. The correction circuit may include a filter configured to filter a conditioned signal received from the signal conditioning circuit. The correction circuit may include a phase detector circuit configured to generate at least one output signal based on measuring a phase shift between the received plurality of input signals. At least one input signal of the plurality of input signals may include an adjusted signal received from the filter.

The invention relates to a method for determining a phase difference (6) between a measurement signal (4) and a reference signal (5). The method comprises at least converting the measurement signal (4) into a first square wave signal (33) and the reference signal (5) into a second square wave signal (35), each of which is essentially a symmetrical square wave signal (33, 35) whose pulse duration corresponds to half a period, and determining the phase difference (6) by comparing the phases of the two square wave signals (33, 35). Furthermore, the invention relates to a device and optical arrangement for determining and controlling a phase difference between a measurement signal and a reference signal.

A high frequency alternating current, HFAC, power supply system comprises at least two inverters configured to provide redundancy. The inverters are each coupled to provide an HFAC voltage to shared o

Embodiments provide a device that includes a first circuit having a first input to receive a first sine wave signal and a second input to receive a second sine wave signal in quadrature with respect to each other and a current mode logic gate having a first input coupled to a first output of the first circuit and a second input coupled to a second output of the first circuit. The first circuit configured to deliver a first square wave signal and a second square wave signal. The current mode logic gate is configured to deliver a third square wave signal at a first level and a fourth square wave signal at a second level when the first and second square wave signals are simultaneously at their first levels and the first square wave signal is ahead of the second square wave signal.

A phase-locked loop, a method of generating a periodic output waveform, and a clock generation circuit are provided. The phase-locked loop includes a phase / frequency detector, a charge pump, an oscillator, and a realignment path. The phase / frequency detector is configured to receive a reference signal and a feedback signal. The charge pump is configured to receive an output from the phase / frequency detector and generate pulses. The oscillator is configured to generate an output waveform based on the pulses from the charge pump. The realignment path is configured to generate a clock realignment signal to the oscillator based on the output from the phase / frequency detector.

Random number generator (GL) comprises three ring oscillators (GP1, GP2, GP3) and seven bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7). The ring oscillators (GP1, GP2, GP3) comprise delay lines (LO1, LO2, LO3) closed in loops. The delay lines (LO1, LO2, LO3) comprise delays (EO) connected in series between inputs (i-LO1, i-L02, i-L03) and outputs (o-LO1, o-LO2, o-LO3) of the delay lines. Outputs (o-UB1, o-UB2, o-UB3, o-UB4, o-UB5, o-UB6, o-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to outputs (o1-GL, o2-GL, o3-GL, o4-GL, o-5GL, o6-GL, o7-GL) of the random number generator (GL). Inputs (i1-UB1, 12-UB1, 11-UB2, 12-UB2, 11-UB3, 12-UB3, 11-UB4, i2-UB4, 11-UB5, 12-UB5, 11-UB6, 12-UB6, 11-UB7, 12-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to the delay lines (LO1, LO2, LO3) of the ring oscillators (GP1, GP2, GP3) to outputs of selected delays (EO).

Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.

Circuitry on an integrated circuit has performance characteristics that depend on a combination of configuration parameters (e.g., PLL loop filter cut-off frequency, PLL loop division ratio, etc.) and a reference clock signal frequency. A frequency of an input signal is measured. Based on the frequency measurement, the circuit is configured with a first parameter associated with a first frequency band in which the measurement frequency is located. The range of the first frequency band is adjusted based on the measurement frequency being within the first frequency band. In particular, the range of the first frequency band is expanded. This enlargement of the first frequency band introduces hysteresis into the selection of frequency bands. In this manner, a measurement error of a measurement frequency located near the band boundary will result in the selection of the first band and the use of the first parameter.