A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1/DOWN1 signal, first and second integrators for integrating the UP1/DOWN1 signal and outputting an UP2/DOWN2 signal and an UP3/DOWN3 signal, respectively, a pattern generator for receiving the UP3/DOWN3 signal from the second integrator to output an UP4/DOWN4 signal, a mixer for receiving the UP2/DOWN2 signal from the first integrator and the UP4/DOWN4 signal from the pattern generator and generating an UP5/DOWN5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP5/DOWN5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.