7results about "Oscillations comparator circuits" patented technology

Phase detectors are provided. The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.

Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.

A phase-locked loop, a method of generating a periodic output waveform, and a clock generation circuit are provided. The phase-locked loop includes a phase / frequency detector, a charge pump, an oscillator, and a realignment path. The phase / frequency detector is configured to receive a reference signal and a feedback signal. The charge pump is configured to receive an output from the phase / frequency detector and generate pulses. The oscillator is configured to generate an output waveform based on the pulses from the charge pump. The realignment path is configured to generate a clock realignment signal to the oscillator based on the output from the phase / frequency detector.

Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.

Circuitry on an integrated circuit has performance characteristics that depend on a combination of configuration parameters (e.g., PLL loop filter cut-off frequency, PLL loop division ratio, etc.) and a reference clock signal frequency. A frequency of an input signal is measured. Based on the frequency measurement, the circuit is configured with a first parameter associated with a first frequency band in which the measurement frequency is located. The range of the first frequency band is adjusted based on the measurement frequency being within the first frequency band. In particular, the range of the first frequency band is expanded. This enlargement of the first frequency band introduces hysteresis into the selection of frequency bands. In this manner, a measurement error of a measurement frequency located near the band boundary will result in the selection of the first band and the use of the first parameter.