196 results about "Asynchronous network" patented technology

An apparatus, system and method for synchronizing the playback of data transmitted over an asynchronous network. An initialization module may initialize at least two receivers to receive playback data from a transmission module. The transmission module may then transmit to the receivers the playback data, and, in some embodiments, synchronization data. Synchronization data may include a playback indicator by which the receivers may determine an appropriate playback data consumption rate. A buffer module may buffer a predetermined amount of playback data which may be played in response to a start signal individually addressed to the receivers.

A wireless circuit (1100, 1190) for tracking an incoming signal and for use in a network (2000) having handover from one part (Cell A) of the network to another part (Cell B). The wireless circuit includes a processor (CE 1100) responsive to the incoming signal, the processor (CE 1100) operable to generate pulse edges representing network-based receiver synchronization instances (RSIs), and a timekeeping circuitry (2420, 2430, 2450) including an oscillator circuitry (2162), the timekeeping circuitry (2420, 2430) operable to maintain a set of counter circuitries (2422-2428) including a counter circuitry (2422) operable to maintain at least one network time component based on the RSIs and another counter circuitry (2428) operable at least during handover and during loss of network coverage for maintaining at least one internal time component (NC) based on the oscillator circuitry (2162), the set of counter circuitries (2422-2428) operable to account for elapsing time substantially gaplessly and substantially without overlap between the time components during a composite of network coverage, loss of network coverage and handover, and the timekeeping circuitry further including a time generator (2450) for combining the time components from the set of counter circuitries (2422-2428) to generate an approximate absolute time (SGTB). Other electronic circuits, positioning systems, methods of operation, and processes of manufacture are also disclosed and claimed.

An asynchronous network system includes a transmitting apparatus which transmits time-synchronization-information data through an asynchronous network, and information processing apparatuses which share identical time information by receiving the time-synchronization-information data. At least one data item whose transmission and reception within a predetermined reaching time are requested to be guaranteed is transmitted by one information processing apparatus among the information processing apparatuses to at least one of the other information processing apparatuses in a state in which the one information processing apparatus occupies a first interval on a communication schedule based on time-synchronization information represented by the time-synchronization-information data.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

A centralized clock distribution mechanism for synchronous TDM communications traffic transported over asynchronous networks such as Ethernet networks. The centralized clocking mechanism of the present invention distributes a high accuracy central clock source to a plurality of CES modules over an Ethernet network. Clock synchronization information based on a high quality clock reference source is distributed to circuit emulation service (CES) modules in the network. CES modules receive the clock synchronization information and use it to reconstruct a local clock. A plurality of clock distributors provide clock redundancy whereby each CES module selects the best clock source to use in reconstructing the local clock.

Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

Methods and apparatus for achieving agreement among participating network devices in an asynchronous network for deciding on a common value is disclosed, whereby the common value is validated by a justification and both together satisfy a predetermined predicate. Moreover, a method for reliably broadcasting messages in an order within the asynchronous network is described. Up to one third or more of the participating network devices might be faulty in arbitrary ways.

A system and method for clock synchronization in a network having one or more asynchronous data links is provided. A clock signal is propagated through, at the physical layer, a sequence of network devices linking a source network device to a destination network device of the network. Each asynchronous data link between the source network device and the destination network device is adapted to receive an incoming clock signal from the previous network device and then provide a clock signal synchronized to the received clock signal to the next network device of the sequence. At the same time, each network device of an asynchronous segment of the network can continue to transmit packets of data asynchronously. By locking the link-based frequency on a per link bases, the receiver clocks located at the edge of a network can be tied directly to a primary source located in the core network.

A system for transmitting real-time data between an asynchronous network (104) and a synchronous network (106) is disclosed. A method (100) may include an ingress path (102) for transmitting data from an asynchronous system (104) to a synchronous system (106), and an egress path (108) for transmitting data from a synchronous system (106) to an asynchronous system (104). An ingress path (102) may include a packet receiver (110) and write to synchronous system (112) steps. An egress path (108) may include read from synchronous system (114), packetizer (116), and packet transmitter (118) steps.

A method and a system for synchronizing audio/video messages and message-related information stored in a workstation with audio/video messages and message-related information stored in a server. A copy of the message-related information stored in the workstation is transferred to the server. The workstation identifies workstation messages that have not been transferred from the workstation to the server. A copy of the identified messages are transferred to the server. The server identifies messages in the server that have not been transferred to the workstation. The server transfers to the workstation the messages identified by the server. The server merges the message-related information transferred to it by the workstation and transfers a copy of the merged message-related information to the workstation.

A novel clock method and synchronization mechanism for recovering and distributing a centralized clock source synchronously over legacy asynchronous network devices such as legacy optical Ethernet devices that do not support synchronous Ethernet. An external device functions transparently to provide legacy optical Ethernet devices a clock synchronization and distribution mechanism. The external devices implement a clock conversion scheme whereby multiple clocks having diverse rates are converted to clock signals all having a common rate. One of the converted clocks is selected and all downstream clock signals are then derived from this clock. A high quality clock source located anywhere on the network is distributed throughout the network thus turning an asynchronous Ethernet network into a synchronous Ethernet network. Synchronous TDM data streams can then be easily transported over the Ethernet network.

A system (100) for receiving data from an asynchronous network and transmitting such data onto a synchronous network includes a voice packet buffer memory system (108) with a jitter buffer (118) having groups of entries storing data for voice channels and jitter buffer valid bit (JBVB) memory (120) for status of a particular entry for multiple jitter buffer groups. Writing or reading data from a jitter buffer entry sets a corresponding JBVB memory bit to a valid or invalid state respectively. Jitter buffer data may be read with a corresponding state memory bit. If a corresponding JBVB memory bit is valid, data from a jitter buffer (118) may be provided as an output. If a corresponding JBVB memory bit is invalid, a loss recovery algorithm may compensate for such invalid jitter buffer data.

A communication access protocol improves the accessibility of devices operating on an asynchronous network (100), while supporting reduced power consumption. The network (100) includes a mediation device (130) for facilitating communications among network devices. Generally, each network device periodically transmits beacon signals to advertise its presence, and listens for communication signals targeted at the network device (532, 534). A device initiating communication with another operates in one of at least two operating modes in order to establish communications (536, 537, 538). In one mode, the initiating device communicates with the mediation device in order to derive timing information for the other device (537). In another mode, the initiating device listens to receive beacon signals directly from the target device in order to synchronize communications with the device (538). The selection of one of the two operating modes depends on a control parameter established for the initiating device, which in one embodiment is dependent on the urgency of communication, a maximum number of retries for using the mediation device, or the like.

Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points. These steps are continually repeated on new sets of data points created from newly received synchronization packets using the current delay estimate for the expected delay. And a clock domain at the destination is continually aligned with a clock domain at the source based on the current delay estimate for packets traversing the network between the source and destination.

A remote radio head is disclosed that comprises an interface for connecting the remote radio head to a base station via an asynchronous packet network, an absolute time reference source for (time-)synchronising a signal transceived by the remote radio head. A corresponding method for transmitting a transmit signal at a remote radio head comprises: receiving a data packet at an interface connecting the remote radio head to a base station via an asynchronous network, processing the data packet to form the transmit signal, determining an absolute time reference by means of an absolute time reference source local to the remote radio head, and transmitting the transmit signal in an absolute time-synchronised manner with respect to the absolute time reference. A method for receiving a receive signal at a remote radio head is also disclosed.

The present invention provides a method of wireless communication with at least one mobile unit and at least two base stations. The method includes determining a phase difference between at least two timing signals associated with said at least two base stations based upon timing information provided by said at least one mobile unit from at least one known location.

Flexible attributes are attached to network requests that may be executed asynchronously. Any number of criteria may be attached to network requests. The requests are queued until the associated criteria are satisfied. Once the criteria are satisfied, the request is executed. Applications that make the requests are provided with simple success and failure notifications that they can respond to with various logic. Any type of criteria may be attached to a request. The criteria may be associated with the requests at design time of the application using a graphical user interface.