118 results about "Asynchronous system" patented technology

A system and method for securely making payments and deposits is disclosed. A method for securely and synchronously making a payment includes the steps of submitting a transaction request to a transaction center, the transaction request including details of a transaction between a customer and a third party, confirming the transaction request with the customer by communicating with a customer securely identifiable device, submitting the transaction request for approval, and paying the third party. A method of securely and synchronously making a deposit includes the steps of submitting a deposit request from a depositor to a transaction center, confirming an authorization request with the depositor by communicating with a customer securely identifiable device, receiving an authorization from the depositor, and depositing a deposit amount in a third party receiver account. Secure and asynchronous systems and methods are also disclosed.

Loss of optical signal is detected in a synchronous communications system by detecting features of a monitor signal occurring at a detection frequency corresponding to the frame rate. Since the frame rate is substantially less than the bit rate, monitoring and detection can be performed at a lower bandwidth than the bit rate. An auto-correlation circuit utilises delays which are an integral multiple of the frame rate and produces a detection value which is compared with a threshold value. Alternatively, detection may be based on a power measurement of a band pass filtered monitor signal by setting the lower bandwidth limit above zero frequency and normalizing the measurement of power relative to an average power measurement. A loss of signal may then be detected by a change in power measurement relative to a threshold and can be used for asynchronous systems as well as synchronous systems. Loss of signal detection may be utilised to control an optical switch to re-route optical signals and generate alarm signals. The use of such detection in all optical networks avoids the requirement for electronic processing at the bit rate as a means of detection of loss of signal.

A system for transmitting real-time data between an asynchronous network (104) and a synchronous network (106) is disclosed. A method (100) may include an ingress path (102) for transmitting data from an asynchronous system (104) to a synchronous system (106), and an egress path (108) for transmitting data from a synchronous system (106) to an asynchronous system (104). An ingress path (102) may include a packet receiver (110) and write to synchronous system (112) steps. An egress path (108) may include read from synchronous system (114), packetizer (116), and packet transmitter (118) steps.

Disclosed is a method and apparatus for providing uplink packet data services through an E-DCH in an asynchronous WCDMA system. A transport block size (TBS) for transmitting uplink transport channel data is determined. A combination of a spreading factor and a modulation scheme for uplink channel data transmission, corresponding to the determined TBS, is selected according to transmittable physical channel data bit sizes and puncturing limit values. The TBS is transmitted by incorporating it into control information of the uplink transport channel data. The modulation scheme and spreading factor combination is determined based on a physical channel data bit size that maximizes transmission efficiency and minimizes the number of punctured bits, without requiring an additional physical channel in transmitting the uplink data having the TBS. This method maximizes uplink transmission efficiency to save transmission resources and reduces signaling overhead required to transmit E-DCH control information.

Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.

A computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An I/O hub, which is coupled to a plurality of input/output buses, includes a RAMDAC. An interconnect bus couples the first integrated circuit and the I/O hub and carries both graphics data to or from a frame buffer and also carries asynchronous system data between the processor and the input/output integrated circuit. The frame buffer may be located in the I/O hub to reduce graphics traffic over the interconnect bus.

The present invention relates to a spreading code synchronization method and others for implementing fast cell search during entry of a mobile station into a soft handover mode in an intercell asynchronous system. In the spreading code synchronization method according to the present invention, a correlation is first detected between a received signal and a common short code, and a received timing of a scrambling code mask of a handover destination cell is detected based thereon. At this time, in order to avoid reception of a signal transmitted from a connecting cell, a received timing of a mask symbol from the connecting cell is excepted from a search range for the received timing of the scrambling code mask of the handover destination cell. The spreading code synchronization method further includes steps of detecting for each of scrambling code candidates a correlation between the received signal and a code of a product of a scrambling code and a common short code at the received timing of the scrambling code mask of the handover destination cell detected, and identifying the scrambling code of the signal transmitted from the handover destination cell, from magnitudes of correlation values.

A method allows two substantially asynchronous system components of a logic emulation system to exchange data packets with reference to a clock signal of predetermined frequency. In one example, each bit is transmitted across the system components over two or more cycles of the clock signal. The reference clock signal can be distributed to the two system components from a common clock signal generator, or can be generated locally independently.

The present invention extends to methods, systems, and computer program products for synchronizing clocks in an asynchronous distributed system. Embodiments of the invention facilitate creation of a trustable and practical common time (time of day) reference across a set of peer nodes (observers), such as, for example, members within a common asynchronous (distributed) system. A class of pseudo synchronous system can be created via tracking and accumulating worst case relativistic time skews amongst pairs of nodes (observers), without reference to a common master. As such, cooperating nodes can essentially guarantee a lower bound on the time-of-day that one node will observe, given an observation on another node. Accordingly, embodiments of the invention can be applied to provide a consistent (essentially safe) view of the worst case (i.e., greatest variance in) current time across such an asynchronous system—without a common external time-of-day clock entity being used.

The invention provides a device and a method for processing clock-domain-crossing asynchronous data, a chip and an operating method of the chip. The device comprises a first data sampling unit, a second data sampling unit, a logical operation unit and a clock signal synchronization unit, wherein the first data sampling unit acquires data and obtains a first data signal in a first clock domain; the second data sampling unit acquires the data and obtains a second data signal in a second clock domain; the logical operation unit receives the first data signal and the second data signal and performs logical operation; the clock signal synchronization unit samples a first clock signal in the first clock domain and/or a second clock signal in the second clock domain to obtain a first synchronous clock signal and/or a second synchronous clock signal; and at least one of the first data sampling unit and the second data sampling unit acquires the data under the first synchronous clock signal and/or the second synchronous clock signal. The method comprises the following steps of: synchronizing clock signals in other clock domains by using a reference clock signal; and sampling the data. By the invention, data synchronism can be ensured, and the processing accuracy of the data is improved.

One embodiment of the present invention provides a system that regulates heat within an asynchronous circuit. During operation, the system monitors a temperature within the asynchronous circuit. If the temperature exceeds a threshold value, the system introduces a delay into the asynchronous circuit that causes signals to propagate more slowly through the asynchronous circuit. This causes circuit elements within the asynchronous circuit to switch less frequently and consequently causes the circuit elements to generate less heat.

A method of handover in a wireless communication system in which an asynchronous system and a synchronous system are mixed is disclosed. The method comprises the steps of: the asynchronous system ordering a dual mode mobile terminal to perform a handover from the asynchronous system to the synchronous system; when the handover order is received at the mobile terminal, the mobile terminal transmitting a frame or a preamble through a reverse traffic channel to the synchronous system, reporting to the synchronous system that the handover is completed and initiating a timer of the mobile terminal which is set according to a predetermined time; the mobile terminal switching from an asynchronous vocoder into a synchronous vocoder when the timer expires; and the wireless communication system switching vocoders of asynchronous and synchronous MSCs when the report is received.

Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system.

The invention particularly discloses a permanent magnet electric transmission system of an urban trolley car, and solves the problem that the operating data of the existing alternating current asynchronous system cannot be detected in real time because the electrical network capacity of an electric car direct current power station is limited. The input terminal of a traction invertor is respectively connected with a brake resistor, a CAN network communication device and one terminal of a filter reactor; the other terminal of the filter reactor is connected with a high-speed fuse; the traction invertor comprises a pre-charge unit, a braking chopping unit, a filtering unit, an inverter unit A, an inverter unit B and a control unit; the output terminal of the inverter unit A is connected with the input terminal of one permanent magnet traction motor; the output terminal of the inverter unit B is connected with the input terminal of the other permanent magnet traction motor; the output terminals of the permanent magnet traction motors are respectively connected with the input terminals of corresponding reduction gears; the output terminals of the reduction gears are connected with a wheel track. The permanent magnet electric transmission system improves the energy saving rate by 18 to 44 percent, is long in the service life of a winding, and improves the operability and the safety of the system.

A method and apparatus for communicating between a plurality of asynchronous transmitting and receiving systems using digital streams arranged in multiple access frames comprises a master system, which cycles a counter using a clock reference to generate a master count, and uses the master count to establish a master frame count. A slave system cycles a counter using a clock reference to generate a main count, and uses the main count to establish a main frame count. From a difference between the master frame count and the main frame count of the slave system, a frame count offset value is determined. A slave frame count for the slave system is then established by adding the offset value to the main frame count, and thereby aligning the slave frame count of the slave system with the master frame count and incrementing the slave frame count when the main count is incremented.

Systems, apparatuses and methods are disclosed for estimating a signal travel time, and thus distance between transceivers, in an orthogonal frequency division multiplexing (OFDM) system. The signal travel time is measured between a transmit time (t_T) and a receive window time (t_window) adjusted by the phase delay (T_Φ). The phase delay (T_Φ) is determined as a difference between a receive time (t_R) and the receive window time (t_window). The receive time (t_R) may be determined based on either an amplitude of the received signal at the receive window time (t_window) or when the received signal crosses a positive-negative axis. In synchronous systems, either a one-way time (OWT) or round-trip time (RTT) may be used for estimation. In asynchronous systems, an RTT is used for estimation.

Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

The invention discloses a method for encoding and decoding an asynchronous space-time code for collaborative multi-point transmission, to solve the problem that the collaborative communication can not be carried out due to time asynchronization and frequency offset during collaborative multi-point joint processing. The method comprises the following specific steps that: (1) user equipment estimates the channel parameter and feeds back the channel parameter to remote wireless equipment; (2) different remote wireless equipment constructs delay convolutional encoding matrixes; (3) the user equipment estimates the overall equivalent channel matrix of the remote wireless equipment; (4) the user equipment constructs the frequency offset matrix; (5) an eNodeB evolutional base station transmits the symbol sequence; (6) the remote wireless equipment carries out space-time coding on the information sequence and sends the information sequence; (7) the user equipment carries out frequency compensation on the received symbol sequence; and (8) the user equipment judges the feedback decoding by using the minimum mean square error and decodes. Due to the adoption of the method, the full-mark set gain can be obtained without carrying out accurate time and frequency synchronization, and the decoding complexity is reduced.

The invention is applicable to the field of chip design, and provides an asynchronous data reading/writing control method, device and system. The method comprises the following steps of: acquiring a reading/writing command from a command initiation end, and generating a command packet, wherein the command packet comprises an enable signal, an address signal and a data signal of the reading/writing command; caching the command packet through the clock trigger of the command initiation end, and setting a caching state signal to be effective at the same time; and setting the caching state signal to be ineffective at the time when the command packet is obtained by a command receiving end through the clock trigger of the command receiving end. In the invention, timely feedback of the caching state and effective isolation among different clock domains are realized by setting the caching state signal to be effective through the clock trigger of the command initiation end at the time when the reading/writing command of the command initiation end is encapsulated and cached and setting the caching state signal to be ineffective through the clock trigger of the command receiving end at the time when the command receiving end acquires the command.

The invention provides a synchronous filter and method for asynchronous data across clock domains. The synchronous filter comprises a synchronization processing unit (30), a combined logic unit (31) and an output sampling unit (32); the synchronization processing unit (30) carries out synchronization processing on a data signal of a clock domain 1, and obtains a data signal of a clock domain 2; the combined logic unit (31) carries out combined logic processing on the data signal of the clock domain 2, and obtains a combined logic processing result; and the output sampling unit (32) samples thecombined logic processing result and the data signal of the clock domain 2, and outputs the data signal of the clock domain 2. The synchronous filter for the asynchronous data across the clock domains provided by the invention effectively reduces the probability of the metastable state of the signals when the data signals are transmitted from the clock domain 1 to the clock domain 2, solves the problem of logic chaos in a post-stage circuit caused by the metastable state, and greatly improves the stability of the circuit.

The invention discloses an asynchronous method for parallel processing of transaction, wherein, the method includes step S102: a transaction request message from an application layer is received and a transaction object which is marked by transaction object identification is created; step S104: the transaction object enters into an initial state and base on the transaction object identification, transaction processing is executed between the application layer and an asynchronous mechanism layer; step S106: after transaction processing is finished, the transaction object is released and the transaction object identification is recycled. The invention not only can solve the problem of mutual interference inside an asynchronous system during parallel execution of a plurality of transactions to increase system efficiency, but also can simplify the development of the asynchronous system.

It is an object of the present invention to propose a sheet computer that eliminates the drawback in operational speed caused by clock delays of a system clock and that is capable of high speed operation. In order to achieve this object, in the sheet computer of the present invention, a display circuit and peripheral circuits connected to the display circuit are fabricated on the same substratum and the peripheral circuits constitute an asynchronous system without global clocking. In the asynchronous system, processes constituting minimum function circuits perform mutual handshaking by channels and drive events actively or passively. The asynchronous system does not use global clocking and it is therefore possible to implement lower power consumption and a higher operational speed.