Synchronous filter and method for asynchronous data across clock domains

Abstract

The invention provides a synchronous filter and method for asynchronous data across clock domains. The synchronous filter comprises a synchronization processing unit (30), a combined logic unit (31) and an output sampling unit (32); the synchronization processing unit (30) carries out synchronization processing on a data signal of a clock domain 1, and obtains a data signal of a clock domain 2; the combined logic unit (31) carries out combined logic processing on the data signal of the clock domain 2, and obtains a combined logic processing result; and the output sampling unit (32) samples thecombined logic processing result and the data signal of the clock domain 2, and outputs the data signal of the clock domain 2. The synchronous filter for the asynchronous data across the clock domains provided by the invention effectively reduces the probability of the metastable state of the signals when the data signals are transmitted from the clock domain 1 to the clock domain 2, solves the problem of logic chaos in a post-stage circuit caused by the metastable state, and greatly improves the stability of the circuit.

Description

technical field [0001] The invention relates to embedded system hardware design, in particular to a synchronous circuit and method for cross-clock domain asynchronous data. Background technique [0002] In the logic design of ASIC (Application Specific Integrated Circuit) and Field Programmable Gate Array (FPGA, Field Programmable Gate Array), there are often signals between multiple clock domains that need to interact, and asynchronous signals across clock domains Whether the interactive processing is reasonable, that is, whether asynchronous signals across clock domains can be sampled stably is one of the key factors for the reliability of hardware circuit design. [0003] Currently there is a method for processing asynchronous data across clock domains, please refer to figure 1 , the pulse signal Pulse_i of the first clock domain needs to be transmitted to the second clock domain. In the first clock domain, use the clock signal CLK1 to generate the pulse signal Pulse_n ...

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Problems solved by technology

Moreover, the pulse holding register can only receive data with a single-bit data width. For asynchronous signals with multiple data widths, the current processing method for asynchronous data across clock domains is not applicable.

[0005] The disadvantages of the prior art are: only single-pulse cross-clock domain asynchronous signals can be synchronously processed, and multi-pulse cross-clock domain asynchronous signals are not applicable; only single-bit cross-clock domain asynchronous signals can be synchronously processed. Multi-bit cross-clock domain asynchronous data of data bus type is not applicable

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