Application of Single Clock Data Synchronization Circuit in Data Transmission

Abstract

The present invention relates to the field of data transmission, the invention particularly relates to the application of a single clock data synchronization circuit in data transmission, including asynchronization processing unit for synchronizing a data signal D (CLK1) in a first clock domain to obtain of the second clock domain data signal Q3, a combinatorial logic unit for performing combinational logic processing on the data signal q3 of the second clock domain to obtain a combinatorial logic processing result L, and an output sampling unit for sampling the combinational logic processingresult L and the data signal Q3 of the second clock domain to output the synchronized second clock domain data signal D ', the synchronization processing unit comprising a first sampling unit for sampling the data signal D (CLK1) of the first clock domain to metastably attenuate the data signal D (CLK1) to obtain a data signal Q1 belonging to the second clock domain; The technical scheme providedby the invention can effectively overcome the defect that only the data with single bit data bit width can be received, and the metastable signal is easy to generate, which leads to the logic confusion of the logic circuit of the subsequent stage.

Description

technical field [0001] The invention relates to the field of data transmission, in particular to the application of a single clock data synchronization circuit in data transmission. Background technique [0002] In the logic design of ASIC (Application Specific Integrated Circuit) and Field Programmable Gate Array (FPGA, Field Programmable GateArray), there are often signals between multiple clock domains that need to interact, and the interaction of asynchronous signals across clock domains Whether the processing is reasonable, that is, whether the asynchronous signal across the clock domain can be sampled stably is one of the key factors for the reliability of the hardware circuit design. [0003] Currently there is a method for processing asynchronous data across clock domains, refer to figure 1 , the pulse signal Pulse_i of the first clock domain needs to be transmitted to the second clock domain. In the first clock domain, the clock signal CLK1 is used to generate the...

AI Technical Summary

Problems solved by technology

Moreover, the pulse holding register can only receive data with a single-bit data width. For asynchronous signals with multiple data widths, the current processing method for asynchronous data across clock domains is not applicable.

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