287results about "Single output arrangements" patented technology

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

An input / output (I / O) sensor is provided for a multi-IC (Integrated Circuit) module. The I / O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I / O block, an IC, and / or a multi-IC module. An I / O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

The present invention relates to the technical field of chips, and provides a frequency calibration method, an electronic device, a storage medium and a computer program product, the method comprising: determining a current frequency deviation direction of a tested clock, the current frequency deviation direction being a deviation direction of a current frequency of the tested clock relative to a target frequency; adjusting the calibration step length and the calibration code according to the difference between the current frequency deviation direction and the previous frequency deviation direction; and if the adjusted calibration step length reaches the preset step length, calibrating the output signal frequency of the tested clock according to the adjusted calibration code. According to the method, the overall calibration time is effectively shortened, the defects that the calibration speed is low, the number of iterations is large, and the calibration precision is fixed in a traditional dichotomy method are overcome, and the calibration efficiency and flexibility are remarkably improved.

Devices and methods may include receiving a square wave having a frequency at an input of a harmonic-cancellation (HC) sine-wave generator; receiving a clock signal having a clock frequency at a clock input of the HC sine-wave generator; generating one or more delayed square waves based on the received square wave and the clock signal using one or more delay components of the HC sine-wave generator; and amplitude-scaling the square wave and the one or more delayed square waves using a plurality of taps of the HC sine-wave generator to produce a plurality of amplitude-scaled square waves. The method may include adding the plurality of amplitude-scaled square waves using summing circuitry of the HC sine-wave generator to produce a sine wave having tone at the frequency with suppressed signal strength at selected harmonics of the frequency of the square wave at an output terminal of the HC sine-wave generator.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

Trajectory planning to improve clock skew is disclosed. In one aspect, an array of nodes includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The nodes (202) also include a trajectory plan that includes a plurality of conductive lines to carry communication signals that propagate between the adjacent nodes. The plurality of conductive lines includes a first conductive line (404) configured to carry a first communication signal in a direction opposite the first direction and a second conductive line (402) configured to carry a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

This application relates to a chiplet and an electronic device, and relates to the circuit field. The chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh. The first die and the second die share a first clock signal of the first clock generation circuit, so that clock signals of the first clock mesh and the second clock mesh are synchronized. This resolves a problem of a large clock delay.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

Provided are a control circuit, a semiconductor memory device, and a control method thereof that are capable of efficiently estimating the amount of delay between a first signal and a second signal and generating an output signal according to the amount of delay. [Solution] The control circuit 30 comprises a delay line section 31 to which a start signal start_tdc is input, the delay line section including a plurality of delay units U1 to U8 connected in series; a detection section 32 to which an end signal end_tdc is input, the detection section detecting, when an end signal is input after the start signal is input to the delay line section, the number of delay units among the plurality of delay units through which the start signal has passed before the end signal is input; and a control section 33 that controls the transmission path of the start signal in the delay line section so that the number of delay units through which the start signal has passed before the start signal is output from the delay line section is equal to the number of delay units detected by the detection section.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

A signal driving circuit includes a first driver, a control signal generation circuit, and a second driver. The first driver is configured to generate a first transmission signal based on an input signal and a clock signal. The control signal generation circuit is configured to generate a delay clock signal by delaying the clock signal and to generate a first control clock signal and a second control clock signal with different pulse widths than the pulse width of the delay clock signal. The second driver is configured to generate a second transmission signal, based on the first transmission signal and the first and second control clock signals.

A memory package (20) includes a plurality of memory chips (22), and an interface chip (21) relaying communications between a controller (10) and the plurality of memory chips (22) and receiving a plurality of signals from the plurality of memory chips (22). The interface chip (21) includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to 1 / 2 of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

In some examples, a circuit includes a window comparator circuit. The window comparator circuit is configured to receive a input signal and a feedback signal, determine a delayed representation of the feedback signal based on a window control signal, determine, based on the feedback signal and the delayed representation of the feedback signal, a time window, responsive to a rising edge of the input signal occurring in the time window, or responsive to a falling edge of the input signal occurring in the time window, determine that the input signal and the feedback signal are locked, and responsive to the rising edge of the input signal occurring outside of the time window, or responsive to the falling edge of the input signal occurring outside of the time window, provide a pulse signal having an asserted value for a programmed period of time.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

The invention relates to a pulse injection circuit, a pulse injection method, an audio power amplifier system and electronic equipment. The pulse injection circuit is applied to the audio power amplifier circuit, and the audio power amplifier circuit comprises an input circuit used for inputting a pulse width modulation signal. The pulse injection circuit comprises a detection circuit and a pulse generation processing circuit. Wherein the detection circuit is used for being connected with the input circuit so as to detect a pulse width modulation signal in real time and generate an injection pulse trigger enable signal in response to the pulse width modulation signal. The pulse generation processing circuit is connected with the detection circuit and the input circuit and is used for responding to the injection pulse trigger enable signal to generate a pulse overturning enable signal; performing logic processing on the pulse flip enable signal and the pulse width modulation signal to form a pulse injection signal; and injecting the pulse injection signal into an input circuit to enable the pulse width modulation signal to generate level flipping. The invention can automatically inject the pulse in response to the demand.

A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.

A phase interpolator includes a decoder, a digital-to-analog converter, and a first phase mixer. The decoder is configured to output a digital signal based on a control signal. The digital-to-analog converter is configured to, based on a first current, a second current, and the digital signal, adjust first to third weight signals among a plurality of target weight signals and to output the first to third weight signals. The first phase mixer is configured to determine first and second target clock signals among a plurality of input clock signals, and based on the first to third weight signals, generate a first output clock signal having a phase between the first and second target clock signals as a phase interpolation clock signal.

An example circuit, method, and electronic device configured to filter pulses below a minimum threshold pulse width and provide delays that exhibit low variance to changes in temperature, voltage, and technology processes, are provided. The example circuit includes a first flip / flop, a second flip / flop, and a charge detector. The first flip / flop generates a first out signal and a first inverse signal based on an input signal and a first clocking signal. The second flip / flop generates an output signal and a second out signal based on the first out signal, the first inverse signal, and a second clocking signal, wherein the second clocking signal is an inverse of the first clocking signal. The charge detector circuit includes a charging capacitor to generate a charge signal based on a change in the input signal, such that pulses are filtered based on a capacitance value of the charging capacitor and a reference voltage.

A time to digital converter including multiple delay lines and an output adder. Each delay line includes multiple series-coupled buffers receiving a start signal, multiple latches each having an input coupled to an output of a buffer and an output providing one of multiple binary values in response to a stop signal, and an adder. Each adder adds the binary values from corresponding latches in response to the stop signal and provides a corresponding one of multiple digital output values. The output adder adds the digital output values from the delay lines and provides a digital output value indicative of a measured delay. The start and stop signals may be buffered to provide multiple start and stop signals each provided one of the delay lines. Each start signal may be delayed by one of multiple different delays. Select logic may combine multiple delay lines into a longer delay line group.

A system for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit and an initial setting circuit. The timing circuit may include a delay stage and a gate stage. The delay stage may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.

The embodiment of the application relates to the technical field of electronics, in particular to a PWM signal generation system, which comprises a PWM generation circuit and a clock cycle analysis circuit. The embodiment of the application dynamically adjusts the number of buffers of an initial delay line, and adaptively determines a target number according to a delay signal state, thereby greatly shortening the calculation period of the total number of buffers in the PWM generation circuit and avoiding the time-consuming iterative calculation in the traditional scheme. In addition, the logic of deriving the total number of buffers based on the target number can realize accurate matching of the delay time of the buffer and the clock cycle, improve the control accuracy of the PWM duty cycle by combining the fine delay processing of the delay unit on the PWM signal, and make up for the defects of insufficient accuracy of the traditional circuit. The system also integrates a temperature sensor and a voltage sensor, and the microprocessor can correct the deviation of the delay time of the buffer in combination with the environmental parameters, enhance the stability of the system under complex working conditions, and widen the applicable scenarios of the system in the technical field of electronics.

To compensate for the non-linearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the non-linearities of the interpolated clocks have opposite polarities, they may have different magnitudes causing some non-linearity. A weighted summing PI that sums interpolated clocks of two PI circuits includes a weighted summing circuit that employs a weight signal to generate a weighted summed interpolated clock having an interpolated phase, based on the weight signal, between the phases of the interpolated clocks. As a result, the phase of the weighted summed interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than the other. A weight calibration circuit may be included to select a balanced weight signal to reduce non-linearity in the weighted summing PI.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

According to an embodiment, a delay circuit for a control logic in a converter is provided. The delay circuit includes a first timer circuit having a transconductance amplifier and a first capacitor. The delay circuit includes a second timer circuit coupled to the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor. The second timer circuit is configured to receive an output signal from the first timer circuit to modify a charging current provided by the second current generator or a sum of the first current generator and the second current generator to charge the second capacitor in the second timer circuit.

In one embodiment, a pulse generating device for generating output pulses (P2) with pulse durations in the range of nanoseconds or shorter comprises a signal source (10) for providing an input current (11) comprising input pulses (P1) of an input pulse duration (P1); a pulse shortening circuit (20) coupled to the signal source (10), which has a delay line (21) and is configured to provide the output pulses (P2) based on the input current (11), wherein a pulse duration of the output pulses (P2) is shorter than the input pulse duration; and a heating source (30) coupled to the pulse shortening circuit (20) for providing a heating current (12) for the delay line (21) of the pulse shortening circuit (20). The delay line (21) is designed to heat up to an at least substantially constant operating temperature using the heating current (12).

Embodiments of the present application provide a memory device, a computing device and a method for in-memory computing. The memory device includes an in-memory computing macro and a clock generation circuit. The in-memory computing macro is configured to perform in-memory computation based on a first clock signal. The clock generation circuit is arranged within the in-memory computing macro and is configured to generate the first clock signal. The frequency of the first clock signal is modified according to a condition of the in-memory computing macro to cause the first clock signal to comply with an operating speed of the in-memory computation.

An integrated circuit (IC) includes a clock modulation circuitry including a delay hierarchy circuitry coupled to the register, the delay hierarchy circuitry configured to receive a clock (CLK) signal, provide a delayed master clock (CLKM) signal to a master latch of the register, and provide a delayed slave clock (CLKS) signal to a slave latch of the register.