646results about "Single output arrangements" patented technology

Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and / or based on the fourth pulse signal having the same logical level as the clock signal.

The present disclosure provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit includes a primary side circuit, an isolation circuit and a secondary side circuit. The primary side circuit generates a primary side signal according to a first input signal and a second input signal. The isolation circuit converts the primary side signal into a secondary side signal. The secondary side circuit receives the secondary side signal through the isolation circuit, to generate an output signal. The signal delay setting circuit is coupled to the secondary side circuit, calculates a delay time according to a voltage difference between an alternative terminal and a secondary side ground terminal of the isolation integrated circuit, and delays the secondary side signal according to the delay time, to control the duty ratio of the output signal.

A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

Certain aspects are directed towards an interpolator and / or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

A method is for measuring a time lapse between a trigger and a pulse of a clock of a time-to-digital converter (TDC) device. The method includes the steps of: a) providing a delay line signal to a delay line of a TDC device; b) subsequently, at a measurement clock pulse: obtaining a measurement delay line state representing states of the delay cells; c) subsequently and within half a clock period of the measurement clock pulse: basing the delay line signal on a clock signal and providing the delay line signal based on the clock signal to the delay line; d) subsequently, at a calibration clock pulse: obtaining a calibration delay line state representing states of the delay cells, and e) computing the time lapse between the trigger and the measurement clock pulse based on the measurement amount of delay cells and the calibration amount of delay cells.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

The embodiment of the invention discloses a PWM signal generation method. The generation method comprises the following steps: determining setting delay time and reset delay time of an nth PWM delay signal, and determining a first comparison result of the setting delay time and a preset clock period and a second comparison result of the reset delay time and the preset clock period, and allocating a first delay time to the delay module and allocating a first comparison threshold to the first comparator according to the first comparison result, and allocating a second delay time to the delay module and allocating a second comparison threshold to the second comparator according to the second comparison result. According to the embodiment of the invention, the method does not need to depend on a high-precision clock chip, can achieve the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit, can achieve the delay of the duty ratio, can also achieve the delay of the signal period, is higher in time resolution, and is higher in precision. And more accurate and stable PWM signals can be output.

A phase interpolator circuit has a first stage that selects a pair of phase vectors from among M available sets of pairs and a second stage that interpolates between the selected pair to phase align a sample clock. The interpolation functions applied to selected pairs of phase vectors can differ to account for integral non-linearity, duty-cycle distortion, phase errors, and crosstalk that vary between phase vectors.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

The invention relates to a phase detection simulation circuit, method and device, and the circuit comprises a random signal generation module which is used for generating a random signal; the signal selection module is used for receiving the first simulation delay signal, the second simulation delay signal and the random signal, and selecting the second simulation delay signal or the random signal as a selection output signal according to a comparison result of a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; the sampling simulation register is used for outputting a sampling simulation result signal according to the first simulation delay signal and the selection output signal; wherein the preset threshold range is used for representing the establishment retention time of the sampling register simulated by the sampling simulation register. According to the invention, the simulation of the sampling register under the metastable state is realized, the integrity and reliability of the simulation result are improved, and the reliability of the simulation phase detection circuit on the prediction result of whether the simulation phase detection circuit meets the requirement of the design target is improved.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

According to one implementation, a pulse generator circuit includes a flip-flop receiving an input clock signal, and one or more delay elements where the circuit is configured to adjust a pulse width of an output clock signal independent of a clock period of the input clock signal. According to another implementation, a pulse generator circuit includes a flip-flop receiving an input clock signal, and one or more delay elements where the circuit is configured to adjust a pulse width of an output clock signal. The flip-flop is configured to transmit a flip-flop output signal to the one or more delay elements where the flip-flop output signal includes a state of the flip-flop. The one or more delay elements are configured to delay the flip-flop output signal by a delay period and transmit the delayed flip-flop output to a reset input.

A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal. A second delay line outputs a second delayed signal. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

To compensate for the non-linearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the non-linearities of the interpolated clocks have opposite polarities, they may have different magnitudes causing some non-linearity. A weighted summing PI that sums interpolated clocks of two PI circuits includes a weighted summing circuit that employs a weight signal to generate a weighted summed interpolated clock having an interpolated phase, based on the weight signal, between the phases of the interpolated clocks. As a result, the phase of the weighted summed interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than the other. A weight calibration circuit may be included to select a balanced weight signal to reduce non-linearity in the weighted summing PI.

Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.

A digital phase interpolator includes: first and second phase interpolating units, first and second auxiliary interpolating units, and a buffer unit. The first auxiliary interpolating unit is connected with the first phase interpolating unit between a first input signal and an input end of the buffer unit. The second auxiliary interpolating unit is connected with the second phase interpolating unit between a second input signal and the input end of the buffer unit, and there is a preset phase difference between the first input signal and the second input signal. An output end of the buffer unit is an output end of the digital phase interpolator. Both the first and second phase interpolating units have N basic interpolating units connected in parallel, and weights of the first and second auxiliary interpolating units are both half of the weight of the basic interpolating unit, wherein N is greater than 1.

The invention relates to a synchronous pulse signal delay adjusting circuit, belongs to the technical field of pulse signal delay, and solves the problems of complex structure and low efficiency of a synchronous pulse signal delay adjusting circuit in the prior art. Comprising a delay circuit, a phase detection circuit and a judgment unit, the delay circuit is used for delaying an input synchronous pulse signal when receiving a delay signal and inputting the delayed synchronous pulse signal into the phase detection circuit; the phase detection circuit is used for performing phase detection on the delayed synchronous pulse signal and outputting a sequence corresponding to the current phase; the judgment unit is used for judging whether the current phase is a target phase or not according to the sequence corresponding to the current phase, and if yes, synchronous pulse signal delay adjustment is completed; otherwise, a delay signal is sent to the delay circuit. And rapid synchronization pulse signal delay is realized.

The invention discloses a method and system for improving CT rotation control precision based on a grating ruler. The method comprises the steps that original square waves of two paths of signals output by the grating ruler are received; negation is carried out on the original square wave to obtain a negated square wave; delaying the original square wave to obtain a delayed square wave; carrying out negation on the delay square wave to obtain a delay negation square wave; operation is carried out based on the original square wave, the inverse square wave, the delay square wave and the delay inverse square wave of the single-path signal, and a pulse square wave of the single-path signal is obtained; performing OR operation on the pulse square waves of the two paths of signals, and combining and outputting high-precision pulse square waves; a rising edge of a high-precision pulse square wave is collected to obtain a high-precision grating ruler signal, and quadruplicated frequency output of the signal is realized by converting two paths of square wave signals output by the grating ruler into four paths of pulse signals, so that the measurement precision and the control precision of the grating ruler are improved, and the measurement precision and the control precision of the grating ruler are improved under the condition that the density of grating holes is not increased. And the requirement of high-speed CT equipment on high-precision measurement is met.

An input / output (I / O) sensor is provided for a multi-IC (Integrated Circuit) module. The I / O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I / O block, an IC, and / or a multi-IC module. An I / O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

The embodiment of the invention discloses a clock signal adjusting circuit. The clock signal adjusting circuit comprises a delay phase-locked loop circuit, a duty ratio correction circuit and a quadrant error correction circuit. And the delay phase-locked loop circuit is configured to receive the initial input clock signal and perform delay adjustment based on the initial input clock signal to obtain a plurality of phase-locked output clock signals. And the duty ratio correction circuit is connected with the delay phase-locked loop circuit and is configured to adjust the duty ratio of each output clock signal. And the quadrant error correction circuit is connected with the duty ratio correction circuit and is configured to adjust the phase difference between different output clock signals. Wherein the delay phase-locked loop circuit, the duty ratio correction circuit and the quadrant error correction circuit respond to a delay phase-locked loop reset command and start to operate at the same time.