824results about "Single output arrangements" patented technology

A clock synchronization system and method are provided. The clock synchronization system includes: a pulse generation module, configured to receive an input first signal, perform sampling processing of the first signal to obtain a second signal, and generate a pulse signal according to the second signal; a voltage-controlled oscillator, configured to output a first output clock; the output frequency divider module, configured to perform frequency division on the first output clock, and synchronize, according to the pulse signal, the first output clock which has been subjected to the frequency division, so as to obtain a second output clock; and the synchronous output module, configured to receive the first output clock, the second output clock, the first signal, and the pulse signal, and perform synchronization processing on the first signal according to the first output clock, the second output clock and the pulse signal, so as to obtain a third signal.

The embodiment of the invention discloses a cascade structure delay circuit, a signal delay method applied to a multi-stage delay unit, semiconductor test equipment and a time sequence generation chip, the circuit comprises a clock source, a signal input source and the multi-stage delay unit, and the multi-stage delay unit comprises at least two delay units connected in a cascade mode; the signal input end of the first-stage delay unit in the multiple stages of delay units is connected with a signal input source; and each delay unit in the multiple stages of delay units is used for delaying an input signal according to the delay configuration value received by the respective delay time configuration end, outputting a delayed output signal, and updating the delay configuration value according to the update interval time set by each delay unit. According to the embodiment of the invention, the overall delay precision and delay time range of the multi-stage delay unit is expanded, and the time precision of the synthetic waveform of the time sequence generation device of the semiconductor test equipment is improved.

Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and / or based on the fourth pulse signal having the same logical level as the clock signal.

The present disclosure provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit includes a primary side circuit, an isolation circuit and a secondary side circuit. The primary side circuit generates a primary side signal according to a first input signal and a second input signal. The isolation circuit converts the primary side signal into a secondary side signal. The secondary side circuit receives the secondary side signal through the isolation circuit, to generate an output signal. The signal delay setting circuit is coupled to the secondary side circuit, calculates a delay time according to a voltage difference between an alternative terminal and a secondary side ground terminal of the isolation integrated circuit, and delays the secondary side signal according to the delay time, to control the duty ratio of the output signal.

A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.

The invention discloses a time measuring circuit and a time measuring method. The time measurement circuit comprises an oscillation module used for outputting an oscillation signal within the first level duration of a signal to be measured; the counting control module is used for measuring the number of complete cycles of the oscillation signal; the output signal is overturned at the first rising edge and the last rising edge of the oscillation signal; the logic module is used for outputting to-be-accurately-measured pulses when the to-be-measured signals and the output signals of the counting control module are different in height; the to-be-accurately-measured pulse comprises a first to-be-accurately-measured pulse corresponding to the ending moment of the first level of the to-be-measured signal; the delay module is used for delaying the pulse to be accurately measured into two paths of measurement signals; the state judgment module is used for judging the edge relative positions of the two paths of measurement signals; and the control module is used for determining the time of the pulse to be accurately measured according to the delay value of the control delay module. According to the invention, the time measurement precision can be improved.

Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.

The embodiment of the invention discloses a clock signal quadrature phase error calibration device, a clock signal quadrature phase error calibration method and a chip, relates to the technical field of clock circuits, and facilitates calibration of clock signal quadrature phase errors. The apparatus comprises: a DLL loop configured to generate a plurality of sets of quadrature phase clock signals; the phase error detection module is used for comparing phase differences of two adjacent groups of orthogonal phase clock signals and outputting phase error information; the phase calibration module comprises a delay link and a digital state machine, the delay link is located in the DLL loop and comprises a plurality of cascaded delay units, a first pin of the digital state machine is connected with the phase error detection module, and a second pin of the digital state machine is connected with the DLL loop. And a second pin of the digital state machine is connected with each delay unit of the delay link and is configured to control at least one delay unit in the delay link according to the phase error information so as to calibrate the phase error of the quadrature phase clock signal. The method is suitable for application scenes such as clock signal transmission and control.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

Certain aspects are directed towards an interpolator and / or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.

The invention discloses a signal receiving method and device, which can reduce the peak power of a signal input to an analog-to-digital converter (ADC), thereby reducing quantization noise and improving signal receiving performance. The method comprises the following steps: receiving a first signal by a receiving device, performing down-conversion on the first signal to obtain a second signal, determining a third signal according to the second signal, sampling the third signal, and determining a target signal. Wherein the first signal comprises a target signal, and the target signal adopts comb mapping, that is, the target signal occupies one subcarrier in every M continuous subcarriers. The third signal comprises superposition of K delay signals of the second signal, the delay time associated with the kth delay signal in the K delay signals is # imgabs0 #, T is the time length of the first signal, k = 1, 2,..., K, delta is greater than or equal to 0, M is a positive integer greater than 1, and K is a positive integer greater than or equal to M.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

A method is for measuring a time lapse between a trigger and a pulse of a clock of a time-to-digital converter (TDC) device. The method includes the steps of: a) providing a delay line signal to a delay line of a TDC device; b) subsequently, at a measurement clock pulse: obtaining a measurement delay line state representing states of the delay cells; c) subsequently and within half a clock period of the measurement clock pulse: basing the delay line signal on a clock signal and providing the delay line signal based on the clock signal to the delay line; d) subsequently, at a calibration clock pulse: obtaining a calibration delay line state representing states of the delay cells, and e) computing the time lapse between the trigger and the measurement clock pulse based on the measurement amount of delay cells and the calibration amount of delay cells.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

The embodiment of the invention discloses a PWM signal generation method. The generation method comprises the following steps: determining setting delay time and reset delay time of an nth PWM delay signal, and determining a first comparison result of the setting delay time and a preset clock period and a second comparison result of the reset delay time and the preset clock period, and allocating a first delay time to the delay module and allocating a first comparison threshold to the first comparator according to the first comparison result, and allocating a second delay time to the delay module and allocating a second comparison threshold to the second comparator according to the second comparison result. According to the embodiment of the invention, the method does not need to depend on a high-precision clock chip, can achieve the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit, can achieve the delay of the duty ratio, can also achieve the delay of the signal period, is higher in time resolution, and is higher in precision. And more accurate and stable PWM signals can be output.

A phase interpolator circuit has a first stage that selects a pair of phase vectors from among M available sets of pairs and a second stage that interpolates between the selected pair to phase align a sample clock. The interpolation functions applied to selected pairs of phase vectors can differ to account for integral non-linearity, duty-cycle distortion, phase errors, and crosstalk that vary between phase vectors.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

The invention relates to a phase detection simulation circuit, method and device, and the circuit comprises a random signal generation module which is used for generating a random signal; the signal selection module is used for receiving the first simulation delay signal, the second simulation delay signal and the random signal, and selecting the second simulation delay signal or the random signal as a selection output signal according to a comparison result of a phase difference between the first simulation delay signal and the second simulation delay signal and a preset threshold range; the sampling simulation register is used for outputting a sampling simulation result signal according to the first simulation delay signal and the selection output signal; wherein the preset threshold range is used for representing the establishment retention time of the sampling register simulated by the sampling simulation register. According to the invention, the simulation of the sampling register under the metastable state is realized, the integrity and reliability of the simulation result are improved, and the reliability of the simulation phase detection circuit on the prediction result of whether the simulation phase detection circuit meets the requirement of the design target is improved.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

According to one implementation, a pulse generator circuit includes a flip-flop receiving an input clock signal, and one or more delay elements where the circuit is configured to adjust a pulse width of an output clock signal independent of a clock period of the input clock signal. According to another implementation, a pulse generator circuit includes a flip-flop receiving an input clock signal, and one or more delay elements where the circuit is configured to adjust a pulse width of an output clock signal. The flip-flop is configured to transmit a flip-flop output signal to the one or more delay elements where the flip-flop output signal includes a state of the flip-flop. The one or more delay elements are configured to delay the flip-flop output signal by a delay period and transmit the delayed flip-flop output to a reset input.

The present application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit includes: a first transistor and a second transistor, the potential of the substrate end of the first transistor changes with the change of a first parameter, the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process of the potential generating circuit, and the potential of the substrate end of the second transistor changes with the change of the first parameter. Among them, the gate end of the first transistor is connected to the drain end of the first transistor, the substrate end of the first transistor serves as the first output end of the potential generating circuit, the gate end of the second transistor is connected to the drain end of the second transistor, and the substrate end of the second transistor serves as the second output end of the potential generating circuit. Thus, the first output end and the second output end can respectively output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal. A second delay line outputs a second delayed signal. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.