500results about "Single output arrangements" patented technology

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

A method is for measuring a time lapse between a trigger and a pulse of a clock of a time-to-digital converter (TDC) device. The method includes the steps of: a) providing a delay line signal to a delay line of a TDC device; b) subsequently, at a measurement clock pulse: obtaining a measurement delay line state representing states of the delay cells; c) subsequently and within half a clock period of the measurement clock pulse: basing the delay line signal on a clock signal and providing the delay line signal based on the clock signal to the delay line; d) subsequently, at a calibration clock pulse: obtaining a calibration delay line state representing states of the delay cells, and e) computing the time lapse between the trigger and the measurement clock pulse based on the measurement amount of delay cells and the calibration amount of delay cells.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

An input / output (I / O) sensor is provided for a multi-IC (Integrated Circuit) module. The I / O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I / O block, an IC, and / or a multi-IC module. An I / O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

The utility model discloses a switching power supply controller and a switching power supply converter. Comprising a switch control circuit, a drive circuit, a start control circuit and a delay circuit. The starting control circuit is used for sampling a direct-current input voltage to obtain a first sampling signal taking a second reference ground as a benchmark, converting the first sampling signal into a second sampling signal taking the first reference ground as the benchmark, and generating an effective starting indication signal when the second sampling signal is greater than a set threshold voltage; and the control circuit is used for delaying preset time to control the switch control circuit to enable to be started after receiving the effective starting indication signal. Through the design, it is ensured that the switching power supply converter starts to work after surge current limiting of the preceding-stage controller is finished, the system cost is reduced, the reliability and stability of the system are improved, and normal starting and running of the power supply converter are ensured.

Techniques for improving the accuracy of delay line calibration schemes. For example, an amount of offset may be determined between one or more first portions of a first clock signal and one or more second portions of a second clock signal that is delayed relative to the first clock signal. The first portion(s) may correspond to the second portion(s) based at least on the second clock signal being delayed relative to the first clock signal. In some examples, a value may be determined based at least on the amount of offset. The value may correspond to an amount to adjust the first clock signal to reduce the amount of offset. In some examples, a delay line may then be calibrated, based at least on the second value, to adjust the first clock signal.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

The present invention relates to the technical field of chips, and provides a frequency calibration method, an electronic device, a storage medium and a computer program product, the method comprising: determining a current frequency deviation direction of a tested clock, the current frequency deviation direction being a deviation direction of a current frequency of the tested clock relative to a target frequency; adjusting the calibration step length and the calibration code according to the difference between the current frequency deviation direction and the previous frequency deviation direction; and if the adjusted calibration step length reaches the preset step length, calibrating the output signal frequency of the tested clock according to the adjusted calibration code. According to the method, the overall calibration time is effectively shortened, the defects that the calibration speed is low, the number of iterations is large, and the calibration precision is fixed in a traditional dichotomy method are overcome, and the calibration efficiency and flexibility are remarkably improved.

A control circuit outputs a first control signal and a second control signal to a first control input and a second control input, respectively, of a programmable delay circuit. In certain aspects, the control circuit receives a rising edge of a delay control signal. In response to the rising edge of the delay control signal, the control circuit outputs a rising edge of the first control signal and a falling edge of the second control signal after the rising edge of the first control signal. The control circuit also receives a falling edge of the delay control signal. In response to the falling edge of the delay control signal, the control circuit outputs a rising edge of the second control signal and outputs a falling edge of the first control signal after the rising edge of the second control signal.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

A method of operating a memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, wherein the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase.

A delay control method includes the following steps. A pre-N-value detection operation is performed comprising detecting a number of delayed clock cycles from an input clock signal to an output clock signal as a number of pre-delayed clock cycles before a delay operation is performed. A delay amount is set by a DLL control circuit according to a phase difference between the input clock signal and the output clock signal and the number of pre-delayed clock cycles. A control signal representing the delay amount is output by the DLL control circuit. The delay operation is performed by a delay line circuit according to the control signal, wherein the delay operation comprises delaying the input clock signal based on the delay amount and generating the output clock signal so that the input clock signal and the output clock signal are synchronous.

Devices and methods may include receiving a square wave having a frequency at an input of a harmonic-cancellation (HC) sine-wave generator; receiving a clock signal having a clock frequency at a clock input of the HC sine-wave generator; generating one or more delayed square waves based on the received square wave and the clock signal using one or more delay components of the HC sine-wave generator; and amplitude-scaling the square wave and the one or more delayed square waves using a plurality of taps of the HC sine-wave generator to produce a plurality of amplitude-scaled square waves. The method may include adding the plurality of amplitude-scaled square waves using summing circuitry of the HC sine-wave generator to produce a sine wave having tone at the frequency with suppressed signal strength at selected harmonics of the frequency of the square wave at an output terminal of the HC sine-wave generator.

A delay-line circuit includes multiple variable-delay circuits and may generate an output signal that is a delayed version of an input signal. A calibration circuit includes an oscillator circuit that may generate an oscillator signal, and may include a replica of at least one of the multiple variable-delay circuits. The calibration circuit may perform an initial calibration of the delay-line circuit and, in response to a completion of the initial calibration, perform a background calibration of the delay-line circuit using the oscillator signal.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

Trajectory planning to improve clock skew is disclosed. In one aspect, an array of nodes includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The nodes (202) also include a trajectory plan that includes a plurality of conductive lines to carry communication signals that propagate between the adjacent nodes. The plurality of conductive lines includes a first conductive line (404) configured to carry a first communication signal in a direction opposite the first direction and a second conductive line (402) configured to carry a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

This application relates to a chiplet and an electronic device, and relates to the circuit field. The chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh. The first die and the second die share a first clock signal of the first clock generation circuit, so that clock signals of the first clock mesh and the second clock mesh are synchronized. This resolves a problem of a large clock delay.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

Provided are a control circuit, a semiconductor memory device, and a control method thereof that are capable of efficiently estimating the amount of delay between a first signal and a second signal and generating an output signal according to the amount of delay. [Solution] The control circuit 30 comprises a delay line section 31 to which a start signal start_tdc is input, the delay line section including a plurality of delay units U1 to U8 connected in series; a detection section 32 to which an end signal end_tdc is input, the detection section detecting, when an end signal is input after the start signal is input to the delay line section, the number of delay units among the plurality of delay units through which the start signal has passed before the end signal is input; and a control section 33 that controls the transmission path of the start signal in the delay line section so that the number of delay units through which the start signal has passed before the start signal is output from the delay line section is equal to the number of delay units detected by the detection section.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

A signal driving circuit includes a first driver, a control signal generation circuit, and a second driver. The first driver is configured to generate a first transmission signal based on an input signal and a clock signal. The control signal generation circuit is configured to generate a delay clock signal by delaying the clock signal and to generate a first control clock signal and a second control clock signal with different pulse widths than the pulse width of the delay clock signal. The second driver is configured to generate a second transmission signal, based on the first transmission signal and the first and second control clock signals.

A phase interpolator includes a decoder, a digital-to-analog converter, and a first phase mixer. The decoder is configured to output a digital signal based on a control signal. The digital-to-analog converter is configured to, based on a first current, a second current, and the digital signal, adjust first to third weight signals among a plurality of target weight signals and to output the first to third weight signals. The first phase mixer is configured to determine first and second target clock signals among a plurality of input clock signals, and based on the first to third weight signals, generate a first output clock signal having a phase between the first and second target clock signals as a phase interpolation clock signal.

Apparatus and methods associated with a switch leakage compensation delay circuit (405a) include a compensation transistor (T0) configured to passively bypass leakage current around a capacitor (C0) connected in series with a control transistor (M0). In an illustrative example, the capacitor (C0) and the compensation transistor (T0) can be connected in parallel between a first node (a0) and a second node (b0). The gate of the compensation transistor (T0) can, for example, be directly connected to its source and the second node (b0). The control transistor (M0) can have its drain connected to the second node (b0). When a control signal turns off the control transistor (M0), the leakage current of the control transistor (M0) can be provided by the leakage current of the compensation transistor (T0), so that the voltage across the capacitor (C0) can remain substantially constant. The delay circuit (405a) can advantageously mitigate the voltage drop across the capacitor (C0) to reduce clock timing skew, for example, in low-speed interleaved ADC operation.

An example apparatus includes: a first metal layer including: a first delay line having a surface area; and a second metal layer including: a second delay line having a surface area overlapping the surface area of the first delay line; and an insulating layer coupled between the first metal layer and the second metal layer.