22 results about "Skew" patented technology

The application discloses a method for compensating internal skew of a differential via channel, comprising the steps of: calculating skew time between differential signals; using obtained material parameters to establish a model of a PCB and a differential via; simulating the established high-precision differential model to obtain S parameters of the differential via structure through simulation; obtaining S parameters and differential internal skew values of a design measurement to calibrate a scale factor of 3D modeling; optimizing stub length difference h in the differential via structure; comparing whether the optimization result meets a design allowed differential internal skew target value, if yes, optimization is completed, and if not, stub length difference h is continuously optimized. The application occupies small layout and wiring space, and the proposed differential via structure compensates for skew of differential phase in time, effectively avoiding the influence of internal skew.

The present disclosure is a parallel signal transmission system comprising: a transmission device that transmits a parallel signal by using a wavelength-multiplexed signal; a reception device that receives the wavelength-multiplexed signal from the transmission device and outputs the parallel signal; and a wavelength switching unit that is connected between the transmission device and the reception device and that changes at least one of the transmission wavelengths of the parallel signal so as to reduce the skew of the parallel signal in the reception device.

The application relates to the field of radio astronomy signal processing, and discloses a radio frequency interference reduction method and device for a phased array radio telescope, wherein the method comprises the following steps: acquiring relative position information of a plurality of navigation satellites, determining potential interference satellites from the plurality of navigation satellites according to the relative position information; acquiring a wideband signal collected by the phased array radio telescope, and determining a plurality of interfered subbands in the wideband signal; matching the interfered subbands with the potential interference satellites, and determining subband interference information of the interfered subbands according to a matching result; acquiring a signal subspace and an interference subspace of the interfered subbands, and then determining a skew projection matrix of the interfered subbands; and simultaneously performing interference reduction and digital beam forming on the interfered subbands according to the skew projection matrix and the signal subspace. The technical scheme provided by one or more embodiments of the application can realize continuous interference reduction of the phased array radio telescope on the in-orbit satellites.

The application provides a minimum phase channel skew correction method and device, electronic equipment and storage medium, and relates to the technical field of communication.The application first acquires training result data corresponding to each line pair of a plurality of line pairs of a target communication system in a training mode, wherein the training result data includes a tap coefficient sequence of a DFE and a received symbol sequence; the plurality of line pairs include a reference line pair and a plurality of to-be-corrected line pairs; then, based on the tap coefficient sequence corresponding to each line pair and a preset cross-correlation operation algorithm, timing offset data is determined; further, based on the timing offset data and the received symbol sequence corresponding to each line pair, the receiving order of each line pair is determined, so as to correct the skew of the target communication system in a data transmission mode based on the timing offset data and the receiving order of each line pair. In this way, skew correction with low complexity and high reliability is realized, the skew correction can be quickly completed in the starting stage, and the accuracy of data transmission is ensured.

A circuit is disclosed that includes timer interleaved (TI) analog-to-digital converter (ADC) circuitry that generates a digital output signal. Correction circuitry receives the digital output signal from the TI ADC circuitry and uses weight values to generate a corrected output signal to correct for time skew. The correction circuitry includes a derivative filter that removes a frequency dependency between the weight value and an input signal to the TI ADC circuitry. Weight update circuitry receives the correction output signal and generates an updated weight value for the correction circuitry. The weight update circuitry includes a notch filter that suppresses spectral content in the corrected output signal to eliminate spurious dependencies during a weight update process.

To provide a composite cable with a small outer diameter and reduced skew. [Solution] The composite cable 1 comprises a bundled core 3 formed by twisting together multiple stranded wires 2 in multiple layers, and a sheath 6 that covers the bundled core 3. The bundled core 3 includes multiple types of stranded wires 2, and the stranded wires 2 include quad stranded wires 21 formed by twisting together two pairs of differential signal lines 210 that transmit differential signals, and multiple quad stranded wires 21 are included in one layer of the bundled core 3.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

Disclosed are integrated circuit structures with buried rails and backside metals for routing input signals to and / or output signals from one or more cells of the integrated circuit structures. Port landing-free connections to input ports and / or from output ports are enabled. As a result, signal routing flexibility is enhanced.

The application belongs to the technical field of optical fiber communication, and proposes a receiver IQ skew measurement method and system based on frequency domain reorganization ZC sequence, comprising: generating ZC sequence based on two different root indexes for the training sequence of the transmitting end; calculating the real part and the imaginary part of the ZC sequence based on orthogonal frequency domain time-frequency transformation, reorganizing the sequence based on the real part and the imaginary part, and taking the reorganized ZC sequence as the training sequence of the transmitting end; and based on the frequency domain, block the received sequence signal, perform conjugate summation on adjacent frequency domain sub-blocks, solve the phase angle based on the summation result, and obtain the IQ skew based on the phase angle. Compared with the prior art, the application reduces the calculation complexity of error solving.

A system for altering an input / output (I / O) data signal of a NAND programming operation includes a skew-gen circuit comprising: a delay block coupled to an input of a two input logic OR gate, and a MUX logic gate coupled to an output of the logic OR gate. The skew-gen circuit is configured to: alter the pulse width of a input data signal by increasing the width of the data high signal and decreasing the width of the data low signal; and output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on the mode.

A sequence pattern generation device that can control skew between lanes of a plurality of lanes by controlling a transmission start timing of a sequence pattern of a plurality of outputs. The sequence pattern generation device includes a primary module 2 and a secondary module 3 each having two outputs of data signals, and a device control unit 16 that, in a case where a start of a sequence of the outputs of the data signals is synchronized, sets delay amounts, aligns phases of clocks of the primary module 2 and the secondary module 3, locks phases of clocks of a primary data generation unit 26 of the primary module 2 and a secondary data generation unit 36 of the secondary module 3, and starts the sequence with the delay amounts set in the primary data generation unit 26 and the secondary data generation unit 36.

The invention provides a time offset signal calibration method for a high-speed time-interleaved analog-to-digital converter. The method comprises the following implementation steps: acquiring a training sample set and a test sample set; constructing a time offset signal calibration network model and carrying out iterative training on the time offset signal calibration network model; and obtaining a time offset signal calibration result. In the process of training a time offset signal calibration network model and obtaining time offset signal calibration results, a full connection module carries out various calibration mapping on time offset signals, and a weighted summator carries out weighted summation on a plurality of preliminary calibration results output by the full connection module based on weight vectors output by a weight generation network. The defect that in the prior art, a single full-connection layer is adopted to conduct calibration mapping on the feature map, and consequently the feature map is difficult to adapt to time offset signals with complex and changeable high-frequency region features is overcome, and the problem that the high-frequency region calibration effect is reduced is solved.

An electronic apparatus includes an alignment unit and a control unit. The alignment unit includes: an alignment roller that supplies a recording medium to a processing unit that performs processing on the recording medium; and a correction motor capable of operating the alignment roller to correct the offset of the recording medium. The control unit drives the correction motor using a first pulse signal having a first frequency, and then drives the correction motor using a second pulse signal having a second frequency lower than the first frequency. And a frequency at which a vibration component having a phase opposite to that of the vibration of the alignment unit can be applied to the alignment unit.

The present disclosure relates to a UCIe receiving end skew calibration method, device and chip, the method comprising: determining minimum phase interpolation and maximum phase interpolation of a clock signal in the case that a UCIe receiving end correctly receives data from a UCIe sending end based on preset minimum skew value and preset maximum skew value of data link skew coding of the UCIe receiving end; obtaining skew calibration value of the data link skew coding of the UCIe receiving end in the case that the clock signal adopts optimal phase interpolation according to the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation and the optimal phase interpolation of the clock signal. The present disclosure helps to solve the problem that the real optimal line delay point on the UCIe receiving end side is ignored due to the nonlinearity between the data link skew coding and the line delay, and helps to improve the robustness of data transmission.

The invention provides an anti-oblique-insertion high-mechanical-stability high-frequency connector, which effectively avoids oblique insertion, ensures smooth butt joint of a contact pin and a jack, and remarkably improves the assembly efficiency and the connection reliability. And a complete shielding layer and impedance matching design is kept, high-frequency signal transmission as high as 20GHz is supported, and the performance is stable. The connector is a female end, and is characterized by comprising an integrated housing structure; a center terminal; the insulator comprises a front positioning cavity and a rear stripped cable positioning cavity, and the front positioning cavity is used for placing the central terminal; the integrated shell structure comprises an insulator positioning and placing cavity, a middle crimping part and a tail cable crimping part which are arranged on the front part in a manner of copying the shape of the insulator; and the insulator positioning and placing cavity, the middle crimping part and the tail cable crimping part are integrally manufactured to form an integral structure.

A skew correction circuit includes a skew value detector configured to delay input data and detect a skew correction value for performing skew correction between a data signal and a clock signal, the skew value detector including a first comparator configured to compare the input data with a capture clock signal and detect a Pass or Fail result; and a controller configured to utilize the skew correction value detected.

The invention provides an isolated clock synchronization device and method for a high-energy physical test. The device comprises a first clock module and a plurality of second clock modules, the first clock module comprises a first FPGA module and a plurality of first photoelectric conversion modules; the first FPGA module comprises a clock source module, a skew clock module and a plurality of main clock modules; the second clock module comprises a second FPGA module, a DAC module, a voltage-controlled oscillator and a second photoelectric conversion module; the clock source module is configured to generate a first clock source signal according to a clock crystal oscillator signal; the skew clock module is configured to generate a second clock source signal according to the clock crystal oscillator signal; the second clock source signal and the first clock source signal have deviation; and the DAC module, the voltage-controlled oscillator and the second FPGA module are configured to perform closed-loop phase compensation, so that the phase of the second clock module is consistent with the phase of the corresponding main clock module. And nanosecond-level phase difference can be eliminated.

This disclosure provides systems, devices, apparatuses, and methods, including computer programs encoded on a storage medium, for radar sensing. A wireless device transmits (314, 414) a broadband radar signal towards a reconfigurable smart surface (RIS) device (122). The wireless device receives (320, 420) a first reflection of the broadband radar signal, the first reflection indicating a plurality of narrowband beam directions associated with the first object detection. The wireless device transmits (330, 430), towards the RIS device (122), narrowband radar signals corresponding to one or more of the plurality of narrowband beam directions. The wireless device receives (334, 434) a second reflection of the narrowband radar signal, the second reflection associated with a second object detection.

A first device includes a first receiver, configured to receive a first signal from a second device over a first connection, corresponding to a first channel, and a second receiver, configured to receive a second signal from the second device over a second connection, corresponding to a second channel; the first receiver includes a first scrambler and a first block counter, and the second receiver includes a second scrambler and a second block counter; and wherein, in response to receiving an instruction to transition the second receiver from a low power state to an active state, the first device is configured to set the second scrambler based on a known relationship between the first scrambler and the second scrambler, and to resolve a skew based on a difference between the first block counter and the second block counter.

Provided are an apparatus and a method for adjusting a skew between data and a clock. The apparatus driven by a supply voltage includes a clock circuit that adjusts a skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop, based on a phase difference between data and a clock. The first loop operation is performed until there is no phase difference between the data and the clock, and the second loop operation is performed until a first slope representing a change in delay of the data with respect to the levels of the power voltage and a second slope representing a change in delay of the clock become identical to each other.

The invention discloses a signal skew compensation apparatus and method. The signal skew compensation apparatus comprises: a clock detection module (1) for detecting a frequency output of an input clock signal; a DELAY module (2) for receiving a data signal and introducing a delay, a delay amount being controlled and delayed data being output based on the frequency detected by the clock detection module (1) and a DELAY value output by a data parsing control module (3); and the data parsing control module (3) for receiving the delayed data and parsing a PING message therein, and adjusting the output DELAY value based on a parsing result. The invention has the advantages of simple implementation, low cost, dynamically adjustable signal skew compensation amount, and high flexibility, real-time performance and efficiency.

The application provides a kind of circuit and method for automatically eliminating SPI interface delay difference, belongs to serial peripheral interface technical field, solve the problem that due to delay difference in SPI interface communication, clock frequency cannot be high, and further affect transmission efficiency;Including De-skew circuit, SPI sending circuit is connected in turn multi-bit data line, De-skew circuit and receiving circuit, the De-skew circuit includes high-precision adjustable delay line group;The method for eliminating delay difference is: using double-edge sampling mode for SPI communication, eliminate the delay difference of SPI slave and SPI host, including first eliminating the delay difference between multi-bit data line connected with receiving circuit, then eliminate the delay difference between clock line and data line;The application realizes the effect of not producing delay difference in the process of SPI interface communication, so that the data effective sampling window is large, improve the clock frequency and transmission efficiency of SPI interface communication.