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Method, apparatus and system for reading and writing data of asynchronous FIFO memory

A first-in-first-out, memory technology, applied in data conversion, electrical digital data processing, instruments, etc., can solve problems such as waste of hardware and power consumption, and achieve the effect of reducing power consumption, saving memory, and reducing management burden

Inactive Publication Date: 2009-02-25
VIMICRO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Because, for those who don't need the full 2 n For the application of this item, this deficiency wastes hardware and power consumption

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  • Method, apparatus and system for reading and writing data of asynchronous FIFO memory
  • Method, apparatus and system for reading and writing data of asynchronous FIFO memory
  • Method, apparatus and system for reading and writing data of asynchronous FIFO memory

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Embodiment Construction

[0070] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0071] One of the core concepts of the embodiments of the present invention is to process the boundary Gray code address jump of the asynchronous FIFO, so that when the FIFO address depth is not a power of 2, the asynchronous FIFO can also be implemented by Gray code. For the asynchronous FIFO that only needs a limited storage space of non-2n Gray code addresses, the present invention reduces unnecessary waste of storage space for storage addresses, thereby saving system memory and reducing system hardware and power consumption.

[0072] refer to figure 1 , shows a flow chart of the steps of Embodiment 1 of a method for writing asynchronous FIFO data according to the present invention, which may specifically include the following ...

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Abstract

The invention provides a data reading / writing method, a device and a system for an asynchronous first-in first-out memorizer. The asynchronous FIFO system comprises a first-in first-out memorizer, an address writing subsystem and an address reading subsystem, wherein the address writing subsystem is composed of an address writing domain gray-code coder, an address writing domain address jumping and locking unit, an address writing domain trans-clock synchronous register, an address writing domain gray-code decoder and an address writing unit; and the reading address domain subsystem is composed of an address reading domain gray-code coder, an address reading domain address jumping and locking unit, an address reading domain trans-clock synchronous register, an address reading domain gray-code decoder and an address reading unit. When the asynchronous FIFO memorizer address jumps to an initial address from a non-two-power boundary, the gray-code output is locked so as to realize stable jumping of the address, so that the asynchronous FIFO can be realized through the gray-code when the depth of the asynchronous FIFO address is not the power of two, thereby saving memory, hardware and power consumption.

Description

technical field [0001] The invention relates to a first-in-first-out system, in particular to a method, device and system for reading and writing data of an asynchronous first-in-first-out memory. Background technique [0002] In modern integrated circuit chips, with the continuous expansion of the design scale, a system often contains several clocks. One problem brought by multiple clock domains is how to design interface circuits between asynchronous clocks. Asynchronous First In First Out (FIFO) provides a simple and fast method to solve this problem. [0003] Asynchronous FIFO is a first-in-first-out circuit widely used in real-time data transmission interfaces to store and buffer data transmission between two asynchronous clocks. It writes data with one kind of clock and reads data with another kind of clock, and transmits real-time data between two different clock systems. In the application, due to the asynchrony of the read and write clocks, the overflow or underf...

Claims

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Application Information

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IPC IPC(8): G06F5/14
Inventor 张浩
Owner VIMICRO CORP
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