984 results about "Frequency compensation" patented technology

An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL).

A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

A single replica current is proportional to current through a main switch of a switching power converter. This replica current may be used for current compensation, detection and response to an overload, detection and response to a super-overload, and combinations thereof. An input voltage is switchably coupled to an output signal generating a load current responsive to a switch control. A replica switch generates a replica current proportional to the load current. A ramp modulation signal may be generated. A voltage ramp of the ramp modulation signal may be adjusted in response to the replica current. A feedback difference signal is compared to the ramp modulation signal to generate a comparison output. Comparison of an overload reference voltage to a replica voltage proportional to the replica current generates an overload signal. The switch control is generated responsive to the comparison output and may be modified responsive to the overload signal.

The present invention is a LDO voltage regulator circuit with common-mode feedback. The LDO voltage regulator includes an error amplifier with a common-mode feedback unit, a pass device and a compensation circuit. A signal from the pass device acts as an input signal to the error amplifier and is compared with another input signal, producing a differential signal. The differential signal is amplified and then provided to the pass device. A capacitor in the compensation unit provides frequency compensation to the LDO voltage regulator. The common-mode feedback unit incorporated into the error amplifier greatly improves a slew rate of a gate voltage of the pass device.

Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

A frequency compensation method for voltage-mode switching regulators is disclosed. A lowpass filter and a bandpass filter are employed in the two signal paths into the dual inputs of PWM comparators. In one embodiment, two zeros are generated to compensate for the L-C output filter poles. Stable operation, low output voltage ripple and fast load transient response are achieved; while the power consumption of error amplifier and the area for implementing on-chip passive components are greatly reduced.

A pulse-width modulated buck regulator includes a feedback control without having any external frequency compensation components to stabilize the feedback control loop irrespective of the reactive component of its load impedance. Additionally, the output voltage is maintained constant not only with feedback but also using a power supply voltage compensation scheme. Thus, the feedback control compensates for resistive losses, thus minimizing hardware. The output voltage is compared with first and second reference voltages. If the output voltage is greater than the first reference voltage, a counter's count is decremented. If the output voltage is less than the second reference voltage, the counter's count is incremented. The counter is disabled if the output voltage is smaller than the first reference voltage and greater than the second reference voltage. The duty cycle of the output voltage is varied in accordance with the counter's count.

The invention discloses a high-sensitivity satellite navigation signal capturing method and a system. The system comprises a digital down-conversion module, an average sampling and block accumulation module, an FFT (fast Fourier transform) module, a circumference shifting module, a local PRN (pseudo random noise) code FFT conjugate memory, a complex multiplier module, an IFFT (inverse fast Fourier transform) module, a differential coherence integration module, a peak detection module and a sequential control module. The digital down-conversion module realizes digital down-conversion operation for satellite digital intermediate frequency signals; the average sampling and block accumulation module averagely samples satellite data and completes a block accumulation function; the FFT module searches code phase frequency domains; the circumference shifting module utilizes Doppler circumference shifting search to replace frequency compensation; the local PRN code FFT conjugate memory stores a local PRN code FFT conjugate result; the complex multiplier module realizes signal de-spreading; the IFFT module calculates different code phase coherence results; the differential coherence integration module accumulates differential coherence energy of de-spread satellite signals; the peak detection module realizes signal capturing output; and the sequential control module controls timing sequence of the various modules of the system. Weak signal capturing speed and sensitivity of a satellite navigation receiver are improved, and parameters can be configured flexibly.

A method and apparatus to dynamically modify the internal compensation of a low drop-out (LDO) voltage regulator is presented. The process involves creating an additional equivalent series resistance (ESR) from an internal circuit. The additional ESR of the internal circuit is sufficient to ensure the DC output stability. This allows the ESR of the output capacitance to be reduced to zero if desired, for improved transient response.

An area-efficient capacitor-free low-dropout regulator based on a current-feedback frequency compensation technique is disclosed. An implementation of a current feedback block with a single compensation capacitor is used to enable capacitance reduction. The resultant low-dropout regulator does not generally require an off-chip capacitor for stability and is particularly useful for system-on-chip applications.

A method and apparatus for single end loop testing for DSL provisioning and maintenance provides testing of the DSL loop using digital techniques including frequency compensation, matched filtering and median filtering, to remove strong background and enhance desired signal for peak detection. The SELT system allows DSL providers to extract loop information from reflective measurements at the central office (CO) so as to determine loop capability of supporting different DSL services. The method and apparatus acquires the desired signal (the far-end echo) which is submerged in the correlated background noise (the near-end echo) by providing a process for detecting loop length and termination types with high accuracy for loops up to 12 kft for 24 AWG and up to 9 kft for 26 AWG by exploiting several digital signal processing techniques including frequency.

The present invention is a voltage regulator circuit with enhanced frequency compensation. The voltage regulator includes an error amplifier, a dynamic bias circuit, an enhanced frequency compensation unit, a pass device and a compensation circuit. A signal from the pass device acts as an input signal of the error amplifier and is compared with another input signal, producing a differential signal. The differential signal is amplified and then provided to the dynamic circuit and the enhanced frequency compensation unit. The enhanced frequency compensation unit is provided such that a zero reference value in a left-hand plane can be generated to optimize the compensation for the voltage regulator circuit. The error amplifier includes a capacitor for compensating an output voltage of the voltage regulator circuit.

The invention discloses an IEEE 1588 accurate clock synchronization protocol-based synchronization system and a synchronization method thereof in the technical field of wireless communication. The system consists of master equipment and slave equipment which are connected through a network, wherein the master equipment comprises a main clock module and a central processing unit (CPU) management control module; and the slave equipment comprises a slave clock module and a CPU management control module. Due to the adoption of a frequency compensation clock provided by Balasubramanian and the like, a frequency adjustable clock counter is constructed and the frequency compensation function is realized; and an improved clock synchronization method is adopted, the limited machine precision of anembedded system, namely influence brought by truncation errors is considered; therefore, higher clock synchronization accuracy is achieved.

The present invention discloses parameter regulating method of non-linear electricity system stabilizer based on frequency domain test and pertains to the technical field of stability control of electric power system. The present invention is characterized in that: test the non-frequency-compensation linear property curves and test the phase angle under different frequency points in the low frequency vibrating range of 0.2 to 2.0Hz from the output point of the stabilizer to the voltage of the generator after the working condition of tested machine unit is fixed; then calculate the lead and lag angle a 1 of the linear part of the output signals of the stabilizer under different frequencies, added with phase angle that has corresponding frequency property, and then decide whether surpass the lead and lag range relative with Delta Omega axle prescribed by national standard; if not surpass, the feedback factor k1, k2 and k3 of the linear part can be calculated out; then the damping coefficient C1 and the gain coefficient C2 can be decided with critical amplification times method and load phase step method. The present invention is easy to be comprehended by commissioning operators and is easy to be populated.

The invention relates to a self-adaption zero-frequency compensation circuit in a low-voltage difference linear voltage regulator. The output end of a transconductance amplifier is connected with a voltage regulation pipe by a voltage bumper, a current detection circuit is connected with the voltage bumper and the common end of the voltage regulation pipe, and the other end is connected with a variable-resistance circuit connected with the compensation end of the transconductance amplifier. In the invention, when a load is higher and current is lower, the current detection circuit can detect the load and the current and the load and the current act on the variable-resistance circuit at the moment to ensure that the resistance is enlarged, and the zero position is also relatively lower; on the contrary, when the load is reduced and the current is enlarged, the resistance value of the variable-resistance circuit is reduced, and the zero position is higher. Therefore, the self-adaption zero can change along with the change of a pole so that the compensation circuit takes the effect of compensation and effectively ensures the stable state of system operation. The compensation circuit successfully solves the problem of poor stability of a low-voltage difference linear voltage regulator so that a load capacitance equivalent series resistance is not really important to the influence on system stability, transient response and ripple waves.

The invention belongs to the technical field of analog IC (Integrated Circuit) design, in particular to a high-bandwidth low-power consumption frequency-compensation three-stage operational amplifier. The amplifier comprises an input stage, a second stage, an output stage, a common mode feedback stage, a comprehension circuit, an internal feedforward circuit, wherein the second stage is connectedwith the input stage, the output stage is connected with the second stage and used for amplifying a signal output by the second stage and driving an external load circuit, the common mode feedback stage extracts the common mode level of the differential output stage and stabilizes the common mode level, the comprehension circuit comprises a traditional trsanscondutance comprehension circuit, a miller comprehension circuit and a resistor for separating a high-frequency zero pole, and the internal feedforward circuit is used for comprehending an internal additional pole and forming a push-pull circuit together with the output stage to reduce static power consumption. The three-stage operational amplifier realizes high gain, high bandwidth and high stability under the condition of little DC power consumption and can be used in a high-speed analog-digital conversion circuit, such as a sigma-delta modulator suitable for the bandwidth of an LTE (Line Terminator Equipment) wireless communication protocol.

The invention discloses a common-mode feedback circuit frequency compensation method of a dual-stage amplifier, which belongs to the analog integrated circuit design field. One common-mode feedback circuit is adopted in the dual-stage amplifier to reduce the area and the power consumption of the feedback circuit; the dual-stage amplifier adopts a fully-differential input/output structure; a differential output terminal is used for sampling the common-mode output level; a first-stage amplifying circuit thereof comprises a controllable biasing circuit; a common-mode feedback control signal controls the first-stage common-mode output level and the second-stage common-mode output level of the amplifier at the same time through the controllable biasing circuit; a feedback amplifier is realized by adopting a dual-stage operational amplifier with miller compensation. The left half plane zero point generated by the feedback amplifier in a loop circuit counteracts a certain left half plane pole in a prime amplifier, thereby forming a stable compensation loop circuit. The common-mode feedback circuit frequency compensation method has the advantages of less feedback circuit elements, lower feedback circuit power consumption, high low-frequency loop gain and better compensation phase margin.

The invention relates to determining a correct code phase of a received, code modulated carrier signal using a correlation portion, a frequency compensation portion, a coherent memory and a non-coherent memory. In order to compensate for a code Doppler effect and/or a carrier Doppler drift effect, a mapping portion maps correlation values either to the coherent memory or to the non-coherent memory. Alternatively, the mapping portion maps correlation values stored in the coherent memory or in the non-coherent memory to new positions. The mapping depends on a frequency compensation applied by the frequency compensation portion and elapsed integration time, and/or on a drift of a frequency offset in correlation values output by said correlation portion.

There is a sort of reference source which has the crack by checking the high electrical source, and it consists of the self-polarization circuit, the regulating circuit, the kernel circuit which has the crack, and the startup circuit. The IPTAT generating circuit of the kernel circuit which has the crack makes the collector current of the Q1 and Q2 of the NPN pipe to equal by that the degenerative feedback which is magnified adjusts its quiescent point, the IPTAT current and the VBE of the Q8 of the NPN transistor which has the negative temperature coefficient in the constant-current circuit are progressed the first compensation of the temperature, at the same time they debase the temperature coefficient. The constant-current circuit produces the polarization by itself, and provides the polarization current to the IPTAT generating current. The operational amplifier circuit advances the plus for the two-stage operational amplifier, the compensation current progresses the frequency compensation for the two-stage operational amplifier. The generating circuit removes the dependency of the reference export VREF to supply voltage by negative feedback effect in order advance the PSRR. The startup circuit removes the degeneration polarization point and it drives the self-polarization circuit to work. The self-polarization circuit provides the polarization voltage for the regulating circuit. The circuit configuration of this invention is simple and new, it does not need the external polarization, the area of this circuit is small, and it has the good temperature coefficient.