Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator

Abstract

The invention relates to a self-adaption zero-frequency compensation circuit in a low-voltage difference linear voltage regulator. The output end of a transconductance amplifier is connected with a voltage regulation pipe by a voltage bumper, a current detection circuit is connected with the voltage bumper and the common end of the voltage regulation pipe, and the other end is connected with a variable-resistance circuit connected with the compensation end of the transconductance amplifier. In the invention, when a load is higher and current is lower, the current detection circuit can detect the load and the current and the load and the current act on the variable-resistance circuit at the moment to ensure that the resistance is enlarged, and the zero position is also relatively lower; on the contrary, when the load is reduced and the current is enlarged, the resistance value of the variable-resistance circuit is reduced, and the zero position is higher. Therefore, the self-adaption zero can change along with the change of a pole so that the compensation circuit takes the effect of compensation and effectively ensures the stable state of system operation. The compensation circuit successfully solves the problem of poor stability of a low-voltage difference linear voltage regulator so that a load capacitance equivalent series resistance is not really important to the influence on system stability, transient response and ripple waves.

Description

【Technical field】 [0001] The invention belongs to a low-dropout linear voltage stabilizer in a large-scale analog integrated circuit, in particular to an adaptive zero-point frequency compensation circuit in the low-dropout linear voltage stabilizer. 【Background technique】 [0002] A typical low-dropout linear regulator in the prior art generally consists of a voltage reference Vref, a transconductance amplifier OTA, a buffer BUFFER, a feedback network composed of voltage dividing resistors R1 and R2, and a voltage regulator PMOS, see figure 1 . Among them, the capacitor CL is the output load capacitor to optimize the transient response, and the resistor ESR is the parasitic equivalent series resistance of the capacitor CL. [0003] figure 1 In the circuit, the load capacitance CL and the resistance seen from node C form the main pole, and the parasitic capacitance at node A and the output resistance of the transconductance amplifier OTA form the second pole. Because the ...

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Problems solved by technology

[0009] The invention successfully solves the stability problem of the low-dropout linear regulator, and makes the impact of the equivalent series resistance ESR of the load capacitor on the system stability, transient response, and ripple not critical

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