43380results about How to "Easy to produce" patented technology

In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfxSiyOz) layer is formed. The silicon content is gradually changed throughout the duration of the HfxSiyOz deposition process. The etching rate for the HfxSiyOz layer in dilute hydrogen fluoride solution is dependent on the silicon content y in the HfxSiyOz layer. The sidewalls of the stacked gradual material layer are etched to form an uneven profile. The lower electrode, the capacitor dielectric layer and the upper electrode are formed on the uneven sidewalls of the stacked gradual material layers, the area between the lower electrode and the upper electrode is increased to improve the capacitance of the charge storage device.

In many processes used in fabricating semiconductors the wafer is seated on the top surface of a pedestal and heated in a high energy process step, such as plasma etching. The pedestal, chuck or platen may be cooling but the wafer gradually heats until the process can no longer continue. Where large, e.g. 300 mm diameter, wafers are being processed the temperature level across the wafer is difficult to maintain substantially constant. In this system and method the lateral temperature distribution is equalized by a heat sink structure in a chamber immediately under the wafer support on top of the pedestal. A number of spatially distributed wicking posts extend downwardly from a layer of wicking material across the top of the chamber, into a pool of a vaporizable liquid. At hot spots, vaporized liquid is generated and transported to adjacent condensation posts extending up from the liquid. The system thus passively extracts heat to equalize temperatures while recirculating liquid and assuring adequate supply. The free volume above and within the liquid, and the short distances between posts, assure adequate heat transfer rates.

A flooring panel or wall panel (20) is provided with a tongue (1) and a groove (2) each comprising cooperating locking means in the form of ribs (11, 12) and grooves (9, 10). The locking means of the upper side and lower side of the tongue (1) and groove (2) respectively are arranged staggered in an insertion direction in which the two panels to be joined to each other are joined to configure a firm joint between two adjoining panels at which an additional surface portion (31; 32; 51) step (31) is provided at the surface area of the upper cheek (3) facing the groove (2) and / or of the lower cheek (5) of the groove which is formed as a step (31) or bevel (32: 51).

A diffractive beam expander (50) comprises an input grating (10), a crossed grating (20), and an output grating (30) implemented on a planar transparent substrate (7). The crossed grating (20) comprises a plurality of diffractive features (23) arranged along the lines of a first set of parallel lines (25) and along the lines of a second set of parallel lines (26) such that the lines (25) of the first set are parallel to the lines (26) of the second set. The lines of the first set have a first grating period and the lines of the second set have a second grating period. A light beam (B1) coupled into the substrate (7) by the input grating (10) impinges on the crossed grating (20) at a first location (EC1) and further locations (EC2). Interaction at the first location (EC1) provides several sub-beams (S00, S01, S10) which propagate in different directions. Further interactions at second locations (EC2) provide further sub-beams (V01, U10) which propagate in the same direction as the original in-coupled light (B1). Light is subsequently coupled out of the substrate (7) by the output grating (30) to provide a light beam (B2) which is expanded in two directions (SX, SZ) with respect to the beam (B0) impinging on the input grating. A virtual display device (200) may comprise said diffractive beam expander (50).

The present invention provides an optical fiber structure that allows for reliable and easy branching of optical fibers, as well as a method of manufacturing such optical fiber structure. The optical fiber structure proposed by the present invention is characterized by a structure wherein multiple optical fiber units, each comprising multiple optical fibers that are aligned two-dimensionally in such a way that one side is covered by a first covering body, are aligned so that the covered surfaces face the same direction, and the covered or uncovered surfaces of the multiple optical fiber units are integrally covered by a second covering body. The second covering body should preferably be made of silicone rubber having a tearing strength of 29 kgf / cm or below.

A field effect transistor which includes, on a substrate, at least a semiconductor layer, a passivation layer for the semiconductor layer, a source electrode, a drain electrode, a gate insulating film and a gate electrode, the source electrode and the drain electrode being connected through the semiconductor layer, the gate insulating film being present between the gate electrode and the semiconductor layer, the passivation layer being at least on one surface side of the semiconductor layer, and the semiconductor layer including a composite oxide which comprises In (indium), Zn (zinc) and Ga (gallium) in the following atomic ratios (1) to (3):In / (In+Zn)=0.2 to 0.8  (1)In / (In+Ga)=0.59 to 0.99  (2)Zn / (Ga+Zn)=0.29 to 0.99  (3).