8642 results about "Crystallite" patented technology

A method for forming a metal interconnect on a substrate is provided. The method includes depositing a refractory metal-containing barrier layer having a thickness less than about 20 angstroms on at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound. The method also includes depositing a seed layer on at least a portion of the barrier layer, and depositing a second metal layer on at least a portion of the seed layer. The barrier layer provides adequate barrier properties and allows the grain growth of the metal layer to continue across the barrier layer into the second metal layer thereby enhancing the electrical performance of the interconnect.

A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide semiconductor film may lead to high contact resistance. One cause of high contact resistance is that a Schottky junction is formed at a contact plane between the source and drain electrodes and the oxide semiconductor film. An oxygen-deficient oxide semiconductor layer which includes crystal grains with a size of 1 nm to 10 nm and has a higher carrier concentration than the oxide semiconductor film serving as a channel formation region is provided between the oxide semiconductor film and the source and drain electrodes.

An anode structure for lithium batteries includes nanofeatured silicon particulates dispersed in a conductive network. The particulates are preferably made from metallurgical grade silicon powder via HF/HNO₃ acid treatment, yielding crystallite sizes from about 1 to 20 nm and pore sizes from about 1 to 100 nm. Surfaces of the particles may be terminated with selected chemical species to further modify the anode performance characteristics. The conductive network is preferably a carbonaceous material or composite, but it may alternatively contain conductive ceramics such as TiN or B₄C. The anode structure may further contain a current collector of copper or nickel mesh or foil.

The present invention provides a method of manufacturing a multilayer semiconductor structure featuring reduced ohmic losses with respect to standard multilayer semiconductor structures. The semiconductor structure comprises a high resistivity silicon substrate with resistivity higher than 3 KΩ.cm, an active semiconductor layer and an insulating layer in between the silicon substrate and the active semiconductor layer. The method comprises suppressing ohmic losses inside the high resistivity silicon substrate by increasing, with regard to prior art devices, charge trap density between the insulating layer and the silicon substrate. In particular this may be obtained by applying an intermediate layer in between the silicon substrate and the insulating layer, the intermediate layer comprising grains having a size, wherein the mean size of the grains of the intermediate layer is smaller than 150 nm, preferably smaller than 50 nm.

The invention provides a thin high-strength hot-rolled steel sheet with a thickness of not more than 3.5 mm which has excellent stretch flangeability and high uniformity in both shape and mechanical properties of the steel sheet, as well as a method of producing the hot-rolled steel sheet. A slab containing C: 0.05-0.30 wt %, Si: 0.03-1.0 wt %, Mn: 1.5-3.5 wt %, P: not more than 0.02 wt %, S: not more than 0.005 wt %, Al: not more than 0.150 wt %, N: not more than 0.0200 wt %, and one or two of Nb: 0.003-0.20 wt % and Ti: 0.005-0.20 wt % is heated at a temperature of not higher than 1200° C. The slab is hot-rolled at a finish rolling end temperature of not lower than 800° C., preferably at a finish rolling start temperature of 950-1050° C. A hot-rolled sheet is started to be cooled within two seconds after the end of the rolling, and then continuously cooled down to a coiling temperature at a cooling rate of 20-150° C./sec. The hot-rolled sheet is coiled at a temperature of 300-550° C., preferably in excess of 400° C. A fine bainite structure is obtained in which the mean grain size is not greater than 3.0 mum, the aspect ratio is not more than 1.5, and preferably the maximum size of the major axis is not greater than 10 mum.

A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.

A carbonaceous material has a plane space d002 of a (002) plane less than 0.337 nm in an X-ray wide angle diffraction method, a crystallite size (Lc) of 90 nm or higher, an R value, as a peak intensity ratio of a peak intensity of 1360 cm<HIL><−1 </SP><PDAT>to a peak intensity of 1580 cm<HIL><−1 </SP><PDAT>in a Raman spectrum in use of an argon ion laser, of 0.20 or higher, and a tap density of 0.75 g/cm<HIL><3 </SP><PDAT>or higher. Also disclosed is a multilayer structure carbonaceous material for electrode, which is manufactured by carbonizing some organic compounds where the carbonaceous material for electrode is mixed with the organic compounds. The battery using the carbonaceous material for electrode or the multilayer structure carbonaceous material for electrode has a large capacity, a small irreversible capacity admitted in the initial cycle, excellent capacity maintaining rate of the cycle, and particularly, largely improved quick charging and discharging characteristics.</PTEXT>

The invention discloses a method for improving the performance of 700 MPa grade V-N microalloyed high strength weathering steel. The method is specific to the characteristics of the sheet billet continuous casting and tandem rolling technology and metallurgy component, and adopts an electric furnace or a revolving furnace to smelt, refine, continuously cast sheet billet which directly enters into a roller hearth to heat after a casting blank concretes, or soaking furnace, hot rolling, laminar flow cooling and wind-up process flow. The chemical composition of molten steel is :C occupies less than or equal to 0.08Wt. percent, Si occupies from 0.25 to 0.75Wt. percent, Mn occupies from 0.2 to 2.0Wt.percent, P occupies less than or equal to 0.025Wt. percent, S occupies less than or equal to 0.040Wt. percent, Cu occupies from 0.25 to 0.60Wt. percent, Cr occupies from 0.30 to 1.25 Wt.percent, Ni occupies less than or equal to 0.65Wt. percent, V occupies from 0.02 to 0.20Wt. percent and N occupies from 0.015 to 0.030 Wt. percent. The invention takes full advantages of the characteristics of the sheet billet continuous casting and tandem rolling short flow process and adopts the V-N microalloyed technique to produce 700 MPa grade high strength weathering steel under the thinning function of VN and V (C, N) nanometer scale precipitate on crystal grain in casting blank of the sheet billet continuous casting and tandem rolling flow and the theory of precipitation strength. By the optimization design of the metallurgy component of V-N microalloyed 700MPa grade high strength weathering steel, the invention increases the low temperature impact ductility of coil of strip and improves the shaping property.

Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

The invention relates to a sputtering target which has a fine uniform equiaxed grain structure of less than 44 microns, no preferred texture orientation as measured by electron back scattered diffraction (“EBSD”) and that displays no grain size banding or texture banding throughout the body of the target. The invention relates a sputtering target with a lenticular or flattened grain structure, no preferred texture orientation as measured by EBSD and that displays no grain size or texture banding throughout the body of the target and where the target has a layered structure incorporating a layer of the sputtering material and at least one additional layer at the backing plate interface, said layer has a coefficient of thermal expansion (“CTE”) value between the CTE of the backing plate and the CTE of the layer of sputtering material. The invention also relates to thin films and their use of using the sputtering target and other applications, such as coatings, solar devices, semiconductor devices etc. The invention further relates to a process to repair or rejuvenate a sputtering target.

To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.

The carbon electrode material of the present invention is used for a vanadium redox-flow cell. The carbon electrode material has quasi-graphite crystal structure in which <002> spacing obtained by X-ray wide angle analysis is 3.43 to 3.60 Å, size of a crystallite in c axial direction is 15 to 33 Å and size of crystallite in a axial direction is 30 to 70 Å. In addition, an amount of surface acidic functional groups obtained by XPS surface analysis is 0.1 to 1.2% and total number of surface bound-nitrogen atoms is 5% or smaller relative to total number of surface carbon atoms. The carbon electrode materials formed of a non-woven fabric of a carbonaceouss fiber is preferable.

A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc₀ while enabling thermal stability, write voltage, read voltage, and Hc values that satisfy 64 Mb design requirements. The NCC layer has RM grains in an insulator matrix where R is Co, Fe, or Ni, and M is a metal such as Si or Al. NCC thickness is maintained around the minimum RM grain size to avoid RM granules not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A second NCC layer and third CoFeB layer may be included in the free layer or a second NCC layer may be inserted below the Ru capping layer.

There is provided a conductive sintered layer forming composition and a conductive sintered layer forming method that can lower heating temperature and shorten heating time for a process of accelerating sintering or bonding by sintering of metal nano-particles coated with an organic substance. The conductive sintered layer forming composition may be obtained by utilizing a phenomenon that particles may be sintered at low temperature by mixing silver oxide with metal particles coated with the organic substance and having a grain size of 1 nm to 5 μm as compared to sintering each simple substance. The conductive sintered layer forming composition of the invention is characterized in that it contains the metal particles whose surface is coated with the organic substance and whose grain size is 1 nm to 5 μm and the silver oxide particles.

It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film, the semiconductor film is crystallized by using a CW laser or a pulse laser having a repetition rate of greater than or equal to 10 MHz. The obtained semiconductor film has a plurality of crystal grains having a width of greater than or equal to 0.01 μm and a length of greater than or equal to 1 μm. In a surface of the obtained semiconductor film, a ratio of an orientation {211} is greater than or equal to 0.4 within the range of an angle fluctuation of ±10°.

It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO₃(ZnO)_m (m=1) are included in an amorphous structure represented by InGaO₃(ZnO)_m (m>0).

A platinum/ruthenium alloy catalyst that includes finely dispersed alloy particles on a powdery, electrically conductive carrier material. The catalyst is particularly resistant to carbon monoxide poisoning when the alloy particles display mean crystallite sizes of 0.5 to less than 2 nm.

Disclosed herein are medical devices. The medical devices generally include a biocompatible nanostructured ceramic material having an average grain size dimension of about 1 nanometer to about 1000 nanometers, a strain to failure of at least about 1 percent, and a cross-sectional hardness greater than or equal to about 350 kilograms per square millimeter. Also disclosed are methods of making and using the medical devices.

A new, cost effective process for the production of ultrafine particles which is based on mechanically activated chemical reaction of a metal compound with a suitable reagent. The process involves subjecting a mixture of a metal compound and a suitable reagent to mechanical activation to increase the chemical reactivity of the reactants and/or reaction kinetics such that a chemical reaction can occur which produces a solid nano-phase substance. Concomitantly, a by-product phase is also formed. This by-product phase is removed so that the solid nano-phase substance is left behind in the form of ultrafine particles. During mechanical activation a composite structure is formed which consists of an intimate mixture of nano-sized grains of the nano-phase substance and the reaction by-product phase. The step of removing the by-product phase, following mechanical activation, may involve subjecting the composite structure to a suitable solvent which dissolves the by-product phase, while not reacting with the solid nano-phase substance. The process according to the invention may be used to form ultrafine metal powders as well as ultrafine ceramic powders. Advantages of the process include a significant degree of control over the size and size distribution of the ultrafine particles, and over the nature of interfaces created between the solid nano-phase substance and the reaction by-product phase.

A composition including a polycrystalline metal nitride having a number of grains is provided. These grains have a columnar structure with one or more properties such as, an average grain size, a tilt angle, an impurity content, a porosity, a density, and an atomic fraction of the metal in the metal nitride.

The invention relates to a process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising the steps:

• • provision of a substrate that has a silicon surface;
  • deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate;
  • optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer;
  • deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer;
  • deposition of a gallium-containing first nitride semiconductor layer on the masking layer,

wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm² in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

The present invention provides a high silica-alumina ratio small crystal grain NaY molecular sieve. The skeleton silica-alumina ratio of NaY molecular sieve, namely. SiO2/Al2O3 mole ratio is 6.0-7.0, and the average grain size is 300-800 nm. It can be made up by adopting non-template agent direct synthesis process. Its preparation method includes the following steps: firstly, stirring and ageing for 0.5-48 hr at 15-60deg.C to obtain crystallization guide agent, then mixing said guide agent, water, silicon source and aluminium source to obtain reaction mixture, then crystallizing said mixture at twice, first steps is dynamic crystallization and second step is static crystallization, finally, filtering, washing and drying so as to obtain the invented high silica-alumina ratio small crystal grain NaY molecular sieve whose relative crystallinity is greater than 80%.

The amount of melting of the bonding wire is closely regulated, and reduction of size and improvement of uniformity of the free air ball is obtained for ball bonding at pitches of less than ninety mils even when bonding wire of reduced diameter is employed. Quenching of the bonding wire adjacent to the free air ball also limits the temperature rise in the bonding wire and the extent of a heat affected zone having less tensile strength and stiffness to less than one micron and with reduced grain enlargement. The present invention provides such a bond for electronic packaging of increased reliability, potential functionality, increased manufacturing yield and reduced process complexity.

Variable property deposit, at least partially of fine-grained metallic material, optionally containing solid particulates dispersed therein, is disclosed. The electrodeposition conditions in a single plating cell are suitably adjusted to once or repeatedly vary at least one property in the deposit direction. In one embodiment denoted multidimension grading, property variation along the length and/or width of the deposit is also provided. Variable property metallic material deposits containing at least in part a fine-grained microstructure and variable property in the deposit direction and optionally multidimensionally, provide superior overall mechanical properties compared to monolithic fine-grained (average grain size: 2 nm-5 micron), entirely coarse-grained (average grain size: >20 micron) or entirely amorphous metallic material deposits.

Methods of making a polycrystalline silicon thin-film transistor having a uniform microstructure. One exemplary method requires receiving a polycrystalline silicon thin film having a grain structure which is periodic in at least a first direction, and placing at least portions (410, 420) of one or more thin-film transistors on the received film such that they are tilted relative to the periodic structure of the thin film.

Improved aluminum-copper-lithium alloys are disclosed. The alloys may include 3.4-4.2 wt. % Cu, 0.9-1.4 wt. % Li, 0.3-0.7 wt. % Ag, 0.1-0.6 wt. % Mg, 0.2-0.8 wt. % Zn, 0.1-0.6 wt. % Mn, and 0.01-0.6 wt. % of at least one grain structure control element, the balance being aluminum and incidental elements and impurities. The alloys achieve an improved combination of properties over prior art alloys.

Lightweight articles comprising a polymeric material at least partially coated with a fine-grained metallic material are disclosed. The fine-grained metallic material has an average grain size of 2 nm to 5,000 nm, a thickness between 25 micron and 5 cm, and a hardness between 200 VHN and 3,000 VHN. The lightweight articles are strong and ductile and exhibit high coefficients of restitution and a high stiffness and are particularly suitable for a variety of applications including aerospace and automotive parts, sporting goods, and the like.

There is disclosed a carbon material from which an electric double layer capacitor (EDLC) having a large capacitance can be fabricated. First, a carbon material is activated to produce crystallites of graphite-like carbon having interlayer distances of 0.365 to 0.385 nm. Positive and negative plates are fabricated using the crystallites.

The present invention provides a method of producing pristine or non-oxidized nano graphene platelets (NGPs) that are highly conductive. The method comprises: (a) providing a pristine graphitic material comprising at least a graphite crystallite having at least a graphene plane and an edge surface; (b) dispersing multiple particles of the pristine graphitic material in a liquid medium containing therein no surfactant to produce a suspension, wherein the multiple particles in the liquid have a concentration greater than 0.1 mg/mL and the liquid medium is characterized by having a surface tension that enables wetting of the liquid on a graphene plane exhibiting a contact angle less than 90 degrees; and (c) exposing the suspension to direct ultrasonication at a sufficient energy or intensity level for a sufficient length of time to produce the NGPs. Pristine NGPs can be used as a conductive additive in transparent electrodes for solar cells or flat panel displays (e.g., to replace expensive indium-tin oxide), battery and supercapacitor electrodes, and nanocomposites for electromagnetic wave interference (EMI) shielding, static charge dissipation, and fuel cell bipolar plate applications.

The invention discloses a superfine WC-Co cemented carbide containing rare-earth elements and a preparation method thereof, belonging to the technical field of cemented carbide. In the cemented carbide, the weight of WC rigid phase accounts for 85-94% of that of the cemented carbide, the weight of Co binder phase accounts for 5-14% of that of the cemented carbide, the weight of grain growth inhibitor accounts for 0.3-2.0% of that of the cemented carbide, and the weight of the thulium in the rare earth addition accounts for 0.2-1.2% of that of the Co binder phase. The method comprises the following steps: weighing various powder stocks, ball-milling, drying and pelletizing to form a compound; and suppressing and shaping the compound, sintering and cooling to obtain the cemented carbide. The adding mode of nano rare earth oxide or Co-RE composite powder can be implemented easily and conveniently, and the rare earth is diffusely and evenly distributed, thereby facilitating to perform physo-chemical reactions; and the cemented carbide has the advantages of low production cost, stable and enhanced performance and easy implementation, production and application.