49 results about "Trap density" patented technology

The invention relates to the technical field of semiconductors, and provides a preparation method of a charge trapping type memory with a TiN-doped Si3N4 storage layer. The preparation method comprises the following steps: S1, cleaning a substrate, and then depositing a tunneling layer on the surface of the substrate; s2, depositing m layers of Si3N4 films and p layers of TiN films on the surface of the tunneling layer, repeating the process for x times, and finally depositing n layers of Si3N4 films to obtain a TiN-doped Si3N4 storage layer; wherein 25 < = m < = 50, 25 < = n < = 50, p = 1, and 5 < = x < = 11; and S3, depositing a barrier layer on the surface of the storage layer, and then evaporating an Al electrode on the surface of the barrier layer. The storage layer Si3N4 film is doped with TiN, more charge traps are provided, the charge trap density of the storage layer is improved, compared with an undoped control group, the storage window is larger, the fatigue characteristic of the device is better, the retention performance is excellent, and the reliability of the charge trapping type memory is greatly improved.

The present invention discloses a preparation method of a perovskite thin film transistor based on a self-assembled monolayer, and relates to the technical field of perovskite. The preparation method of the present invention comprises the following steps: (1) a small molecule solution dissolved in an organic solvent is spin-coated on a silicon wafer coated with silicon dioxide, annealed at 100-120°C for 10-15min, and a multilayer small molecule film is obtained, wherein the small molecule solution is Br-2EPO or Br-2EPT; (2) an organic solvent is spin-coated on the multilayer small molecule film. The present invention introduces two self-assembled monolayers of Br-2EPO or Br-2EPT, and the phosphate group reacts with the hydroxyl group on the gate oxide surface to achieve a smaller hydroxyl density arrangement. At the same time, the perovskite is made to achieve a better lattice arrangement through halogen bonds and Lewis acid-base interactions, thereby improving the gate interface state and effectively reducing the internal trap density of the perovskite thin film transistor.

The application discloses a dielectric high-space-resolution trap imaging method and system based on a scanning probe microscope, and the method comprises the following steps: recording a sample surface topography image sequence and a surface potential image sequence after removing a voltage; correcting image offset according to the surface topography image sequence, and extracting surface potential decay data of each pixel point from the corrected surface potential image sequence; determining trap distribution information of each pixel point by fitting and calculation according to the surface potential decay data of each pixel point; and forming deep and shallow trap energy level peak value images and / or deep and shallow trap density peak value images corresponding to the film surface topography according to the trap distribution information of all pixel points and the original positions of the pixel points. The method directly images the trap characteristics of a sample at a nanometer scale, and has the advantages of high spatial resolution and intuitive comparison.

The invention relates to a method for measuring the near-interface trap density of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) channel, which belongs to the field of semiconductor device testing and comprises the following steps of: selecting a SiC MOSFET sample; performing standard alternating current capacitance measurement by using a parameter analyzer to test capacitance between the anode and the cathode and the anode; selecting a high reference frequency and a low reference frequency from the frequencies of the plurality of sine waves; the difference between the response charge density at the low reference frequency and the response charge density at the high reference frequency is calculated to determine a near-interface trap density at which the region is active above a threshold. According to the method, the density of the near-interface trap influencing the SiC MOSFET channel performance can be represented in a lossless mode, the test method is simple, data support can be provided for SiC MOSFET performance optimization, the device performance and reliability are improved, a user can be helped to compare and select devices from different manufacturers more conveniently, and the method is suitable for SiC MOSFETs of all structures.

A silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×1013 cm−3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×1017 cm−3 or less measured by a SIMS method and a Cr density of 1.0×1017 cm−3 or less measured by a SIMS method.

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

The present invention relates to a method for measuring the near-interface trap density of a SiC MOSFET channel, which belongs to the field of semiconductor device testing, and includes: selecting a SiC MOSFET sample; using a parameter analyzer to perform standard AC capacitance measurement to test the capacitance between an anode and a cathode; selecting a high reference frequency and a low reference frequency from the frequencies of multiple sine waves; calculating the difference between the response charge density at the low reference frequency and the response charge density at the high reference frequency to determine the near-interface trap density active in the region above the threshold. The present invention can non-destructively characterize the density of near-interface traps that affect the channel performance of SiC MOSFET, the test method is simple, and can provide data support for the performance optimization of SiC MOSFET, improve the device performance and reliability, and can also help users more conveniently compare and select devices from different manufacturers, and the method is applicable to SiC MOSFETs of all structures.

The present invention discloses a method for predicting spatial charge dissipation characteristics of randomly distributed trap densities at different depths, including: constructing a one-dimensional simulation model according to the actual structure of a target epoxy resin composite insulating material; constructing a spatial charge dissipation characteristics model of randomly distributed trap densities at different depths according to the constructed one-dimensional simulation model; simulating the spatial charge dissipation characteristics model of randomly distributed trap densities at different depths to obtain the spatial charge distribution of the target epoxy resin composite insulating material after decompression. The method predicts the spatial charge dissipation process of epoxy resin composite insulating materials based on the random distribution of energy of trap densities at different depths, thereby providing assistance for subsequent research on the influence of the internal electrical distribution and behavioral characteristics of epoxy composite materials after decompression on the insulating properties of epoxy composite materials.

The present invention discloses a method for detecting the trap density of a MOSFET gate oxide layer, comprising: 1) testing the threshold voltage and gate oxide layer capacitance of a MOSFET device; 2) subjecting the MOSFET to electron beam irradiation treatment, and testing the threshold voltage of the device after different irradiation doses; 3) when the device threshold voltage does not change with increasing irradiation dose, discontinuing irradiation treatment and recording the final threshold voltage; 4) calculating the change in the gate oxide layer fixed charge based on the change in the MOSFET threshold voltage before and after electron irradiation treatment; and 5) calculating the gate oxide layer trap density based on the change in the gate oxide layer fixed charge and the area of ​​the gate oxide layer. Using the present invention, the gate oxide layer trap density of a MOSFET can be quickly obtained, which is used for analyzing device performance and improving gate oxide layer processes, and has a wide range of applications.

The invention relates to the technical field of reliability evaluation of semiconductor devices, and discloses a method and a system for evaluating hot carrier degradation of an integrated circuit. Initial model parameters of a transistor are extracted, and initial model parameters of a non-degraded transistor are extracted; calculating the interface trap density delta NIT and the oxide layer trap density delta NOT through the degradation amount delta Vth of the threshold voltage and the degradation amount delta IDsat of the saturated leakage current; calculating the degradation amount of the transmission parameters of the transistors, namely calculating the degradation amount of the transmission parameters of the plurality of transistors for the interface trap density delta NIT and the oxide layer trap density delta NOT through a preset physical relational expression; and predicting the current-voltage characteristics of the transistor, substituting the degradation amount of the transmission parameters of the transistor into the compact model of the transistor, and predicting the current-voltage characteristics of the transistor after degradation. According to the method adopted by the invention, the complex I-V characteristic change can be comprehensively predicted only by measuring the degradation of the two key parameters Vth and IDsat, so that the experimental test quantity and the time cost are greatly reduced.

This invention relates to a hafnium-based ferroelectric field-effect transistor and its fabrication method. A hafnium-based ferroelectric field-effect transistor includes a silicon substrate; and a gate disposed on the silicon substrate, the gate being separated from the silicon substrate by an interface layer. A source and a drain are respectively disposed on opposite sides of the gate; wherein the interface layer is aluminum oxynitride, and the gate includes a bottom-to-top stacked HZO layer and a titanium nitride layer. This invention solves the problem of poor durability in existing ferroelectric transistors and further enhances the trap density and pyrolysis performance (Pr) by incorporating an HPA process.

A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×1011 cm−3.

The invention relates to a multi-stress polyimide charge behavior refined model establishment method and system, and relates to the technical field of material analysis, and the method comprises the steps: carrying out a bias thermally stimulated current test on a to-be-tested polyimide material to obtain trap characteristics; according to a thermally stimulated current curve and a dielectric spectrum test result, the trapped charges of different energy levels are distinguished to obtain charge peaks of different properties; fitting the trap removal current according to the trap charge trap removal peak to obtain a trap removal current fitting curve, further obtaining a trap energy level through an Arrhenius formula, and integrating the trap removal current fitting curve to obtain trap density; an electron incidence track and electron energy deposition distribution are obtained through a Monte Carlo method, and electron deposition depth distribution is calculated; and according to the trap parameters and the electron deposition depth distribution, constructing a polyimide charge behavior refined model. According to the invention, the charge behavior in the polyimide material can be accurately simulated.

Provided is a stretchable organic thin film field effect transistor (OTFT) element with high sensitivity and low power characteristic as a temperature sensor element that resolved instability caused by charge trap density induced as strain or heat in a sub-threshold region.

The invention belongs to the technical field of microelectronics and semiconductors, and provides a method for improving SiC gate oxide interface quality through step-by-step oxidation, which comprises the following steps: depositing alpha-Si on a silicon carbide epitaxial wafer to obtain an alpha-Si / SiC composite structure; and carrying out two times of dry oxygen oxidation on the alpha-Si / SiC composite structure at different temperatures, and annealing to obtain the alpha-Si / SiC composite structure. According to the method, the alpha-Si / SiC system is oxidized step by step, so that the content of carbon clusters at the SiC / SiO2 interface is reduced, and high-quality gate oxide with relatively low interface state density, low near interface trap density and low oxide layer effective fixed charge density can be obtained. And meanwhile, alpha-Si is converted into SiO2 at low temperature, so that the roughness of a gate medium is reduced, and the breakdown characteristic of gate oxide is ensured. According to the invention, the problems of high SiC / SiO2 interface trap density, poor reliability and the like in the gate oxide preparation process of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device are solved.

The invention provides a semiconductor device and a memory system, the semiconductor device comprises a first semiconductor structure, the first semiconductor structure comprises a gate stack structure and a channel structure, the channel structure is located in the gate stack structure, the channel structure comprises an electron capture layer, and the electron capture layer is located between the gate stack structure and the channel structure. The electron capture layer comprises a first electron capture material and a second electron capture material, the dielectric constant of the second electron capture material is greater than that of the first electron capture material, and the trap density of the second electron capture material is greater than that of the first electron capture material. According to the semiconductor device and the memory system provided by the invention, the second electron capture material with a larger dielectric constant and higher trap density is added into the electron capture layer, so that the partial voltage of the electron capture layer can be reduced, and the programming speed of the semiconductor device is improved.

The invention provides a semiconductor structure and a manufacturing method thereof, a memory, a storage system and electronic equipment, relates to the technical field of semiconductors, and aims to increase the trap density of a charge trapping layer in the semiconductor structure so as to enlarge a memory window of the semiconductor structure and improve the charge storage characteristic of the semiconductor structure. The semiconductor structure comprises a stacked structure and a channel structure penetrating through the stacked structure. The channel structure comprises a functional layer and a channel layer which are stacked in the radial direction of the channel structure. Wherein the functional layer comprises a charge trapping layer, and the charge trapping layer contains carbon elements. The semiconductor structure can be applied to a memory to realize data reading and writing operations.

A method for evaluating the channel interface of a polymer transistor, based on three parameters: total carrier concentration, free carrier concentration, and channel interface trap density, evaluates the quality of the channel interface of a polymer transistor by comparing it with a standard sample, helps to better analyze the device performance, provides theoretical guidance for evaluating the effects of the structure of thin-film transistors, fabrication processes, active layer and gate insulating layer materials, etc. on the electrical performance of the device, and further provides a reference for building an evaluation model for polymer transistor interface analysis in the future.

This invention discloses a triarylamine crosslinked molecule with a halostyrene side chain, its preparation method, and its applications, belonging to the field of optoelectronic materials technology. This triarylamine crosslinked molecule with a halostyrene side chain exhibits good structural symmetry and good orbital separation characteristics, effectively suppressing nonradiative recombination of electrons and holes during carrier transport, which is beneficial to improving the carrier separation and transport efficiency of the device. When applied to the fabrication of perovskite solar cells, it improves the photoelectric performance of the device. Single-electron and single-hole device tests show that after adding this crosslinked molecule, the trap filling threshold voltage is significantly reduced, the trap density decreases, and the electron mobility and hole mobility increase. This crosslinked molecule can effectively passivate perovskite defects and improve carrier transport capability, making it suitable for high-efficiency and stable perovskite solar cells.

The application provides a preparation method of a semiconductor structure, comprising the following steps: providing a substrate, forming a germanium-silicon layer on the substrate, performing at least one passivation process on the germanium-silicon layer by using a trimethylaluminum solution, and performing an annealing process on the germanium-silicon layer. The germanium-silicon layer is subjected to trimethylaluminum passivation treatment by using the trimethylaluminum solution, so that a passivation layer containing a large number of Al-O bonds is formed on the surface of the germanium-silicon layer, germanium condensation is formed at the junction of the passivation layer and the germanium-silicon layer, the condensed germanium ions are uniformly diffused into the germanium-silicon layer through the annealing process, the germanium ion concentration in the germanium-silicon layer is improved, a well-shaped germanium-silicon crystal structure is formed by means of the energy provided in the annealing process, and the germanium-silicon layer with low interface trap density and large carrier mobility is provided, so that the performance of the semiconductor device is improved.

The invention discloses a preparation method of a perovskite thin film transistor based on a self-assembled monomolecular layer, and relates to the technical field of perovskite. The preparation method comprises the following steps: (1) spin-coating a silicon wafer plated with silicon dioxide with a micromolecular solution dissolved in an organic solvent, and annealing at 100-120 DEG C for 10-15 min to obtain a multi-layer micromolecular film, the micromolecular solution being Br-2EPO or Br-2EPT; and (2) spin-coating an organic solvent on the multi-layer micromolecular film. According to the invention, two self-assembled monolayers Br-2EPO or Br-2EPT are introduced, and a phosphate group reacts with hydroxyl on the surface of a gate oxide to realize smaller hydroxyl density arrangement. And meanwhile, through the interaction of halogen bonds and Lewis acid-base, better lattice arrangement of perovskite is realized, the gate interface state is improved, and the internal trap density of the perovskite thin film transistor is effectively reduced.

A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×1011 cm−3.

The invention relates to a preparation method of a high-temperature-resistant and radiation-resistant polypropylene-based cable insulating material, which comprises the following steps: by taking a styrene thermoplastic elastomer and polypropylene as base materials, using a free radical initiator and taking an aromatic compound with a conjugated structure as an assistant cross-linking agent, carrying out dynamic cross-linking reaction through a torque rheometer to obtain the high-temperature-resistant and radiation-resistant polypropylene-based cable insulating material. The cable insulating material with high breakdown field strength and deep trap density is developed, and the cable insulating material has higher radiation resistance and can be used as a nuclear power cable insulating material.

The present invention relates to the field of semiconductor technology and proposes a method for preparing a charge-trapping memory (CTM) with a TiN-doped Si3N4 storage layer. The method comprises the following steps: S1, cleaning the substrate, and then depositing a tunneling layer on the substrate surface; S2, depositing m layers of Si3N4 film and p layers of TiN film on the tunneling layer surface, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer, wherein 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11; S3, depositing a barrier layer on the storage layer surface, and then evaporating an Al electrode on the barrier layer surface. By doping the Si3N4 storage layer with TiN, the present invention provides more charge traps and increases the charge trap density of the storage layer. Compared with an undoped control group, the CTM exhibits a larger storage window, better device fatigue characteristics, and excellent retention performance, greatly improving the reliability of the CTM.

Provided are a polymer thin-film transistor and a method of fabricating the same. Donor-acceptor copolymer-based field-effect transistors (FETs) have attracted considerable attention from technological and academic perspectives due to their low band gap, high mobility, low cost, easy solution processability, flexibility, and stretchability. Large-area films can be formed through meniscus-guided coating among various solution-processing techniques. 29-Diketopyrrolopyrrole-selenophene vinylene selenophene (29-DPP-SVS) donor-acceptor copolymer-based FETs have already shown excellent performance due to their short π-π stacking distance and strong π-π interaction. Charge carrier mobility of these types of semiconductor materials significantly depends on an applied electric field. Accordingly, detailed analysis of the electric-field dependency of charge carrier mobility is necessary to understand the transport mechanism within the material. Therefore, 29-DPP-S VS-based FETs are fabricated by varying the blade coating (BC) speed of a semiconductor layer. The effect of the BC speed on the electrical characteristics of the FETs is studied through the analysis of electric-field-dependent mobility. The results show that the charge carrier mobility of different FETs depends on the applied electric field and that the type of dependency is Poole-Frenkel. At an optimized BC speed (2 mm s−1), the device shows maximum zero-field mobility (3.39 cm2V−1s−1) due to the low trap density within the conductive channel.

The invention provides a perovskite precursor solution and a method for preparing a perovskite layer by using the perovskite precursor solution. The perovskite precursor solution comprises a perovskite precursor, an additive and a solvent, wherein the additive has the following structure: # imgabs0 # R1 is selected from C1-4 alkyl groups; and R2 is selected from hydrogen or C1-4 alkyl groups. The additive contained in the perovskite precursor solution can effectively improve the quality of a perovskite film, induce phase crystallization and passivate a trap state, and can be combined with uncoordinated Pb < 2 + > to reduce the trap density and improve the photoelectric property, repeatability and stability of the solar cell.

The invention discloses a method for calculating space charge distribution of a cable factory joint at different temperatures, which comprises the following steps of: 1, cutting a sample of the cable factory joint to obtain an insulation sample, and measuring the average thickness; 2, measuring conductance current at different temperatures, calculating the carrier mobility, and fitting the temperature and the carrier mobility of the insulation sample; 3, testing a positive-voltage and negative-voltage charging isothermal surface potential attenuation curve to obtain electron trap energy levels, electron trap densities, hole trap energy levels and hole trap densities at different temperatures; 4, setting boundary conditions, and establishing a bipolar carrier model; and 5, substituting the carrier mobility, the electron trap energy level, the electron trap density, the hole trap energy level and the hole trap density into the bipolar carrier model to obtain space charge distribution. According to the method, the space charge distribution in the cable factory joint can be quickly and accurately calculated, and the fault risk caused by unreasonable space charge distribution is reduced.

The present invention discloses a method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage changes, and relates to the field of trap testing and reliability assessment of power semiconductor devices. The method comprises: connecting the device under test to a transient threshold voltage test circuit; applying a negative gate voltage to the device during the trap filling process; applying a test current to the source and drain sections of the device during the trap test process to obtain the source-drain voltage change, which is the threshold voltage change; and simultaneously utilizing a structure function to process the threshold voltage change caused by each trap, and calculating the trap density of each trap. The present invention implements transient threshold voltage testing and trap density calculation of heterogeneous semiconductor devices through circuit design. The method can be applied to trap density testing of heterogeneous semiconductor devices from different sources and has good universality.

The present application provides a surface trap distribution test method and device based on light excitation, which belongs to the technical field of dielectric property testing of solid medium materials. The method sends a preset excitation energy parameter to the electron gun device so that the electron gun device emits corresponding trapped charges to the sample to be tested within a first time period. The sample to be tested is a solid medium that is relatively arranged at the emission end of the electron gun device and the collection end of the surface potentiometer through an active connection device. When the trapped charge is injected into the sample to be tested, a light source excitation instruction is generated to enable the light source excitation device to emit preset wavelength photon streams to the sample to be tested in sequence through the light source excitation instruction. The surface potential sequence corresponding to the trapped charge is determined by the relatively arranged surface potentiometer. Based on the excitation energy parameter, the surface potential sequence, the preset trap energy level formula and the preset trap density distribution formula, the corresponding surface trap energy level value and surface trap density distribution value of the sample to be tested are determined.

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.