15 results about "Trap density" patented technology

The application discloses a dielectric high-space-resolution trap imaging method and system based on a scanning probe microscope, and the method comprises the following steps: recording a sample surface topography image sequence and a surface potential image sequence after removing a voltage; correcting image offset according to the surface topography image sequence, and extracting surface potential decay data of each pixel point from the corrected surface potential image sequence; determining trap distribution information of each pixel point by fitting and calculation according to the surface potential decay data of each pixel point; and forming deep and shallow trap energy level peak value images and / or deep and shallow trap density peak value images corresponding to the film surface topography according to the trap distribution information of all pixel points and the original positions of the pixel points. The method directly images the trap characteristics of a sample at a nanometer scale, and has the advantages of high spatial resolution and intuitive comparison.

A silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×1013 cm−3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×1017 cm−3 or less measured by a SIMS method and a Cr density of 1.0×1017 cm−3 or less measured by a SIMS method.

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

The invention relates to the technical field of reliability evaluation of semiconductor devices, and discloses a method and a system for evaluating hot carrier degradation of an integrated circuit. Initial model parameters of a transistor are extracted, and initial model parameters of a non-degraded transistor are extracted; calculating the interface trap density delta NIT and the oxide layer trap density delta NOT through the degradation amount delta Vth of the threshold voltage and the degradation amount delta IDsat of the saturated leakage current; calculating the degradation amount of the transmission parameters of the transistors, namely calculating the degradation amount of the transmission parameters of the plurality of transistors for the interface trap density delta NIT and the oxide layer trap density delta NOT through a preset physical relational expression; and predicting the current-voltage characteristics of the transistor, substituting the degradation amount of the transmission parameters of the transistor into the compact model of the transistor, and predicting the current-voltage characteristics of the transistor after degradation. According to the method adopted by the invention, the complex I-V characteristic change can be comprehensively predicted only by measuring the degradation of the two key parameters Vth and IDsat, so that the experimental test quantity and the time cost are greatly reduced.

This invention discloses a triarylamine crosslinked molecule with a halostyrene side chain, its preparation method, and its applications, belonging to the field of optoelectronic materials technology. This triarylamine crosslinked molecule with a halostyrene side chain exhibits good structural symmetry and good orbital separation characteristics, effectively suppressing nonradiative recombination of electrons and holes during carrier transport, which is beneficial to improving the carrier separation and transport efficiency of the device. When applied to the fabrication of perovskite solar cells, it improves the photoelectric performance of the device. Single-electron and single-hole device tests show that after adding this crosslinked molecule, the trap filling threshold voltage is significantly reduced, the trap density decreases, and the electron mobility and hole mobility increase. This crosslinked molecule can effectively passivate perovskite defects and improve carrier transport capability, making it suitable for high-efficiency and stable perovskite solar cells.

The application provides a preparation method of a semiconductor structure, comprising the following steps: providing a substrate, forming a germanium-silicon layer on the substrate, performing at least one passivation process on the germanium-silicon layer by using a trimethylaluminum solution, and performing an annealing process on the germanium-silicon layer. The germanium-silicon layer is subjected to trimethylaluminum passivation treatment by using the trimethylaluminum solution, so that a passivation layer containing a large number of Al-O bonds is formed on the surface of the germanium-silicon layer, germanium condensation is formed at the junction of the passivation layer and the germanium-silicon layer, the condensed germanium ions are uniformly diffused into the germanium-silicon layer through the annealing process, the germanium ion concentration in the germanium-silicon layer is improved, a well-shaped germanium-silicon crystal structure is formed by means of the energy provided in the annealing process, and the germanium-silicon layer with low interface trap density and large carrier mobility is provided, so that the performance of the semiconductor device is improved.

Provided are a polymer thin-film transistor and a method of fabricating the same. Donor-acceptor copolymer-based field-effect transistors (FETs) have attracted considerable attention from technological and academic perspectives due to their low band gap, high mobility, low cost, easy solution processability, flexibility, and stretchability. Large-area films can be formed through meniscus-guided coating among various solution-processing techniques. 29-Diketopyrrolopyrrole-selenophene vinylene selenophene (29-DPP-SVS) donor-acceptor copolymer-based FETs have already shown excellent performance due to their short π-π stacking distance and strong π-π interaction. Charge carrier mobility of these types of semiconductor materials significantly depends on an applied electric field. Accordingly, detailed analysis of the electric-field dependency of charge carrier mobility is necessary to understand the transport mechanism within the material. Therefore, 29-DPP-S VS-based FETs are fabricated by varying the blade coating (BC) speed of a semiconductor layer. The effect of the BC speed on the electrical characteristics of the FETs is studied through the analysis of electric-field-dependent mobility. The results show that the charge carrier mobility of different FETs depends on the applied electric field and that the type of dependency is Poole-Frenkel. At an optimized BC speed (2 mm s−1), the device shows maximum zero-field mobility (3.39 cm2V−1s−1) due to the low trap density within the conductive channel.

A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

The invention discloses a space charge dissipation method and device for a solid insulator in a combined electric appliance. The method comprises the following steps: for different types of solid insulators such as an insulating pull rod, a basin-type insulator, a supporting insulator and the like, measuring surface potential attenuation data of the insulators after corona charging at the same temperature in combination with atom types, contents and chemical bond proportions of the insulators, quantitatively calculating trap levels and trap densities of the insulators, and calculating the trap density of the insulators. The method comprises the following steps: measuring the actual size of a combined electric appliance insulator, calculating the number of deep trap charges, regulating and controlling the focus of an X-ray generation device, the type of a filter and the rotating speed of an anode, accurately positioning the insulator needing X-ray irradiation, and regulating and controlling the tube voltage, tube current and exposure time of the X-ray generation device by combining the trap level and trap density of the insulator. Therefore, the space charges of the insulator can be quickly, safely and effectively dissipated.

The invention discloses a method for achieving high stability and high performance of a low-crystallinity polymer n-type organic thin film transistor through contact engineering. The method comprises the steps that S1, low-crystallinity and high-crystallinity polymers are used for preparing a device, variables are set, an Al / Ti electrode is adopted, and an Au electrode is optionally used as a reference; s2, measuring transmission Id-Vg and output Id-Vd characteristics; s3, processing the collected I-V data to calculate key parameters; s4, comparing Id-Vg, Id-Vd and derivative parameter evolution of the low-crystallinity polymer and the high-crystallinity polymer under the Al / Ti electrode item by item, including an optimal performance window, and comparing with a reference Au electrode device; and S5, generating a comparison report and a conclusion, and attaching an annotation graph. The method can improve the overall performance of the device, such as mobility, on-state current, contact resistance, trap density and the like.

The invention provides a growth method of a metal halide single crystal film, which comprises the following steps of: firstly, depositing a layer of blended polymer film with an orthogonal dissolution characteristic on the surface of a metal halide single crystal substrate as a sacrificial layer, and performing solvent treatment to form a self-patterning soft template; and then coating the polymer layer with a precursor solution of a target epitaxy, carrying out nucleation, transverse growth and grain combination to form a uniform and compact single crystal thin film, and completing mechanical stripping and transfer of the epitaxial thin film through a thermal stripping adhesive tape. The growth method provided by the invention has excellent universality, can grow various metal halide single crystal films including lead-based, non-lead-based, alloy and superlattice structures, and has wide adjustability in size and thickness; in addition, the prepared thin film shows high carrier mobility and low trap density which are equivalent to those of blocky single crystals.

This invention provides a high-voltage radiation-hardened GaN device with a stepped heterojunction buffer layer, belonging to the field of microelectronics technology. The device, from bottom to top, comprises a buffer layer, a barrier layer, a p-AlGaN layer, and source, gate, and drain electrode structures. A portion of the GaN buffer layer near the source is replaced with a low-Al content AlGaN material, thus forming a heterojunction stepped structure within the buffer layer. This structure alleviates lattice mismatch and reduces trap density by embedding a low-aluminum AlGaN layer. Simultaneously, it utilizes a novel interface polarization effect to induce two-dimensional hole gas, dynamically neutralizing excess electrons during irradiation to suppress avalanche multiplication. Combined with the stepped structure, it optimizes the potential distribution, expands the depletion region, and weakens the peak electric field, thereby simultaneously improving the device's voltage withstand and radiation resistance characteristics. This provides a new path with significant industrialization potential for high-reliability, low-cost GaN power devices in extreme environments such as aerospace.

The invention provides a SiC MOSFET device gate dielectric structure manufacturing method and a SiC MOSFET device, and the method comprises the steps: generating a first dielectric layer on the surface of a SiC substrate, and placing the SiC substrate on which the first dielectric layer is generated in a nitrogen-containing atmosphere for interface nitriding treatment; carrying out high-temperature annealing treatment on the SiC substrate after the interface nitriding treatment; forming a second dielectric layer on the surface, far away from the SiC substrate, of the first dielectric layer by adopting a preset deposition method; wherein the dielectric constant parameter value of the second dielectric layer is higher than a preset parameter value; performing thermal annealing treatment on the first dielectric layer and the second dielectric layer, wherein the first dielectric layer and the second dielectric layer after annealing jointly form a gate dielectric structure; wherein the duration of the thermal annealing treatment is shorter than the preset duration. The method can effectively avoid the problems of poor reliability of the gate dielectric structure, high interface trap density, insufficient gate breakdown voltage and the like, and significantly improves the service life and reliability of the device.

This Schottky barrier junction type high electron mobility transistor includes: a compound semiconductor layer having a barrier layer; an insulator disposed on the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction. A trap density of carriers captured at an interface between the carrier capture region and the compound semiconductor layer is higher than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator.

The invention provides a method and chip for improving the trap density of a 4H-SiC interface, and the method comprises the steps: providing a 4H-SiC substrate, preparing a thermal oxidation layer on the 4H-SiC substrate, and forming a 4H-SiC sample; carrying out first-stage annealing in a preset pressure environment, and forming an initial nitride layer on the interface of the 4H-SiC sample by using NO2; and carrying out second-stage annealing under the preset pressure environment, and passivating an interface trap of the 4H-SiC sample by using pulse type NO gas under the assistance of ultraviolet irradiation. According to the invention, the trap density of the SiO2 / 4H-SiC interface can be reduced.