30 results about "Trap density" patented technology

The present invention discloses a preparation method of a perovskite thin film transistor based on a self-assembled monolayer, and relates to the technical field of perovskite. The preparation method of the present invention comprises the following steps: (1) a small molecule solution dissolved in an organic solvent is spin-coated on a silicon wafer coated with silicon dioxide, annealed at 100-120°C for 10-15min, and a multilayer small molecule film is obtained, wherein the small molecule solution is Br-2EPO or Br-2EPT; (2) an organic solvent is spin-coated on the multilayer small molecule film. The present invention introduces two self-assembled monolayers of Br-2EPO or Br-2EPT, and the phosphate group reacts with the hydroxyl group on the gate oxide surface to achieve a smaller hydroxyl density arrangement. At the same time, the perovskite is made to achieve a better lattice arrangement through halogen bonds and Lewis acid-base interactions, thereby improving the gate interface state and effectively reducing the internal trap density of the perovskite thin film transistor.

The application discloses a dielectric high-space-resolution trap imaging method and system based on a scanning probe microscope, and the method comprises the following steps: recording a sample surface topography image sequence and a surface potential image sequence after removing a voltage; correcting image offset according to the surface topography image sequence, and extracting surface potential decay data of each pixel point from the corrected surface potential image sequence; determining trap distribution information of each pixel point by fitting and calculation according to the surface potential decay data of each pixel point; and forming deep and shallow trap energy level peak value images and / or deep and shallow trap density peak value images corresponding to the film surface topography according to the trap distribution information of all pixel points and the original positions of the pixel points. The method directly images the trap characteristics of a sample at a nanometer scale, and has the advantages of high spatial resolution and intuitive comparison.

A silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×1013 cm−3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×1017 cm−3 or less measured by a SIMS method and a Cr density of 1.0×1017 cm−3 or less measured by a SIMS method.

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

The present invention discloses a method for detecting the trap density of a MOSFET gate oxide layer, comprising: 1) testing the threshold voltage and gate oxide layer capacitance of a MOSFET device; 2) subjecting the MOSFET to electron beam irradiation treatment, and testing the threshold voltage of the device after different irradiation doses; 3) when the device threshold voltage does not change with increasing irradiation dose, discontinuing irradiation treatment and recording the final threshold voltage; 4) calculating the change in the gate oxide layer fixed charge based on the change in the MOSFET threshold voltage before and after electron irradiation treatment; and 5) calculating the gate oxide layer trap density based on the change in the gate oxide layer fixed charge and the area of ​​the gate oxide layer. Using the present invention, the gate oxide layer trap density of a MOSFET can be quickly obtained, which is used for analyzing device performance and improving gate oxide layer processes, and has a wide range of applications.

The invention relates to the technical field of reliability evaluation of semiconductor devices, and discloses a method and a system for evaluating hot carrier degradation of an integrated circuit. Initial model parameters of a transistor are extracted, and initial model parameters of a non-degraded transistor are extracted; calculating the interface trap density delta NIT and the oxide layer trap density delta NOT through the degradation amount delta Vth of the threshold voltage and the degradation amount delta IDsat of the saturated leakage current; calculating the degradation amount of the transmission parameters of the transistors, namely calculating the degradation amount of the transmission parameters of the plurality of transistors for the interface trap density delta NIT and the oxide layer trap density delta NOT through a preset physical relational expression; and predicting the current-voltage characteristics of the transistor, substituting the degradation amount of the transmission parameters of the transistor into the compact model of the transistor, and predicting the current-voltage characteristics of the transistor after degradation. According to the method adopted by the invention, the complex I-V characteristic change can be comprehensively predicted only by measuring the degradation of the two key parameters Vth and IDsat, so that the experimental test quantity and the time cost are greatly reduced.

This invention relates to a hafnium-based ferroelectric field-effect transistor and its fabrication method. A hafnium-based ferroelectric field-effect transistor includes a silicon substrate; and a gate disposed on the silicon substrate, the gate being separated from the silicon substrate by an interface layer. A source and a drain are respectively disposed on opposite sides of the gate; wherein the interface layer is aluminum oxynitride, and the gate includes a bottom-to-top stacked HZO layer and a titanium nitride layer. This invention solves the problem of poor durability in existing ferroelectric transistors and further enhances the trap density and pyrolysis performance (Pr) by incorporating an HPA process.

A method for evaluating the channel interface of a polymer transistor, based on three parameters: total carrier concentration, free carrier concentration, and channel interface trap density, evaluates the quality of the channel interface of a polymer transistor by comparing it with a standard sample, helps to better analyze the device performance, provides theoretical guidance for evaluating the effects of the structure of thin-film transistors, fabrication processes, active layer and gate insulating layer materials, etc. on the electrical performance of the device, and further provides a reference for building an evaluation model for polymer transistor interface analysis in the future.

This invention discloses a triarylamine crosslinked molecule with a halostyrene side chain, its preparation method, and its applications, belonging to the field of optoelectronic materials technology. This triarylamine crosslinked molecule with a halostyrene side chain exhibits good structural symmetry and good orbital separation characteristics, effectively suppressing nonradiative recombination of electrons and holes during carrier transport, which is beneficial to improving the carrier separation and transport efficiency of the device. When applied to the fabrication of perovskite solar cells, it improves the photoelectric performance of the device. Single-electron and single-hole device tests show that after adding this crosslinked molecule, the trap filling threshold voltage is significantly reduced, the trap density decreases, and the electron mobility and hole mobility increase. This crosslinked molecule can effectively passivate perovskite defects and improve carrier transport capability, making it suitable for high-efficiency and stable perovskite solar cells.

The application provides a preparation method of a semiconductor structure, comprising the following steps: providing a substrate, forming a germanium-silicon layer on the substrate, performing at least one passivation process on the germanium-silicon layer by using a trimethylaluminum solution, and performing an annealing process on the germanium-silicon layer. The germanium-silicon layer is subjected to trimethylaluminum passivation treatment by using the trimethylaluminum solution, so that a passivation layer containing a large number of Al-O bonds is formed on the surface of the germanium-silicon layer, germanium condensation is formed at the junction of the passivation layer and the germanium-silicon layer, the condensed germanium ions are uniformly diffused into the germanium-silicon layer through the annealing process, the germanium ion concentration in the germanium-silicon layer is improved, a well-shaped germanium-silicon crystal structure is formed by means of the energy provided in the annealing process, and the germanium-silicon layer with low interface trap density and large carrier mobility is provided, so that the performance of the semiconductor device is improved.

The present invention relates to the field of semiconductor technology and proposes a method for preparing a charge-trapping memory (CTM) with a TiN-doped Si3N4 storage layer. The method comprises the following steps: S1, cleaning the substrate, and then depositing a tunneling layer on the substrate surface; S2, depositing m layers of Si3N4 film and p layers of TiN film on the tunneling layer surface, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer, wherein 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11; S3, depositing a barrier layer on the storage layer surface, and then evaporating an Al electrode on the barrier layer surface. By doping the Si3N4 storage layer with TiN, the present invention provides more charge traps and increases the charge trap density of the storage layer. Compared with an undoped control group, the CTM exhibits a larger storage window, better device fatigue characteristics, and excellent retention performance, greatly improving the reliability of the CTM.

Provided are a polymer thin-film transistor and a method of fabricating the same. Donor-acceptor copolymer-based field-effect transistors (FETs) have attracted considerable attention from technological and academic perspectives due to their low band gap, high mobility, low cost, easy solution processability, flexibility, and stretchability. Large-area films can be formed through meniscus-guided coating among various solution-processing techniques. 29-Diketopyrrolopyrrole-selenophene vinylene selenophene (29-DPP-SVS) donor-acceptor copolymer-based FETs have already shown excellent performance due to their short π-π stacking distance and strong π-π interaction. Charge carrier mobility of these types of semiconductor materials significantly depends on an applied electric field. Accordingly, detailed analysis of the electric-field dependency of charge carrier mobility is necessary to understand the transport mechanism within the material. Therefore, 29-DPP-S VS-based FETs are fabricated by varying the blade coating (BC) speed of a semiconductor layer. The effect of the BC speed on the electrical characteristics of the FETs is studied through the analysis of electric-field-dependent mobility. The results show that the charge carrier mobility of different FETs depends on the applied electric field and that the type of dependency is Poole-Frenkel. At an optimized BC speed (2 mm s−1), the device shows maximum zero-field mobility (3.39 cm2V−1s−1) due to the low trap density within the conductive channel.

The present invention discloses a method for testing the trap density of heterogeneous semiconductor devices based on threshold voltage changes, and relates to the field of trap testing and reliability assessment of power semiconductor devices. The method comprises: connecting the device under test to a transient threshold voltage test circuit; applying a negative gate voltage to the device during the trap filling process; applying a test current to the source and drain sections of the device during the trap test process to obtain the source-drain voltage change, which is the threshold voltage change; and simultaneously utilizing a structure function to process the threshold voltage change caused by each trap, and calculating the trap density of each trap. The present invention implements transient threshold voltage testing and trap density calculation of heterogeneous semiconductor devices through circuit design. The method can be applied to trap density testing of heterogeneous semiconductor devices from different sources and has good universality.

The present application provides a surface trap distribution test method and device based on light excitation, which belongs to the technical field of dielectric property testing of solid medium materials. The method sends a preset excitation energy parameter to the electron gun device so that the electron gun device emits corresponding trapped charges to the sample to be tested within a first time period. The sample to be tested is a solid medium that is relatively arranged at the emission end of the electron gun device and the collection end of the surface potentiometer through an active connection device. When the trapped charge is injected into the sample to be tested, a light source excitation instruction is generated to enable the light source excitation device to emit preset wavelength photon streams to the sample to be tested in sequence through the light source excitation instruction. The surface potential sequence corresponding to the trapped charge is determined by the relatively arranged surface potentiometer. Based on the excitation energy parameter, the surface potential sequence, the preset trap energy level formula and the preset trap density distribution formula, the corresponding surface trap energy level value and surface trap density distribution value of the sample to be tested are determined.

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

The invention discloses a space charge dissipation method and device for a solid insulator in a combined electric appliance. The method comprises the following steps: for different types of solid insulators such as an insulating pull rod, a basin-type insulator, a supporting insulator and the like, measuring surface potential attenuation data of the insulators after corona charging at the same temperature in combination with atom types, contents and chemical bond proportions of the insulators, quantitatively calculating trap levels and trap densities of the insulators, and calculating the trap density of the insulators. The method comprises the following steps: measuring the actual size of a combined electric appliance insulator, calculating the number of deep trap charges, regulating and controlling the focus of an X-ray generation device, the type of a filter and the rotating speed of an anode, accurately positioning the insulator needing X-ray irradiation, and regulating and controlling the tube voltage, tube current and exposure time of the X-ray generation device by combining the trap level and trap density of the insulator. Therefore, the space charges of the insulator can be quickly, safely and effectively dissipated.

The invention discloses a method for achieving high stability and high performance of a low-crystallinity polymer n-type organic thin film transistor through contact engineering. The method comprises the steps that S1, low-crystallinity and high-crystallinity polymers are used for preparing a device, variables are set, an Al / Ti electrode is adopted, and an Au electrode is optionally used as a reference; s2, measuring transmission Id-Vg and output Id-Vd characteristics; s3, processing the collected I-V data to calculate key parameters; s4, comparing Id-Vg, Id-Vd and derivative parameter evolution of the low-crystallinity polymer and the high-crystallinity polymer under the Al / Ti electrode item by item, including an optimal performance window, and comparing with a reference Au electrode device; and S5, generating a comparison report and a conclusion, and attaching an annotation graph. The method can improve the overall performance of the device, such as mobility, on-state current, contact resistance, trap density and the like.

The invention provides a growth method of a metal halide single crystal film, which comprises the following steps of: firstly, depositing a layer of blended polymer film with an orthogonal dissolution characteristic on the surface of a metal halide single crystal substrate as a sacrificial layer, and performing solvent treatment to form a self-patterning soft template; and then coating the polymer layer with a precursor solution of a target epitaxy, carrying out nucleation, transverse growth and grain combination to form a uniform and compact single crystal thin film, and completing mechanical stripping and transfer of the epitaxial thin film through a thermal stripping adhesive tape. The growth method provided by the invention has excellent universality, can grow various metal halide single crystal films including lead-based, non-lead-based, alloy and superlattice structures, and has wide adjustability in size and thickness; in addition, the prepared thin film shows high carrier mobility and low trap density which are equivalent to those of blocky single crystals.

The present invention addresses the problem of providing a crystal film and a multilayer crystal film, which contribute to improvement of the electric characteristics of a semiconductor. Disclosed is a crystal film which contains a crystalline oxide and one or more group 14 elements of the periodic table as a dopant, wherein the trap density at 0.2-0.8 eV from the lower end of a conduction band of a semiconductor layer of the oxide is 1 × 1014 / cm3 or less.

This invention provides a high-voltage radiation-hardened GaN device with a stepped heterojunction buffer layer, belonging to the field of microelectronics technology. The device, from bottom to top, comprises a buffer layer, a barrier layer, a p-AlGaN layer, and source, gate, and drain electrode structures. A portion of the GaN buffer layer near the source is replaced with a low-Al content AlGaN material, thus forming a heterojunction stepped structure within the buffer layer. This structure alleviates lattice mismatch and reduces trap density by embedding a low-aluminum AlGaN layer. Simultaneously, it utilizes a novel interface polarization effect to induce two-dimensional hole gas, dynamically neutralizing excess electrons during irradiation to suppress avalanche multiplication. Combined with the stepped structure, it optimizes the potential distribution, expands the depletion region, and weakens the peak electric field, thereby simultaneously improving the device's voltage withstand and radiation resistance characteristics. This provides a new path with significant industrialization potential for high-reliability, low-cost GaN power devices in extreme environments such as aerospace.

The invention provides a SiC MOSFET device gate dielectric structure manufacturing method and a SiC MOSFET device, and the method comprises the steps: generating a first dielectric layer on the surface of a SiC substrate, and placing the SiC substrate on which the first dielectric layer is generated in a nitrogen-containing atmosphere for interface nitriding treatment; carrying out high-temperature annealing treatment on the SiC substrate after the interface nitriding treatment; forming a second dielectric layer on the surface, far away from the SiC substrate, of the first dielectric layer by adopting a preset deposition method; wherein the dielectric constant parameter value of the second dielectric layer is higher than a preset parameter value; performing thermal annealing treatment on the first dielectric layer and the second dielectric layer, wherein the first dielectric layer and the second dielectric layer after annealing jointly form a gate dielectric structure; wherein the duration of the thermal annealing treatment is shorter than the preset duration. The method can effectively avoid the problems of poor reliability of the gate dielectric structure, high interface trap density, insufficient gate breakdown voltage and the like, and significantly improves the service life and reliability of the device.

The embodiment of the present application provides a micro-light emitting diode device, a manufacturing method and a display device. Among them, the micro-light emitting diode device includes a backplane; a plurality of micro-light emitting diodes, wherein the plurality of micro-light emitting diode arrays are arranged on the backplane, and each of the micro-light emitting diodes includes a bottom wall close to the backplane, a top wall away from the backplane, and a side wall connecting the bottom wall and the top wall; a protective layer, wherein the protective layer is arranged on a portion of the sidewalls of each micro-light emitting diode to reduce the sidewall leakage current, and the protective layer is formed by in-situ polymerization of an in-situ cross-linkable lipoic acid gel layer. The embodiment of the present application uses the second layer of spatial force of the in-situ cross-linkable lipoic acid gel layer, under the action of coordination bonds, to achieve a lower interface trap density between the protective layer and GaN, thereby solving the problem of leakage current at the edge of the micro-light emitting diode device.

A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

The application discloses a kind of calculation methods of space charge distribution of cable factory joint at different temperatures, comprising the following steps: step one: cutting sample of cable factory joint insulation sample, and measuring average thickness;Step two: measuring conductance current at different temperatures, calculating carrier mobility, and fitting temperature and insulation sample carrier mobility;Step three: test positive pressure and negative pressure charging isothermal surface potential decay curve, obtain electron trap energy level, electron trap density, hole trap energy level and hole trap density at different temperatures;Step four: set boundary condition, establish bipolar carrier model;Step five: carrier mobility, electron trap energy level, electron trap density, hole trap energy level and hole trap density are substituted into bipolar carrier model, and space charge distribution is obtained.The application can quickly and accurately calculate the space charge distribution in the interior of cable factory joint, reduce the risk of failure caused by unreasonable space charge distribution.

The invention provides an organic short-wave infrared image sensor. The organic short-wave infrared image sensor comprises a substrate and an organic photodiode arranged on an electrode layer of the substrate, the substrate comprises a TFT (thin film transistor) substrate or a CMOS (complementary metal oxide semiconductor) substrate; the organic photodiode comprises an upright device structure taking ITO or conductive metal as an anode, or an inverted device structure taking ITO or conductive metal as a cathode. According to the invention, high device performance is realized through an active layer material with low trap density, an interface layer material with high charge blocking capability and a high-quality film forming technology. According to the imaging array, the responsivity exceeding 0.3 AW <-1 >, the dark current lower than 10 <-9 > A <-2 > and the wide linear dynamic range exceeding 130 dB can be obtained, the blind pixel rate is smaller than 1%, and the effect of clear imaging under the weak light of 10 [mu] w cm <-2 > can be achieved.

This Schottky barrier junction type high electron mobility transistor includes: a compound semiconductor layer having a barrier layer; an insulator disposed on the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction. A trap density of carriers captured at an interface between the carrier capture region and the compound semiconductor layer is higher than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator.

The invention provides a method and chip for improving the trap density of a 4H-SiC interface, and the method comprises the steps: providing a 4H-SiC substrate, preparing a thermal oxidation layer on the 4H-SiC substrate, and forming a 4H-SiC sample; carrying out first-stage annealing in a preset pressure environment, and forming an initial nitride layer on the interface of the 4H-SiC sample by using NO2; and carrying out second-stage annealing under the preset pressure environment, and passivating an interface trap of the 4H-SiC sample by using pulse type NO gas under the assistance of ultraviolet irradiation. According to the invention, the trap density of the SiO2 / 4H-SiC interface can be reduced.

The invention discloses a GaN HEMT trap density characterization method based on drain-source resistance change, and relates to the field of power semiconductor device trap test and reliability evaluation. Comprising the following steps: connecting a tested GaN HEMT with a test circuit; transient response of drain-source resistance of the device is monitored under a constant bias condition; separating the contribution of each trap level to the resistance change by using a Bayesian iterative algorithm; and obtaining the trap density of each energy level through calculation from the drain-source resistance change caused by each trap. According to the method, accurate calculation of the trap density of the GaN HEMT is achieved through drain-source resistance dynamic response analysis, the method can directly reflect the influence of traps on the dynamic conduction characteristics of the device, can be widely applied to reliability evaluation of GaN HEMT devices of different technologies, and has the advantages of being easy and convenient to test, high in resolution ratio and high in applicability.

Electrical components: - a carrier substrate (1) with a top side (10), - a trap-rich layer (2) on the top (10), - a dielectric layer (3) on the trap-rich layer (2), - an electroacoustic resonator (4) on the dielectric layer (3), - a coil (5), wherein - the dielectric layer (3) and the trap-rich layer (2) are located between the coil (5) and the carrier substrate (1), - the carrier substrate (1) is based on a semiconductor material, - the trap-rich layer (2) has a higher charge carrier trap density than the carrier substrate (1), wherein the charge carrier trap density in the trap-rich layer (2) is at least ten times the charge carrier trap density in the carrier substrate (1).