1545 results about "Conduction band" patented technology

A thin film transistor, which is capable of improving carrier mobility, and a display device and an electronic device, each of which uses the thin film transistor, are provided. The thin film transistor includes: a gate electrode; an oxide semiconductor layer including a multilayer film including a carrier travel layer configuring a channel and a carrier supply layer for supplying carriers to the carrier travel layer; a gate insulating film provided between the gate electrode and the oxide semiconductor layer; and a pair of electrodes as a source and a drain. A conduction band minimum level or a valence band maximum level corresponding to a carrier supply source of the carrier supply layer is higher in energy than a conduction band minimum level or a valence band maximum level corresponding to a carrier supply destination of the carrier travel layer.

A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO₂ gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

The present invention is generally directed to nanocomposite thermoelectric materials that exhibit enhanced thermoelectric properties. The nanocomposite materials include two or more components, with at least one of the components forming nano-sized structures within the composite material. The components are chosen such that thermal conductivity of the composite is decreased without substantially diminishing the composite's electrical conductivity. Suitable component materials exhibit similar electronic band structures. For example, a band-edge gap between at least one of a conduction band or a valence band of one component material and a corresponding band of the other component material at interfaces between the components can be less than about 5 k_BT, wherein k_B is the Boltzman constant and T is an average temperature of said nanocomposite composition.

A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO₂ gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

The invention discloses a process for preparing a high efficiency nanometer Tio2 visible light catalyst codoped with metal and non metallic ion, belonging to the photocatalysis technology field. The invention adopts titanic acid ester as precursor, uses metal salt and non-metallic compound as dopant, in accordance with sol-gel method, prepares the nanometer TiO2-based photocatalyst with codoping, high efficiency and visible light catalytic activity, wherein the catalytic activity is greatly higher than that of single-doped TiO2-based catalyst. The invention is characterized by the following: 1. due to codoping of the metal and non metallic ion, discrete localized doping level is formed respectively on the lower part of the conduction band energy level and the upper part of the valence band energy level of the TiO2-based catalyst, thus increasing the absorption of visible light and greatly improving the catalytic activity; 2. the doping level can inhibit the recombination of photogenerated carrier, promote the probability of the photogenerated carrier entering into the photocatalytic reaction and efficiently degrade pollutant molecules.

A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.

A method for fabricating a flash memory includes forming a tunnel oxide layer by depositing a material with a conduction band energy level lower than that of SiO₂ on a semiconductor substrate; forming a floating gate by depositing polysilicon on the tunnel oxide layer; forming an intergate dielectric layer on the floating gate; forming a control gate on the intergate dielectric layer; forming a gate electrode by patterning the tunnel oxide layer, the floating gate, the intergate dielectric layer and the control gate; and forming a source/drain region by implanting impurities into the substrate using the gate electrode as a mask.

A capacitor (10) includes a substrate (12) and two metal electrodes (14, 18). A dielectric layer (16) is formed between the electrodes. Preferably, the dielectric layer has a dielectric constant greater than 25 and an adequate conduction band offset with silicon. Exemplary embodiments proposed use the following material systems: Hf_uTi_vTa_wO_xN_y, Hf_uTi_vO_xN_y, Ti_uSr_vO_xN_y, Ti_uAl_vO_xN_y and Hf_uSr_vO_xN_y (where u, v, w, x, and y are the atomic proportions of the elements in the dielectric stack).

A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region and an n-type device region; a first-type suicide contact to the n-type device region; the first-type suicide having a work function that is substantially aligned to the n-type device region conduction band; and a second-type silicide contact to the p-type device region; the second-type silicide having a work function that is substantially aligned to the p-type device region valence band. The present invention also provides a semiconducting structure and a method of forming therefore, in which the silicide contact material and silicide contact processing conditions are selected to provide strain based device improvements in pFET and nFET devices.

A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. A second oxide semiconductor film having a crystalline structure is provided over the first oxide semiconductor film and a third oxide semiconductor film is provided over the second oxide semiconductor film. The bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than the bottom of a conduction band in the first oxide semiconductor film and the bottom of a conduction band in the third oxide semiconductor film.

The invention discloses a high-isolation semi-groove slot antenna array, and relates to a multiple-input-multiple-output antenna. The antenna array consists of three semi-groove slot antennas which are placed together and are pairwise orthogonal in radiating polarization directions, wherein each semi-groove slot antenna consists of a microstrip feeder line on a medium substrate, and a metal ground surface; a radiating semi-groove slot and a plurality of isolation slots are formed in each metal ground surface; the radiating semi-groove slots are rectangular; one end of each radiating semi-groove slot is short-circuit; the other end of each radiating semi-groove slot is open-circuit; the isolation slots around the radiating semi-groove slots are mutually parallel; long side directions of the radiating semi-groove slots are perpendicular to long side directions of the isolation slots; the resonant frequency of the isolation slot is lower than the working frequency of the antennas; one end of each microstrip feeder line is an input-output port of each antenna; and metal short-circuit pins are arranged at the tail ends of microstrip feeder line conduction bands at the other ends of the microstrip feeder lines, and connect the conduction bands and the metal ground surfaces on the edges of the radiating semi-groove slots. The antenna array can effectively reduce adverse effects of the metal ground surfaces on shielding and isolation of normal radiation of the antennas.

A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.

A field effect transistor includes a nitride semiconductor layer; an In_xAl_yGa_1-x-yN layer (wherein 0<x<1, 0<y<1 and 0<x+y<1) formed on the nitride semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the In_xAl_yGa_1-x-yN layer. The lower ends of the conduction bands of the nitride semiconductor layer and the In_xAl_yGa_1-x-yN layer are substantially continuous on the interface therebetween.

A plurality of quantum dots comprise a first inorganic material, and each quantum dot is coated with a second inorganic material. The coated quantum dots being are in a matrix of a third inorganic material. At least the first and third materials are photoconductive semiconductors. The second material is arranged as a tunneling barrier to require a charge carrier (an electron or a hole) at a base of the tunneling barrier in the third material to perform quantum mechanical tunneling to reach the first material within a respective quantum dot. A first quantum state in each quantum dot is between a conduction band edge and a valence band edge of the third material in which the coated quantum dots are embedded. Wave functions of the first quantum state of the plurality of quantum dots may overlap to form an intermediate band.

The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction. The unipolar barrier is configured to raise the conduction band energy level if the surface Fermi energy level is pinned near or above the conduction band energy level or lower the valence band energy level if the surface Fermi energy level is pinned near or below the valence band energy level such that the unipolar barrier is configured to propagate the bulk photocurrent and substantially block surface leakage current. The at least one p-n junction and the unipolar barrier are integrally formed.