16 results about "Equivalent oxide thickness" patented technology

The invention provides a semiconductor structure and a preparation method thereof, a memory device and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; a plurality of semiconductor columns distributed in an array mode and first insulation structures located between the semiconductor columns are manufactured on one side of the substrate, the semiconductor columns extend in the direction perpendicular to the plane of the semiconductor column array, the first insulation structures are provided with first grooves, and channel regions of the semiconductor columns are exposed out of the first grooves; a superlattice film with ferroelectric materials and anti-ferroelectric materials alternating in sequence is manufactured in the first groove, a plurality of gate dielectric layers corresponding to the semiconductor columns in a one-to-one mode are formed, and each gate dielectric layer surrounds at least part of the periphery of a channel region of the corresponding semiconductor column; and manufacturing a grid electrode outside the grid electrode dielectric layer so as to form a plurality of transistors distributed in an array. According to the invention, low electric leakage is maintained while the equivalent oxide thickness is reduced.

The invention provides a method for improving the electrical thickness stability of an ONO laminated layer in a memory device. The method comprises the following steps: obtaining the actually measured thicknesses of a first oxide layer, a silicon nitride layer and a deposited second oxide layer; multiplying the actually measured thickness of the silicon nitride layer by a conversion coefficient to obtain the equivalent oxide thickness; calculating the target thickness of a second oxide layer according to the target electrical thickness, the actually measured thickness of the first oxide layer and the equivalent oxide thickness of the silicon nitride layer; calculating a difference value between the actually measured thickness of the deposited second oxide layer and the target thickness; finally, advanced process control wet soak (APC Dip) treatment is performed on the second oxide layer based on the difference to adjust its thickness. According to the invention, the second oxide layer is adjusted directly based on the electrical thickness target and by considering the dielectric constant difference, so that the thickness fluctuation of the silicon nitride layer can be effectively compensated, the stability and control precision of the electrical thickness of the ONO lamination are remarkably improved, and the performance and yield of a memory device are improved.

The application discloses a MOSCAP device based on p-dipole material Ga2O3 and a preparation method thereof; firstly, a SiO2 interface layer (IL) is grown on a p-Si substrate through a thermal oxidation method; Ga2O3 with different cycle numbers is grown on the IL layer through an atomic layer deposition technology, and a HfO2 film is grown in situ; then, the device is rapidly annealed to repair oxide defects between dielectric layers; finally, a patterned W electrode is prepared, so that the MOSCAP device is obtained; in the application, the MOSCAP device after the Ga2O3 dipole layer is added exhibits a lower hysteresis curve, and only a very low equivalent oxide thickness (EOT) is increased EOT , and significant V FB forward regulation is realized; and the application proves that Ga2O3 is a potential new p-dipole material, and has a wide application prospect in the development of multi-threshold technology at an advanced process node.

The invention provides a gate oxide annealing method for reducing a gate oxide interface state. The method aims at solving the problem that the interface state density of a thin silicon oxynitride gate medium is high. The method comprises the following steps: carrying out first annealing treatment on a nitrided gate oxide layer in a nitrogen atmosphere; and after the first annealing treatment, re-oxidation treatment is carried out on the gate oxide layer in situ in a pure oxygen atmosphere. Through the in-situ re-oxidation treatment, a high-quality silicon dioxide thin layer is formed at the interface of the gate oxide layer and the silicon substrate, so that the dangling bond of the interface is effectively repaired, and the nitrogen concentration at the interface is reduced. According to the invention, the interface state density and gate oxide electric leakage can be significantly reduced, the equivalent oxide thickness is maintained basically unchanged, and the electrical performance and reliability of the semiconductor device are effectively improved.

The present invention provides a capacitor having a double electrode layer in which the thickness of the double electrode layer per one super cycle can be finely adjusted to be 1 nm to 2 nm by a tin doped molybdenum oxide (TMO) process having one super cycle of an atomic layer deposition process including a Mo deposition sub-cycle for forming a Mo oxide layer and a Sn oxide doping sub-cycle for doping the Sn oxide, thereby reducing an equivalent oxide thickness and a leakage current and increasing a dielectric constant.

The present invention discloses a method for fabricating a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric integration technology with an eliminable buffer layer. The method comprises: sequentially depositing a back-gate electrode and a back-gate dielectric on a substrate; transferring a channel layer onto the back-gate dielectric; sequentially forming a buffer layer, a source electrode, a drain electrode, a top-gate dielectric layer formed of a high-k dielectric material, and a top-gate electrode on the channel layer; and annealing the buffer layer in a vacuum environment to sublime the buffer layer, thereby forming van der Waals interfaces between the channel layer and the top-gate dielectric layer, and between the channel layer and the source electrode and the drain electrode. The high-k gate dielectric integration technology based on an eliminable buffer layer provided by the present invention utilizes a buffer layer that can be eliminated after vacuum annealing, thereby avoiding damage to the two-dimensional material, depositing a high-k gate dielectric, achieving interface control between the channel layer and the top-gate dielectric, and miniaturizing the equivalent oxide thickness. Furthermore, the method achieves good contact between the channel layer and the source and drain metals, thereby reducing the contact resistance of the transistor and improving its electrical performance.

The invention provides a semiconductor structure. The semiconductor structure comprises a semiconductor layer; the source region and the drain region are located in the semiconductor layer and are arranged at intervals; the gate structure is located on the semiconductor layer and comprises a gate dielectric layer and a gate which are stacked, the gate dielectric layer comprises a first region close to the drain region and a second region close to the source region, and the equivalent oxide layer thickness of the second region is equal to that of the first region; wherein the first region comprises a first dielectric layer and a second dielectric layer which are stacked; at least part of the first dielectric layer has a first dielectric constant; the second dielectric layer has a second dielectric constant which is greater than the first dielectric constant; the second region has a first dielectric constant. According to the semiconductor structure, the dielectric layer with the high dielectric constant is inserted into the gate dielectric layer close to the drain region, so that an asymmetric gate structure is formed under the condition that an EOT value is not changed, the overhigh longitudinal electric field intensity when high voltage is applied to the drain can be reduced, and the carrier tunneling probability is reduced.

The invention provides a semiconductor structure and a forming method thereof, in the forming method of the semiconductor structure, a first gate dielectric layer is firstly formed, and the first gate dielectric layer covers substrates of a first well region and a second well region; forming a second gate dielectric layer by adopting an atomic layer deposition process, wherein the second gate dielectric layer covers the first gate dielectric layer; wherein the second gate dielectric layer is made of HfTiO. Titanium is an effective dopant, the oxide of titanium has a high k value, and the k value of HfTiO is about 30; and in addition, the HfTiO also shows good thermal stability and is relatively high in crystallization temperature. In addition, Ti and Hf are tetravalent elements, and Ti-doped HfO2 does not cause increase of oxygen vacancies, so that increase of leakage current in the film is avoided. Therefore, by using the Ti-doped hafnium oxide film as the gate oxide dielectric layer, the k value is improved, so that the lower equivalent oxide thickness is obtained under the same thickness, the gate leakage current is reduced, and the device performance is improved.

The invention discloses an asymmetric double-gate two-dimensional semiconductor field effect transistor and a preparation method thereof. The transistor comprises a substrate, a bottom gate dielectric layer is stacked on the substrate, a channel layer is arranged in the center of the bottom gate dielectric layer, a drain electrode and a source electrode are arranged at the two ends of the top of the channel layer respectively, and the drain electrode and the source electrode extend to the bottom gate dielectric layer; a top gate dielectric layer is arranged in the center of the top of the channel layer, a top gate electrode is arranged on the top gate dielectric layer, a bottom gate electrode is arranged at the bottom of the substrate, and the equivalent oxide layer thickness ratio of the bottom gate dielectric layer to the top gate dielectric layer is at least larger than 25 times; according to the invention, the asymmetric double-gate dielectric structure is constructed, so that the gate control capability of the double-gate two-dimensional semiconductor field effect transistor is improved, the regulation and control range of the threshold voltage is increased, and the excellent switching characteristic of the two-dimensional semiconductor field effect transistor is ensured.

The invention relates to the related technical field of semiconductor chips, in particular to a gate-oxide process fault positioning optimization method and system for an MOSFET, and the method comprises the steps: determining gate-oxide process key parameters, constructing a defect type digital feature matrix, carrying out the correlation analysis, setting a first defect recognition vector, carrying out the correlation analysis of a positioning fault source and sensitive parameters, and setting a second vector, and generating a non-dominated solution set, screening an optimal process parameter combination, and sending a compensation instruction. The technical problems that the quality of silicon carbide MOSFET gate oxidation cannot be comprehensively and deeply reflected, a fault process point is difficult to accurately position, and the performance stability of a silicon carbide MOSFET device is low are solved, and a gate oxide defect type digital characteristic matrix is constructed according to key parameters such as the thickness of an equivalent oxide layer and the density of an interface state. Correlation analysis is carried out on the isolation oxide layer and the gate oxide test structure, the gate oxide quality of the silicon carbide MOSFET is monitored and improved, and the performance and reliability of the silicon carbide MOSFET device are improved.

A device includes a substrate, a dielectric structure, a gate electrode, and a drain electrode. The dielectric structure is over the substrate. The dielectric structure includes a first portion, a second portion, and a third portion. The first portion has a first equivalent oxide thickness. The second portion is spaced apart from the first portion and has a second equivalent oxide thickness. The third portion laterally surrounds the first and second portions and has a third equivalent oxide thickness greater than the first equivalent oxide thickness of the first portion. The gate electrode is over the dielectric structure and in contact with the first and third portions of the dielectric structure. The drain electrode is over the dielectric structure and in contact with the second and third portions of the dielectric structure.

The invention belongs to the technical field of semiconductors, and particularly relates to a composite gate dielectric layer for an MISHEMT device, a depletion mode MISHEMT device and a preparation method of the depletion mode MISHEMT device. The composite gate dielectric is prepared at normal temperature through an electron cyclotron resonance physical vapor deposition coating technology, and the composite gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer which are adjacent to each other; the first gate dielectric layer is made of Si3N4, and the second gate dielectric layer is made of Ta2O5. According to the method, electron cyclotron resonance (ECR) coating equipment is used, the ECR effect and the high energy density of ECR plasma are utilized, reaction gas is fully ionized and uniformly deposited, the uniform, compact and defect-free Si3N4 film is formed at the normal temperature, and the problem of Ga atom diffusion in high-temperature deposition is avoided; the second layer is made of a Ta2O5 material, the dielectric constant is high, the thickness of an equivalent oxide layer can be effectively reduced, the gate capacitance density is improved, and the driving capacity of the device is enhanced.

The invention provides a semiconductor device, a preparation method thereof and an integrated circuit, in the device, a first gate insulating layer comprises an oxidation part and a nitrogen oxidation part, and the oxidation part is located on the side, away from a substrate, of the nitrogen oxidation part. Therefore, on one hand, the high K value characteristic of the nitrogen element can be utilized, so that the nitrogen oxidation part has small EOT, the overall equivalent oxide layer thickness of the first gate oxide layer is reduced, the NBTI effect is inhibited, and the device performance is improved. On the other hand, the oxidation part in the first gate insulating layer is located on the side, deviating from the substrate, of the nitrogen oxidation part, so that the oxidation part can serve as a protection layer of the nitrogen oxidation part in the pattern definition process of the first gate insulating layer, the nitrogen oxidation part is prevented from reacting with cleaning liquid used for removing the mask, and the reliability of the mask is improved. Damage of the cleaning liquid to the top of the first gate insulating layer (namely, the side deviating from the substrate) is avoided, and the inhibition effect of the first gate insulating layer on the NBTI effect is guaranteed.

The invention provides an MOSFET device simulation model calculation method, computer equipment and a storage medium. The MOSFET device simulation model calculation method comprises the steps that value transmission of internal parameter variables of a simulation model is conducted according to external input parameters; variable abnormity check is carried out during scaling, the thickness of an equivalent oxide layer of an electrical grid is updated, and then fringing field capacitance calculation is carried out; range checking is carried out on the scaled model internal parameter variables, and associated variable anomaly checking is carried out; a body bias coefficient of a non-uniform depletion width effect is introduced to carry out model calculation on model internal parameter variables which do not exceed the range, and current, charge, conductance and capacitance of each node are obtained; and performing element value filling of a model matrix according to a model calculation result, and introducing multiplication parameters to respectively multiply current, charge and FN noise. According to the scheme, the correctness and precision of the MOSFET device model can be further improved, so that the reliability of a simulation result can be better ensured when the whole circuit is simulated.

The application relates to an insulating material with high dielectric constant, a transistor and a preparation method thereof, which adopts high-purity MoO3 powder, and a MoO3 thin layer is grown on a SiO2 / Si substrate by a physical vapor deposition process; the MoO3 powder is placed in an alumina boat; the substrate is inverted on the alumina boat, and then the alumina boat is placed in the heating center of a single-temperature-zone tubular furnace; the tubular furnace is vacuumized, heated to a target temperature under vacuum, argon is introduced after the target temperature is reached, and the argon is kept for a certain time; the argon is turned off after the heat preservation is finished, the furnace is naturally cooled, and a MoO3 thin layer which stands on the substrate is obtained; the material has the characteristics of high dielectric constant, ultra-thin equivalent oxide thickness and the like, a transistor is obtained through a polymer-free transfer method, the cleanliness of a device manufacturing contact surface is protected, the electrical performance is greatly improved, the structural stability of the material is maintained, and the device shows excellent transfer characteristics.

In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.