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Manufacturing method for semiconductor element

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as severe interface layer thickness

Active Publication Date: 2010-03-03
TAIWAN SEMICON MFG CO LTD
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  • Abstract
  • Description
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Problems solved by technology

Therefore, the desire to control the thickness of this interfacial layer becomes more and more critical as the gate length decreases

Method used

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  • Manufacturing method for semiconductor element
  • Manufacturing method for semiconductor element
  • Manufacturing method for semiconductor element

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Embodiment Construction

[0017] The process of forming a semiconductor device on a substrate will be first described below, especially the description about forming a gate structure. In various examples in this specification, repeated reference numerals may appear to simplify the description, but this does not mean that there is any specific relationship between the various embodiments and / or the drawings. Furthermore, when it is mentioned that a certain layer is “on” or “over” another layer, it may mean that the two layers are in direct contact or that other elements or film layers are interposed therebetween.

[0018] figure 1 A method 100 for forming a gate electrode according to an embodiment of the present invention is shown. Figure 2 to Figure 9 in accordance with figure 1 The process cross-sectional schematic diagram corresponding to the manufacturing steps. The method 100 may include a partial or complete integrated circuit process, including static random access memory (Static Random Acce...

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Abstract

A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and / or restricted from growth. The invention is beneficial to controlling the equivalent oxide thickness of the gate structure. The gettering layer includes a dielectric layer and / or a metal layer, thus the gettering layer is able to be removed from the gate stack or retained in the structure.

Description

technical field [0001] The present invention relates to an integrated circuit device, and more particularly to a method of forming a gate structure in an IC device. Background technique [0002] With the reduction of critical dimensions of semiconductors, semiconductor processes have introduced gate dielectric materials with high dielectric constants. The high-k dielectric has a higher dielectric constant than conventionally used silicon dioxide, allowing relatively thicker dielectric layers at similar equivalent oxide thicknesses (EOTs). This process also facilitates the introduction of metal gate structures with lower resistance than conventional polysilicon. Therefore, transistors with high-k dielectrics plus metal gate stacks are advantageous. [0003] However, the process of fabricating high-k dielectric plus metal gate structures faces challenges. For example, high-k dielectric layers (such as hafnium oxide; HfO 2 ) and a substrate (such as silicon) to form an inte...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/283H01L21/336
CPCH01L21/28185H01L29/51H01L21/3221H01L21/28518H01L29/513H01L29/49
Inventor 陈建豪侯永田徐鹏富黄国泰赵元舜洪正隆
Owner TAIWAN SEMICON MFG CO LTD
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