Method of forming HfSiN metal for n-FET applications

Abstract

A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) device which includes a thermally stable n-type metal on a high dielectric constant, k / interfacial layer stack. The present invention also provides a process for forming the thermally stable n-type metal which can be integrated with a CMOS processing flow. BACKGROUND OF THE INVENTION [0002] In standard CMOS devices, polysilicon is typically the standard gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that they can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect and relative high electr...

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Benefits of technology

[0018] In accordance with the present invention, the Si source diluted with He, which limits the Si source reactivity, improves the quality of the film. The resistivities of the HfSiN film can vary depending on the concentration of the process gases. Typically, the higher the nitrogen and / or Si concentrations, the higher the resistivity.

Problems solved by technology

However, there are also some problems associated with using a polysilicon gate.

Another problem with polySi gates is that the dopant in the polySi gate, such as boron, can easily diffuse through the thin gate dielectric causing further degradation of the device performance.

Gate stack reactions occur during this high temperature anneal limiting the choice of materials.

Metal compounds may be more stable, but still have problems with targeting the right workfunction.

Furthermore, it appears that the inversion thickness scability is somewhat limited using TaSiN.

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