Semiconductor device

Abstract

The invention relates to a semiconductor device, in particular to an interface optimized high-k gate dielectric complementary metal oxide semiconductor (CMOS) device. Interface layers with different thicknesses and different materials are adopted on a semiconductor substrate in an N-channel metal oxide semiconductor (NMOS) region and a semiconductor substrate of a P-channel metal oxide semiconductor (PMOS) region, the equivalent oxide thickness (EOT) of a device, in particular the EOT of a PMOS device, is effectively reduced, and the electron mobility of the device, in particular the electronmobility of an NMOS device is improved, so that the overall performance of the device is effectively improved.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a high-k gate dielectric CMOS device with optimized interface. Background technique [0002] With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself also need to be further reduced. The application of the core technology of 32 / 22 nanometer process integrated circuits has become an inevitable trend in the development of integrated circuits, and it is also one of the topics that major international semiconductor companies and research organizations are competing to research and develop. The gate engineering research of CMOS devices with "high-k / metal gate" technology as the core is the most representative core process in 32 / 22 nanometer technology, and the related material, process and structure research ...

AI Technical Summary

Problems solved by technology

The resulting problem is that with the continuous thinning of the interface layer, some atoms in the high-k gate dielectric material will diffuse to the channel region of the semiconductor substrate through the ultra-thin interface layer under high-temperature heat treatment. In turn, the carrier mobility of the channel region is degraded, and the problem of carrier mobility degradation caused by atomic diffusion in the high-k gate dielectric is more serious for NMOS devices, and the impact is relatively serious for PMOS devices much smaller

Moreover, SiON with a large dielectric constant is commonly used in the interface layer in the prior art. x , but the resulting problem is that the introduction of N in the interface layer will degrade the carrier mobility, especially the electron carrier mobility of NMOS devices

In addition, when the high-k gate dielectric is in direct contact with the semiconductor substrate, a higher interface state will be generated, which will also degrade the carrier mobility, especially the electron carrier mobility, which will affect the carrier mobility of the NMOS device. rate has a big impact on

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