35 results about "Polycrystalline semiconductor" patented technology

A memory device includes alternating stacks that are laterally spaced apart from each other by lateral isolation trench fill structures, and each of the alternating stacks includes a respective vertically alternating sequence of insulating layers and electrically conductive layers, memory openings vertically extending through a respective one of the alternating stacks, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a polycrystalline semiconductor source layer underlying the alternating stack and contacting bottom surfaces of the vertical semiconductor channels. Each of the lateral isolation trench fill structures includes a thermally conductive trench fill material portion that is vertically spaced from the polycrystalline semiconductor source layer by a thermally insulating material.

The subject of the invention is a method for producing a polycrystalline semiconductor material, comprising introducing a reaction gas containing hydrogen and at least one semiconductor component into a reaction chamber of a vapor deposition reactor, the reaction chamber being delimited by a reactor housing and a bottom plate, wherein the reaction gas is introduced through at least one nozzle located in the bottom plate, and wherein the reaction chamber contains at least two filament rods attached to the bottom plate, on which the semiconductor material is deposited, wherein the at least two filament rods differ in length.

A waveguide-type visible and near-infrared photodetector structure and preparation method thereof are provided. The structure includes a dielectric layer, a cladding layer, an optical waveguide layer, an intermediate layer, and an electroabsorption layer from top to bottom; the electroabsorption layer and the dielectric layer are communicated through an optical-layer-to-electronic-layer via structure; the dielectric layer is made of a single-crystal or polycrystalline semiconductor material. The method enables the fabrication of a waveguide-type visible and near-infrared photodetector with large bandwidth and high sensitivity, and has the advantages of fewer process steps and a simple driving circuit design.

An organic light emitting display apparatus is disclosed that comprises a substrate including a first portion and a second portion; a first thin film transistor having a first polycrystalline semiconductor pattern, the first thin film transistor on the first portion of the substrate; a second thin film transistor having a first oxide semiconductor pattern, the second thin film transistor on the second portion of the substrate; and an organic light emitting device configured to emit light, the organic light emitting device connected to the second thin film transistor; wherein the first polycrystalline semiconductor pattern includes a surface that is planarized and the first oxide semiconductor pattern includes a surface that includes a plurality of protrusions.

Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor.

A display device includes a substrate, first and second transistors on the substrate, a first electrode connected to one of the first and second transistors, a second electrode facing the first electrode, and a light emission member between the first and second electrodes, where the first transistor includes a first channel including a polycrystalline semiconductor member on the substrate, a first source electrode and a first drain electrode at respective opposite sides of the first channel, a first gate electrode overlapping the first channel, and a first insulating layer covering the first gate electrode, the second transistor includes a second gate electrode on the first insulating layer, a second channel including an oxide semiconductor member on the second gate electrode, second source and drain electrodes on the second channel, and an external light blocking member on the second source and drain electrodes and overlapping the second channel.

Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.

Method (100) for producing a technical semiconductor substrate comprising the steps of providing (110) a powder mixture comprising a semiconductor powder having a first coefficient of thermal expansion and an additive having a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion, producing (120) a polycrystalline semiconductor substrate from the powder mixture by sintering, wherein the polycrystalline semiconductor substrate has a third coefficient of thermal expansion which is greater than the first coefficient of thermal expansion, and depositing (130) a monocrystalline semiconductor layer onto the polycrystalline semiconductor substrate by bonding.

An organic light emitting display apparatus is disclosed that comprises a substrate including a first portion and a second portion; a first thin film transistor having a first polycrystalline semiconductor pattern, the first thin film transistor on the first portion of the substrate; a second thin film transistor having a first oxide semiconductor pattern, the second thin film transistor on the second portion of the substrate; and an organic light emitting device configured to emit light, the organic light emitting device connected to the second thin film transistor; wherein the first polycrystalline semiconductor pattern includes a surface that is planarized and the first oxide semiconductor pattern includes a surface that includes a plurality of protrusions.

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor through hole, a semiconductor interposer and a preparation method of the semiconductor interposer. The invention provides a preparation method of a semiconductor interposer, which comprises the following steps of: forming lattice defects in a preset through hole region of a semiconductor substrate, and growing an epitaxial semiconductor material layer; selectively removing the amorphous or polycrystalline semiconductor material in the preset through hole region through a corrosion process to obtain a semiconductor intermediate layer through hole; filling the through hole with metal to form a conductive through hole; and thinning the second surface of the semiconductor substrate until the conductive through hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor intermediate layer. According to the method, local internal stress generated by deep reactive ion etching or laser through holes is fundamentally avoided, etching damage to the inner walls of the through holes is reduced, the integrity of the semiconductor interposer is remarkably improved, and the risks of warping, internal stress and even breakage of high wafer level or chip level packaging are fundamentally reduced.

Disclosed is an organic light emitting display apparatus including hybrid type thin film transistors comprising a driving thin film transistor of a subpixel including an oxide semiconductor pattern such that the s-factor value of the driving thin film transistor is increased and a thin film transistor formed in at least one of a non-active area and an active area, the thin film transistor including a polycrystalline semiconductor pattern, wherein the organic light emitting display apparatus includes various storage capacitors formed by imparting conductivity to the polycrystalline semiconductor pattern and the oxide semiconductor pattern.

Disclosed is a display panel including: a substrate divided into a first area and a second area positioned outside the first area; a buffer layer disposed in the first area and the second area and disposed on the substrate; a first thin-film transistor including a polycrystalline semiconductor layer disposed in the first area and disposed on the buffer layer, and a first gate electrode disposed on the polycrystalline semiconductor layer; a second thin-film transistor including an oxide semiconductor layer disposed in the first area and disposed on the buffer layer, and a second gate electrode disposed on the oxide semiconductor layer; a first intermediate insulating layer disposed between the first area and the second area and interposed between the first thin-film transistor and the second thin-film transistor; a first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; and a second contact hole passing through the first intermediate insulating layer in the second area.

An organic light emitting display device including both a polycrystalline semiconductor element and an oxide semiconductor element, and a method of manufacturing the display device are disclosed. In order to solve the damage of an oxide semiconductor pattern during a heat treatment process in the process of forming the oxide semiconductor element, until the process of forming the polycrystalline semiconductor element is completed, after one portion of a connection electrode connecting a polycrystalline semiconductor pattern to source and drain electrodes is formed in advance, then by forming the other portion of the connection electrode for completing the connection between the source and drain electrodes to the polycrystalline semiconductor pattern in the process of forming the oxide semiconductor element, the connection electrode can have a connection node between two edges thereof, and thereby, the performance of the oxide semiconductor element can be improved.

This invention relates to a semiconductor structure having a main contact region embedded in a polycrystalline semiconductor material, and discloses a main contact semiconductor structure and a method for forming the main contact semiconductor structure. A semiconductor substrate comprising a single-crystal semiconductor material includes a device region and a plurality of main contact regions, each main contact region being composed of a single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are located between the polycrystalline layer and the device region, and the polycrystalline regions are arranged with lateral spacing, with gaps between adjacent pairs of polycrystalline regions. One of the plurality of main contact regions is disposed in the gap between adjacent pairs of polycrystalline regions.

The application discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductor, and is used for simplifying the manufacturing process of a three-dimensional stacked complementary transistor, reducing the manufacturing difficulty of the three-dimensional stacked complementary transistor, and further improving the working performance of the three-dimensional stacked complementary transistor. The semiconductor device comprises a semiconductor substrate, a first ring-gate transistor and a second ring-gate transistor. The first ring-gate transistor is formed on the semiconductor substrate. The material of a channel region of the first ring-gate transistor is single-crystal semiconductor material. The second ring-gate transistor is formed above the first ring-gate transistor and is arranged in a spaced mode with the first ring-gate transistor. The material of a channel region of the second ring-gate transistor is polycrystal semiconductor material. The second ring-gate transistor and the first ring-gate transistor constitute a three-dimensional stacked complementary transistor. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor.

A method for manufacturing a semiconductor device includes: forming a release layer including a first polycrystalline semiconductor layer provided on a first substrate, and a second polycrystalline semiconductor layer provided between the first substrate and the first polycrystalline semiconductor layer and having a p-type impurity concentration which is lower than that of the first polycrystalline semiconductor layer, and an n-type impurity concentration which is higher than that of the first polycrystalline semiconductor layer; subjecting the first polycrystalline semiconductor layer to anodic chemical conversion to form a first porous layer; forming a first device layer on the first porous layer; and bonding together the first device layer and a second device layer provided on a second substrate.

The invention discloses a method and a device for horizontally synthesizing a large-size high-purity indium phosphide polycrystalline semiconductor material. The method comprises the steps of high-purity material preparation and sealing, heating reaction and pressure regulation and control, heat preservation reaction, temperature gradient regulation and control, cooling crystallization, annealing treatment, pressure relief and material taking and the like. The method comprises the following steps: controlling the molar ratio range of high-purity indium and high-purity phosphorus to be 1-1.2, reacting at a specific temperature, regulating and controlling the pressure to be 2.5-4.0 MPa, and controlling the axial temperature difference to be 0-15 DEG C / cm and the radial temperature difference to be 0-5 DEG C / cm by utilizing a direct-current resistance heating furnace, so as to prepare the indium phosphide polycrystal with the diameter of 150-212mm and the length of more than or equal to 400mm. The method solves the problems of uneven radial thermal field and the like in the prior art, the crystal does not have indium-rich and phosphorus-rich areas, holes or cracks, the impurity content is less than or equal to 1.0 * 10 <-6 > level, the productivity per unit volume is improved by 4 times, the one-time synthesis amount reaches 15kg or above, the energy consumption is reduced by 15% or above, the cost is reduced by 30% or above, and the method is suitable for industrial production.

The present invention relates to a hybrid organic light emitting display device including a driving thin film transistor having an oxide semiconductor pattern and a switching thin film transistor having an oxide semiconductor pattern or a polycrystalline semiconductor pattern in a driving device unit for driving a unit pixel, in which a light blocking layer below an active layer is electrically connected to a source electrode to form the driving thin film transistor with wide control range at low gradation and the light blocking layer is disposed as close as possible to the active layer to broaden the control range of the driving thin film transistor.

A memory device includes alternating stacks that are laterally spaced apart from each other by lateral isolation trench fill structures, and each of the alternating stacks includes a respective vertically alternating sequence of insulating layers and electrically conductive layers, memory openings vertically extending through a respective one of the alternating stacks, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a polycrystalline semiconductor source layer underlying the alternating stack and contacting bottom surfaces of the vertical semiconductor channels. Each of the lateral isolation trench fill structures includes a thermally conductive trench fill material portion that is vertically spaced from the polycrystalline semiconductor source layer by a thermally insulating material.

The invention relates to a method (100) for producing a technical semiconductor substrate, comprising the steps of providing (110) a powder mixture comprising a semiconductor powder having a first coefficient of thermal expansion and an additive having a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion, producing (120) a polycrystalline semiconductor substrate from the powder mixture by means of sintering, wherein the polycrystalline semiconductor substrate has a third coefficient of thermal expansion which is greater than the first coefficient of thermal expansion, and applying (130) a monocrystalline semiconductor layer to the polycrystalline semiconductor substrate by means of bonding.

Provided is a display device. The display device comprises a first flexible substrate, a second flexible substrate including a first area, a second area, and a third area, and an intermediate layer between the first flexible substrate and the second flexible substrate. A plurality of pixels is disposed in the first area, and the plurality of pixels includes a first transistor including a polycrystalline semiconductor and a first gate electrode, a second transistor including an oxide semiconductor and a second gate electrode composed of a first metal layer, a second metal layer, and a third metal layer, and a third transistor including the polycrystalline semiconductor disposed in the second area, and a plurality of dams, a first line, a second line, and a cathode are disposed in the third area, and the cathode extends to the first area and the second area.

A flexible display device comprising: a flexible substrate; a semiconductor layer over the flexible substrate, the semiconductor layer comprising a polycrystalline semiconductor; a gate insulating layer over the semiconductor layer; and a gate electrode over the gate insulating layer, the gate electrode overlapping a channel region of the semiconductor layer in plan view, wherein the semiconductor layer includes a source region and a drain region located on opposite sides of the channel region, wherein the channel region includes a first region in contact with the source region and a second region in contact with the drain region, and wherein a channel width of the first region is greater than a channel width of the second region.

A display device according to an embodiment of the present disclosure includes a light emitting diode electrically connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor electrically connected between the driving voltage line and the light emitting diode; a second transistor electrically connected between a first electrode of the driving transistor electrically connected to the driving voltage line and a data line to which a data voltage is applied; a first scan line electrically connected to a gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor connected to the light emitting diode and a gate electrode of the driving transistor; a connection electrode electrically connecting the gate electrode of the driving transistor and the third transistor, and a contact portion electrically contacting the connection electrode and the third transistor, at least a portion of the contact portion not overlapping the first scan line, the driving transistor and the second transistor including a polycrystal semiconductor, and the third transistor including an oxide semiconductor.

Integrated circuits with embedded memory that includes double-walled ferroelectric capacitors over an array of access transistors. Capacitor access transistors may be recessed channel array transistors (RCATs) implemented in a monocrystalline material that has been transferred from a donor wafer, or implemented in an amorphous or polycrystalline semiconductor material that has been deposited, such as a metal oxide semiconductor.

A solar battery according to the present embodiment has an electrode, which includes a metal and an adhesive material, formed in a conductive region including a polycrystalline semiconductor layer, and thus, the electrical characteristics of the solar battery may be improved and the manufacturing process thereof may be simplified. More specifically, the solar battery includes a semiconductor substrate, and the conductive region including the polycrystalline semiconductor layer is positioned on one surface of the semiconductor substrate.

A susceptor configured to hold one or more WBG (Wide Bandgap) semiconductor wafers for epitaxial layer growth to support a manufacture of at least one WBG semiconductor device. A susceptor is removed from an epitaxial reactor when a predetermined thickness of polycrystalline WBG semiconductor material builds up from growing epitaxial layers on one or more WBG semiconductor wafers. The susceptor is scanned by a laser such that the energy from the laser is absorbed by the one or more layers of polycrystalline WBG semiconductor material to decompose the one or more layers of polycrystalline WBG semiconductor material into two or more constituent components. The two or more constituent components are then removed from the susceptor by etching to produce a cleaned susceptor. The cleaned susceptor can then be placed in an epitaxial reactor to grow epitaxial wafers on WBG semiconductor wafers.

The application relates to a power switch transistor and belongs to the field of semiconductor power devices. The transistor comprises a drift region, a semiconductor body region, a terminal voltage resistance region, a floating electrode semiconductor region, a gate insulating medium region, a third electrode polycrystalline semiconductor region, a first insulating passivation layer, a second insulating passivation layer, a second electrode metal region, a floating electrode metal region, a third electrode metal region, a first electrode semiconductor region and a first electrode metal region. The second insulating passivation layer and the second electrode surface metal layer form a terminal metal shielding structure, the influence of a packaging lead or a copper belt on the terminal voltage resistance region of the power switch transistor chip can be effectively eliminated, the breakdown voltage of the chip is ensured not to be disturbed, the length of the packaging lead or the copper belt can be further shortened, even without lead bonding, so that the area occupied by the chip packaging lead and the parasitic inductance introduced by the lead are reduced.

A method includes providing a workpiece. The workpiece includes a fin-shaped structure including a fin base and a stack of semiconductor layers over the fin base, a dummy gate structure disposed over the stack of semiconductor layers, and a source / drain feature connected to the channel layers of the stack of semiconductor layers and disposed on a side of the dummy gate structure. The stack of semiconductor layers includes channel layers interleaving with sacrificial layers. The method further includes forming a trench in the dummy gate structure and the fin-shaped structure, depositing a dielectric layer in the trench, depositing a polycrystalline semiconductor material over the dielectric layer, performing a planarization process to the workpiece, and replacing the dielectric layer, the polycrystalline semiconductor material, the dummy gate structure, and the sacrificial layers with a metal gate structure.

The invention relates to a method for producing polycrystalline semiconductor material, comprising introducing a reaction gas, which contains at least one semiconductor component in addition to hydrogen, into a reaction chamber of a gas phase deposition reactor delimited by a reactor jacket and a base plate, wherein the reaction gas is introduced through at least one nozzle located in the base plate and wherein the reaction chamber contains at least two filament rods attached to the base plate, onto which rods the semiconductor material is deposited, wherein at least two filament rods are different lengths.