63 results about "Polycrystalline semiconductor" patented technology

A memory device includes alternating stacks that are laterally spaced apart from each other by lateral isolation trench fill structures, and each of the alternating stacks includes a respective vertically alternating sequence of insulating layers and electrically conductive layers, memory openings vertically extending through a respective one of the alternating stacks, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a polycrystalline semiconductor source layer underlying the alternating stack and contacting bottom surfaces of the vertical semiconductor channels. Each of the lateral isolation trench fill structures includes a thermally conductive trench fill material portion that is vertically spaced from the polycrystalline semiconductor source layer by a thermally insulating material.

The subject of the invention is a method for producing a polycrystalline semiconductor material, comprising introducing a reaction gas containing hydrogen and at least one semiconductor component into a reaction chamber of a vapor deposition reactor, the reaction chamber being delimited by a reactor housing and a bottom plate, wherein the reaction gas is introduced through at least one nozzle located in the bottom plate, and wherein the reaction chamber contains at least two filament rods attached to the bottom plate, on which the semiconductor material is deposited, wherein the at least two filament rods differ in length.

A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

The display device includes: a substrate; a polycrystalline semiconductor layer including a channel of the driving transistor and a channel of the seventh transistor; a gate electrode of the driving transistor overlapping with its channel; a gate electrode of the seventh transistor overlapping with its channel; an oxide semiconductor layer including a channel of the fourth transistor; a gate electrode of the fourth transistor overlapping with its channel; a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and a gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

The display device includes: a substrate; a polycrystalline semiconductor layer including a channel of the driving transistor and a channel of the seventh transistor; a gate electrode of the driving transistor overlapping with its channel; a gate electrode of the seventh transistor overlapping with its channel; an oxide semiconductor layer including a channel of the fourth transistor; a gate electrode of the fourth transistor overlapping with its channel; a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and a gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

A waveguide-type visible and near-infrared photodetector structure and preparation method thereof are provided. The structure includes a dielectric layer, a cladding layer, an optical waveguide layer, an intermediate layer, and an electroabsorption layer from top to bottom; the electroabsorption layer and the dielectric layer are communicated through an optical-layer-to-electronic-layer via structure; the dielectric layer is made of a single-crystal or polycrystalline semiconductor material. The method enables the fabrication of a waveguide-type visible and near-infrared photodetector with large bandwidth and high sensitivity, and has the advantages of fewer process steps and a simple driving circuit design.

The utility model relates to the technical field of semiconductor materials, and discloses a quartz product for synthesizing a large-size high-purity indium phosphide polycrystalline semiconductor material, which comprises a quartz tube, a convex groove is arranged at the top of the quartz tube, a quartz cap is arranged at one end of the quartz tube and the convex groove, and fixing blocks are fixedly connected to two ends of the convex groove. The same guide rod is fixedly connected between the two fixed blocks, the guide rod is slidably sleeved with the same rectangular block, the rectangular block is provided with a round hole matched with the guide rod, the two sides of the end, away from the quartz cap, of the rectangular block are each provided with a first special-shaped groove, and the two sides of the other end of the rectangular block are each provided with a second special-shaped groove; one end of the inner wall of the quartz tube away from the quartz cap is provided with a quartz phosphorus boat. According to the utility model, gaps among the quartz phosphorus boat, the quartz column and the quartz indium boat are enough, so that phosphorus steam can stably pass through, a thermal field in the quartz tube can be more stable, and the synthesis quality of indium phosphide polycrystals is improved.

An organic light emitting display apparatus is disclosed that comprises a substrate including a first portion and a second portion; a first thin film transistor having a first polycrystalline semiconductor pattern, the first thin film transistor on the first portion of the substrate; a second thin film transistor having a first oxide semiconductor pattern, the second thin film transistor on the second portion of the substrate; and an organic light emitting device configured to emit light, the organic light emitting device connected to the second thin film transistor; wherein the first polycrystalline semiconductor pattern includes a surface that is planarized and the first oxide semiconductor pattern includes a surface that includes a plurality of protrusions.

Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor.

A display device includes a substrate, first and second transistors on the substrate, a first electrode connected to one of the first and second transistors, a second electrode facing the first electrode, and a light emission member between the first and second electrodes, where the first transistor includes a first channel including a polycrystalline semiconductor member on the substrate, a first source electrode and a first drain electrode at respective opposite sides of the first channel, a first gate electrode overlapping the first channel, and a first insulating layer covering the first gate electrode, the second transistor includes a second gate electrode on the first insulating layer, a second channel including an oxide semiconductor member on the second gate electrode, second source and drain electrodes on the second channel, and an external light blocking member on the second source and drain electrodes and overlapping the second channel.

Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.

Method (100) for producing a technical semiconductor substrate comprising the steps of providing (110) a powder mixture comprising a semiconductor powder having a first coefficient of thermal expansion and an additive having a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion, producing (120) a polycrystalline semiconductor substrate from the powder mixture by sintering, wherein the polycrystalline semiconductor substrate has a third coefficient of thermal expansion which is greater than the first coefficient of thermal expansion, and depositing (130) a monocrystalline semiconductor layer onto the polycrystalline semiconductor substrate by bonding.

An embodiment provides a semiconductor device, a storage device, and a method for manufacturing a transistor that can stably improve characteristics. The semiconductor device of the embodiment includes a substrate, a gate insulating film on the substrate, a stacked semiconductor layer, and a metal layer on or above the stacked semiconductor layer. The stacked semiconductor layer has: a first layer formed on the gate insulating layer and including polycrystalline semiconductor doped with phosphorus; a second layer formed on the first layer and including polycrystalline semiconductor doped with carbon; and a third layer formed on the second layer and including polycrystalline semiconductor doped with phosphorus or undoped with phosphorus. The phosphorus content of the third layer is less than that of the first layer, or the third layer does not contain phosphorus.

An organic light emitting display apparatus is disclosed that comprises a substrate including a first portion and a second portion; a first thin film transistor having a first polycrystalline semiconductor pattern, the first thin film transistor on the first portion of the substrate; a second thin film transistor having a first oxide semiconductor pattern, the second thin film transistor on the second portion of the substrate; and an organic light emitting device configured to emit light, the organic light emitting device connected to the second thin film transistor; wherein the first polycrystalline semiconductor pattern includes a surface that is planarized and the first oxide semiconductor pattern includes a surface that includes a plurality of protrusions.

The display device includes: a substrate; a polycrystalline semiconductor layer including a channel of the driving transistor and a channel of the seventh transistor; a gate electrode of the driving transistor overlapping with its channel; a gate electrode of the seventh transistor overlapping with its channel; an oxide semiconductor layer including a channel of the fourth transistor; a gate electrode of the fourth transistor overlapping with its channel; a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and a gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

A solar battery according to the present embodiment has an electrode, which includes a metal and an adhesive material, formed in a conductive region including a polycrystalline semiconductor layer, and thus, the electrical characteristics of the solar battery may be improved and the manufacturing process thereof may be simplified. More specifically, the solar battery includes a semiconductor substrate, and the conductive region including the polycrystalline semiconductor layer is positioned on one surface of the semiconductor substrate.

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor through hole, a semiconductor interposer and a preparation method of the semiconductor interposer. The invention provides a preparation method of a semiconductor interposer, which comprises the following steps of: forming lattice defects in a preset through hole region of a semiconductor substrate, and growing an epitaxial semiconductor material layer; selectively removing the amorphous or polycrystalline semiconductor material in the preset through hole region through a corrosion process to obtain a semiconductor intermediate layer through hole; filling the through hole with metal to form a conductive through hole; and thinning the second surface of the semiconductor substrate until the conductive through hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor intermediate layer. According to the method, local internal stress generated by deep reactive ion etching or laser through holes is fundamentally avoided, etching damage to the inner walls of the through holes is reduced, the integrity of the semiconductor interposer is remarkably improved, and the risks of warping, internal stress and even breakage of high wafer level or chip level packaging are fundamentally reduced.

In one embodiment, a semiconductor die includes a polycrystalline semiconductor resistor structure (poly resistor structure). The poly resistor structure includes a resistive path between a first terminal and a second terminal. The poly resistor structure includes a first region having a net first conductivity type dopant concentration located in the resistance path and a second region having a net second conductivity type dopant concentration located in the resistance path. A silicide structure is located on both a first portion of the first region and a first portion of the second region to electrically connect the first portion of the first region and the first portion of the second region. In some embodiments, poly resistor structures with different conductivity type regions can be connected together.

An organic light emitting diode display and an electronic device are provided. The organic light emitting diode display includes: a first thin film transistor having a channel formed in a polycrystalline semiconductor layer; a second thin film transistor having a channel formed in the oxide semiconductor layer; an organic light emitting diode electrically connected to the first thin film transistor; a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to the gate electrode of the first thin film transistor; and an overlapping layer overlapping the oxide semiconductor layer in plan view and receiving the positive voltage. The oxide semiconductor layer is placed higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.

Disclosed is an organic light emitting display apparatus including hybrid type thin film transistors comprising a driving thin film transistor of a subpixel including an oxide semiconductor pattern such that the s-factor value of the driving thin film transistor is increased and a thin film transistor formed in at least one of a non-active area and an active area, the thin film transistor including a polycrystalline semiconductor pattern, wherein the organic light emitting display apparatus includes various storage capacitors formed by imparting conductivity to the polycrystalline semiconductor pattern and the oxide semiconductor pattern.

Disclosed is a display panel including: a substrate divided into a first area and a second area positioned outside the first area; a buffer layer disposed in the first area and the second area and disposed on the substrate; a first thin-film transistor including a polycrystalline semiconductor layer disposed in the first area and disposed on the buffer layer, and a first gate electrode disposed on the polycrystalline semiconductor layer; a second thin-film transistor including an oxide semiconductor layer disposed in the first area and disposed on the buffer layer, and a second gate electrode disposed on the oxide semiconductor layer; a first intermediate insulating layer disposed between the first area and the second area and interposed between the first thin-film transistor and the second thin-film transistor; a first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; and a second contact hole passing through the first intermediate insulating layer in the second area.

The present invention relates to a hybrid organic light emitting display device including a driving thin film transistor having an oxide semiconductor pattern and a switching thin film transistor having an oxide semiconductor pattern or a polycrystalline semiconductor pattern in a driving device unit for driving a unit pixel, in which a light blocking layer below an active layer is electrically connected to a source electrode to form the driving thin film transistor with wide control range at low gradation and the light blocking layer is disposed as close as possible to the active layer to broaden the control range of the driving thin film transistor.

An emissive display device includes a polycrystalline semiconductor including a channel, source region, and drain region of a driving transistor disposed on a substrate. The device includes a gate electrode of the driving transistor overlapping the channel of the driving transistor, an oxide semiconductor including a channel, a source region, and a drain region of a second transistor disposed on the substrate, and a first connection electrode. The first connection electrode includes a first connector electrically connected to the gate electrode of the driving transistor, a second connector electrically connected to a second electrode of the second transistor, and a main body disposed between the first connector and the second connector. The device includes an initialization voltage line disposed on the substrate and applying an initialization voltage. The initialization voltage line surrounds at least a part of the second connector of the first connection electrode.

An organic light emitting display device including both a polycrystalline semiconductor element and an oxide semiconductor element, and a method of manufacturing the display device are disclosed. In order to solve the damage of an oxide semiconductor pattern during a heat treatment process in the process of forming the oxide semiconductor element, until the process of forming the polycrystalline semiconductor element is completed, after one portion of a connection electrode connecting a polycrystalline semiconductor pattern to source and drain electrodes is formed in advance, then by forming the other portion of the connection electrode for completing the connection between the source and drain electrodes to the polycrystalline semiconductor pattern in the process of forming the oxide semiconductor element, the connection electrode can have a connection node between two edges thereof, and thereby, the performance of the oxide semiconductor element can be improved.

This invention relates to a semiconductor structure having a main contact region embedded in a polycrystalline semiconductor material, and discloses a main contact semiconductor structure and a method for forming the main contact semiconductor structure. A semiconductor substrate comprising a single-crystal semiconductor material includes a device region and a plurality of main contact regions, each main contact region being composed of a single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are located between the polycrystalline layer and the device region, and the polycrystalline regions are arranged with lateral spacing, with gaps between adjacent pairs of polycrystalline regions. One of the plurality of main contact regions is disposed in the gap between adjacent pairs of polycrystalline regions.

The application discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductor, and is used for simplifying the manufacturing process of a three-dimensional stacked complementary transistor, reducing the manufacturing difficulty of the three-dimensional stacked complementary transistor, and further improving the working performance of the three-dimensional stacked complementary transistor. The semiconductor device comprises a semiconductor substrate, a first ring-gate transistor and a second ring-gate transistor. The first ring-gate transistor is formed on the semiconductor substrate. The material of a channel region of the first ring-gate transistor is single-crystal semiconductor material. The second ring-gate transistor is formed above the first ring-gate transistor and is arranged in a spaced mode with the first ring-gate transistor. The material of a channel region of the second ring-gate transistor is polycrystal semiconductor material. The second ring-gate transistor and the first ring-gate transistor constitute a three-dimensional stacked complementary transistor. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor.

A method for manufacturing a semiconductor device includes: forming a release layer including a first polycrystalline semiconductor layer provided on a first substrate, and a second polycrystalline semiconductor layer provided between the first substrate and the first polycrystalline semiconductor layer and having a p-type impurity concentration which is lower than that of the first polycrystalline semiconductor layer, and an n-type impurity concentration which is higher than that of the first polycrystalline semiconductor layer; subjecting the first polycrystalline semiconductor layer to anodic chemical conversion to form a first porous layer; forming a first device layer on the first porous layer; and bonding together the first device layer and a second device layer provided on a second substrate.

The display device includes: a substrate; a polycrystalline semiconductor layer including a channel of a driving transistor and a channel of a seventh transistor; a gate electrode of the driving transistor overlapping with its channel; a gate electrode of the seventh transistor overlapping with its channel; an oxide semiconductor layer including a channel of a fourth transistor; a gate electrode of the fourth transistor overlapping with its channel; a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

The invention discloses a method and a device for horizontally synthesizing a large-size high-purity indium phosphide polycrystalline semiconductor material. The method comprises the steps of high-purity material preparation and sealing, heating reaction and pressure regulation and control, heat preservation reaction, temperature gradient regulation and control, cooling crystallization, annealing treatment, pressure relief and material taking and the like. The method comprises the following steps: controlling the molar ratio range of high-purity indium and high-purity phosphorus to be 1-1.2, reacting at a specific temperature, regulating and controlling the pressure to be 2.5-4.0 MPa, and controlling the axial temperature difference to be 0-15 DEG C / cm and the radial temperature difference to be 0-5 DEG C / cm by utilizing a direct-current resistance heating furnace, so as to prepare the indium phosphide polycrystal with the diameter of 150-212mm and the length of more than or equal to 400mm. The method solves the problems of uneven radial thermal field and the like in the prior art, the crystal does not have indium-rich and phosphorus-rich areas, holes or cracks, the impurity content is less than or equal to 1.0 * 10 <-6 > level, the productivity per unit volume is improved by 4 times, the one-time synthesis amount reaches 15kg or above, the energy consumption is reduced by 15% or above, the cost is reduced by 30% or above, and the method is suitable for industrial production.