82 results about "Polycrystalline silicon thin films" patented technology

Provided in the present disclosure are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises a base and a first polysilicon thin film transistor, wherein the first polysilicon thin film transistor is located on the base; a channel of the first polysilicon thin film transistor comprises a plurality of crystal grains; and in the channel of the first polysilicon thin film transistor, the length of the crystal grains in a first direction is greater than the length thereof in a second direction, the first direction being the length direction of a channel region, and the second direction being the width direction of the channel region. Thus, the present disclosure helps to improve the resolution and refresh rate of a display panel, thereby optimizing a display effect and improving the user experience.

A surface composite film structure with longitudinal transmission cutoff and transverse transmission conduction, and a preparation method and application thereof are provided. The surface composite film structure includes a nano dielectric layer arranged on a surface of a silicon substrate, a silicide layer arranged on the nano dielectric layer and a polycrystalline silicon layer arranged on the silicide layer. A material of the nano dielectric layer is a hydrogenated silicon oxide film, a material of the silicide layer is a hydrogenated carbon nitride silicon film including phosphorus or boron, and a material of the polycrystalline silicon layer is a phosphorus-doped or boron-doped polycrystalline silicon film. The surface composite film structure can achieve an excellent passivation effect and has the characteristics of longitudinal non-conduction and transverse conduction, and the transverse sheet resistance is flexibly adjustable, meeting the performance requirements of new silicon-based semiconductor physical devices.

Provided are abrasive grains and a composition for chemical mechanical polishing which are for selectively polishing a silicon nitride film, and which are applicable not only to silicon oxide films but also to amorphous silicon films and polysilicon films. This method for manufacturing abrasive grains includes: a first step of heating a mixture which contains particles having a sulfanyl group (—SH) fixed to the surface thereof via covalent bonds, and which contains a compound having carbon-carbon unsaturated double bonds; and a second step, which is performed after the first step, of further adding a peroxide and carrying out heating.

The invention discloses a polycrystalline silicon thin film deposition method, which comprises the following steps: carrying out film coating operation at a first process temperature in a process chamber of a furnace tube machine, and depositing a first polycrystalline silicon layer on a wafer through an LP CVD process; the steps are repeatedly executed, the thickness of the first polycrystalline silicon layer thin film formed on the surface of the inner wall of the process chamber of the furnace tube machine table in an accumulated mode is increased in the process, and tensile stress is generated; when the preset number of times of coating operation is completed and the furnace tube machine table is in a non-operation state, coating operation is conducted at the second temperature, a second polycrystalline silicon layer is deposited on the first polycrystalline silicon layer on the surface of the inner wall of the process chamber through the LPCVD process, and the second process temperature is different from the first process temperature; and the second polycrystalline silicon layer generates pressure stress opposite to the tensile stress in direction. According to the embodiment of the invention, the probability that the polycrystalline silicon thin film accumulated on the inner wall of the process chamber of the furnace tube machine table falls off due to stress increase can be reduced, so that the operation time of the furnace tube machine table is prolonged, and the reliability of products is improved.

Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a driving circuit layer on the base substrate, a light-emitting structure layer on a side of the driving circuit layer away from the base substrate, and a shield electrode layer on a side of the driving circuit layer proximal to the base substrate. The light-emitting structure layer includes a plurality of light-emitting devices. The driving circuit layer includes a plurality of pixel driving circuits. At least part of transistors in each of the pixel driving circuits are oxide thin film transistors, and at least part of transistors are low-temperature polycrystalline silicon thin film transistors.

Embodiments of the present application provide a semiconductor device and a method of manufacturing the same for implementing both polysilicon TFTs and oxide TFTs with less process complication. The semiconductor device includes first and second thin film transistor structures formed on a substrate. The first TFT structure includes a first transistor and a capacitor on the first transistor, and the second TFT structure includes a bottom metal layer, a second insulating layer on the bottom metal layer, and a second transistor on the second insulating layer. A lower electrode of the capacitor comprises the same metal material as the bottom metal layer, a dielectric layer of the capacitor comprises the same insulator material as the second insulating layer, and the upper electrode of the capacitor comprises the same oxide semiconductor material as a semiconductor active layer of the second transistor.

The application provides a vertical structure thin film transistor and electronic device; the vertical structure thin film transistor can realize a polysilicon thin film transistor with a minimum channel length by stacking a first doped part, a channel part and a second doped part; and the second doped part is arranged in a via of an insulating layer, the second doped part is connected to the channel part through the via and partially contacts the channel part, the contact area of the second doped part and the channel part is reduced, the ions diffused to the channel area are reduced, the device stability of the thin film transistor is improved, the projection area of the thin film transistor is reduced, the aperture ratio of the display panel is improved, and the development of high-resolution and high-refresh-rate products and even the realization of the function of part of chips are facilitated.

The invention discloses an LTPO display panel and a display device. The LTPO display panel comprises a substrate, a buffer layer, a first low-temperature polycrystalline silicon thin film transistor, a second low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor, each of the first low-temperature polycrystalline silicon thin film transistor and the second low-temperature polycrystalline silicon thin film transistor comprises a low-temperature polycrystalline silicon layer, a first gate insulating layer and a first gate layer which are stacked; the first low-temperature polycrystalline silicon thin film transistor and the second low-temperature polycrystalline silicon thin film transistor are covered with a second gate insulating layer, and at least part of the second gate insulating layer is covered with a second gate layer; the oxide thin film transistor is located above the first low-temperature polycrystalline silicon thin film transistor and / or above the second grid electrode layer. The first low-temperature polycrystalline silicon thin film transistor is of a top gate structure and can serve as a barrier layer, hydrogen ions on the low-temperature polycrystalline silicon thin film transistor are prevented from diffusing to a channel region of the oxide thin film transistor, and the stability of the oxide thin film transistor is improved.

The invention discloses a method for improving the compactness of a super back-sealing LTO film, and particularly relates to the technical field of semiconductor manufacturing processes, and the method comprises the following steps: S1, preparing an LTO film; s2, improving the compactness of the LTO film; s3, preparing a polycrystalline silicon thin film; s4, HF acid cleaning and measurement; and S5, obtaining a finished product. According to the method for improving the compactness of the super back-sealed LTO film, APCVD film forming parameters do not need to be modified or independent annealing equipment does not need to be additionally arranged, only the heat preservation time of the LPCVD non-film-forming step is adjusted, the method is seamlessly compatible with an existing AP + LP technology, the technology compatibility is high, performance improvement is achieved within a reasonable time range by setting the optimal heat preservation time to be 30 min, and the method is suitable for large-scale production. By adjusting the optimal heat preservation time of the LPCVD non-film-forming step, the single-batch processing period is prevented from being greatly prolonged, the productivity influence is small, and the compactness of the LTO film is improved to the maximum extent while the single-batch processing period is prevented from being greatly prolonged by adjusting the optimal heat preservation time of the LPCVD non-film-forming step.

The embodiment of the invention provides a semiconductor wafer and a preparation method thereof, the semiconductor wafer comprises a substrate, a polycrystalline silicon layer and a composite buffer layer arranged between the substrate and the polycrystalline silicon layer, the composite buffer layer comprises a first sub-layer used for providing a preset stress, and a second sub-layer used for providing a second stress; the average tensile stress of the polycrystalline silicon layer is at least partially counteracted; and a second sub-layer disposed between the first sub-layer and the polysilicon layer, the second sub-layer having a higher in-plane stiffness than the first sub-layer for dispersing stress generated in the polysilicon layer in a plane parallel to an interface between the first sub-layer and the second sub-layer, and transmitting the dispersed stress to the first sub-layer. Through the function-decoupled composite buffer layer structure, accurate allocation and efficient compensation of non-uniform tensile stress in the polycrystalline silicon thin film are realized, so that the problem of excessive warping of a wafer is fundamentally solved.

The invention relates to the technical field of super-large-scale integrated circuit manufacturing in the semiconductor industry, and particularly provides a low-temperature polycrystalline silicon thin film transistor, a display panel and a preparation method. The method aims at solving the problems that in the prior art, an optimization method for interface defects is still high in process complexity, cost is increased or the effect is limited. Therefore, the invention provides a preparation method of a low-temperature polycrystalline silicon thin film transistor, which comprises the following steps of: forming an amorphous silicon layer on a substrate; forming a silicon oxide layer on the amorphous silicon layer; laser annealing is carried out, so that the amorphous silicon layer is converted into a polycrystalline silicon layer, the polycrystalline silicon layer is used for forming a channel region and an electrode contact region of the low-temperature polycrystalline silicon thin film transistor, and the thickness of the silicon oxide layer is configured to be capable of inhibiting the height of protrusions formed when the amorphous silicon layer is converted into the polycrystalline silicon layer. According to the method, the protruding height of the polycrystalline silicon layer is reduced, the interface defects of polycrystalline silicon and GI are optimized, and the problems of residual images and the like caused by accumulation of the interface defects are solved.

This invention provides a stacked structure for selective contact, a front-side battery structure, and a fabrication method. The stacked structure includes a dielectric layer, a first heavily doped polysilicon layer, and an etch-resistant layer sequentially stacked on the front side of a substrate. A second heavily doped polysilicon layer is disposed on the etch-resistant layer in the region corresponding to the front-side metal electrode. This stacked structure solves the problem of difficult-to-control etching process by adding an etch-resistant layer, thereby enabling a fabrication process that allows for the full deposition of polysilicon thin films, the formation of locally patterned protective regions, and the etching away of the remaining unpatterned polysilicon thin films. This allows for the application of an ultrathin silicon oxide / heavily doped polysilicon structure to the front side of the battery, passivating the contact between the metal electrode and the silicon substrate, avoiding the existence of high recombination regions, reducing carrier recombination, and maintaining carrier collection efficiency, ultimately improving the battery's open-circuit voltage, fill factor, and conversion efficiency.

The application relates to the technical field of pressure sensor manufacturing, in particular to a high-sensitivity silicon-based piezoresistive pressure sensor and a manufacturing method. A double-throw wafer silicon chip is used as a substrate, and an insulating medium layer is grown on the top surface of the substrate; a polysilicon thin film is deposited on the insulating medium layer to form a polysilicon film layer; secondary oxidation is carried out on the polysilicon film layer to form a secondary oxidation layer with a preset thickness; ion implantation is carried out on the polysilicon film layer under vacuum conditions to form a piezoresistive sensitive device layer; the secondary oxidation layer and the polysilicon film layer are etched to form a sensitive device; annealing and rediffusion treatment are carried out on the sensitive device; a second insulating medium layer is deposited on the surface of the annealed and rediffused sensitive device; the second insulating medium layer is etched to form device connection wires; and a pad and a metal wire structure are formed on the top of the device connection wires and in the preset area outside the device connection wires through a photoetching, metal deposition and etching process, so that the problem of weak insulation performance of the silicon-based piezoresistive pressure sensor is solved.

The invention relates to a micro sensor for measuring pressure and temperature in human tissue and a packaging process thereof, a pressure sensor and a temperature sensor are arranged on a carrier plate, and a pressure signal sampling module detects a pressure signal according to the change of resistance values of monocrystalline silicon and polycrystalline silicon film piezoresistors on the pressure sensor; and the temperature signal sampling module is used for detecting a temperature signal according to the change of a resistance value of a thermistor on the temperature sensor. The pressure sensor and the temperature sensor share the grounding wire, so that micro-assembly of the pressure sensor and the temperature sensor on the carrier plate is realized, the convenience of the micro-sensor device is improved, and the packaging volume is reduced.

The application discloses a method for reducing the loss of the key size of polycrystalline silicon caused by photoresist rework, which comprises the following steps: S1, providing a semiconductor device for polycrystalline silicon LEC etching, and the process immediately before polycrystalline silicon film etching has been completed; S2, performing polymer deposition; S3, performing photoresist rework and polycrystalline silicon film etching, and obtaining a device with a polycrystalline silicon key size meeting the process control standard. The application can effectively improve the problem of the reduction of the key size of polycrystalline silicon, improve the product yield and reduce the production cost by increasing the key size of the hard mask through polymer deposition on the semiconductor device immediately before the process of polycrystalline silicon film etching has been completed without changing the pattern of the polycrystalline silicon film.

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device has a source region and a drain region provided on a main surface of a semiconductor substrate, a gate insulating film provided on the main surface between the source region and the drain region, a gate electrode provided on the gate insulating film, and a drain wiring electrically connected to the drain region, the drain wiring includes a first wiring portion electrically connected to the drain region, a second wiring portion, and a polycrystalline silicon film electrically connected between the first wiring portion and the second wiring portion.SELECTED DRAWING: Figure 2

The application discloses a P-type TOPCon cell and a preparation method thereof. The P-type TOPCon cell takes P-type crystalline silicon as a substrate, and the front surface of the P-type TOPCon cell comprises, from inside to outside, a tunneling oxide layer, a phosphorus-doped polysilicon stack and a front composite passivation layer. The phosphorus-doped polysilicon stack comprises, from inside to outside, a first phosphorus-doped polysilicon film, a first silicon oxide film, a second phosphorus-doped polysilicon film, a second silicon oxide film and a third phosphorus-doped polysilicon film. The phosphorus doping concentration and the thickness of the third phosphorus-doped polysilicon film are greater than those of the first phosphorus-doped polysilicon film. The preparation method comprises preparing the tunneling oxide layer, the phosphorus-doped polysilicon stack and the front composite passivation layer on the front surface of the P-type crystalline silicon. The P-type TOPCon cell has the advantages of excellent anti-space radiation capability, high conversion efficiency, long service life and the like. As a novel solar cell with excellent performance, the P-type TOPCon cell can adapt to a harsh space environment and meet the demand of modern spacecraft for high-performance power supplies.

This technology provides a way to easily remove the gettering layer. [Solution] A processing method according to one aspect of the present disclosure comprises: preparing a substrate having a polycrystalline silicon film containing a catalyst metal on its surface; forming a gettering layer on the polycrystalline silicon film; and annealing the substrate to diffuse the catalyst metal contained in the polycrystalline silicon film into the gettering layer, wherein the gettering layer is formed of amorphous silicon germanium containing impurities that enable the diffusion of the catalyst metal into the gettering layer.

The invention relates to the technical field of semiconductor manufacturing, discloses a silicon wafer surface treatment and thin film deposition defect repair method and alkali corrosion equipment, solves the LP pollution defect caused by environmental particulate matters in an LPCVD (Low Pressure Chemical Vapor Deposition) process, and realizes silicon wafer regeneration. The method comprises the following steps: cleaning before corrosion by adopting an ammonia water / hydrogen peroxide mixed solution; carrying out alkali corrosion for 40 seconds by using a potassium hydroxide solution with the concentration of 0.134% at 90 DEG C, and accurately stripping a polluted polycrystalline silicon layer; and after two-stage pure water rinsing and subsequent cleaning, carrying out LPCVD deposition again to form a clean polycrystalline silicon film. The matched alkali corrosion equipment is of a three-groove type structure and comprises a constant temperature control module and a timing module. According to the method, the removal amount of the polycrystalline silicon layer is accurately controlled while LP pollution particles are removed by optimizing cooperative control of three parameters of concentration-temperature-time of the corrosive liquid, secondary pollution is effectively prevented by matching with a dual cleaning process, the repair quality is ensured through film thickness detection and appearance inspection, the yield of the silicon wafer is remarkably improved, and the manufacturing cost is reduced.

A surface composite film structure capable of cut-off longitudinal transport and conducted lateral transport, a preparation method therefor and the use thereof. The surface composite film structure comprises a nano dielectric layer provided on a surface of a silicon substrate, a silicon compound layer provided on the nano dielectric layer, and a polycrystalline silicon layer provided on the silicon compound layer, the material of the nano dielectric layer being a hydrogenated silicon oxide thin film, the material of the silicon compound layer being a phosphorus-containing or boron-containing hydrogenated silicon carbonitride thin film, and the material of the polycrystalline silicon layer being a phosphorus-doped or boron-doped polycrystalline silicon thin film. The surface composite film structure can achieve an excellent passivation effect, has the characteristics of being longitudinally non-conductive and laterally conductive, and has flexible and adjustable lateral sheet resistance, thus satisfying the performance requirements of silicon-based semiconductor physical devices.

The present application provides a method for preparing a composite substrate, a composite substrate, and an electronic component. The method for preparing the composite substrate includes: first preparing a first polysilicon thin film layer on a substrate, and then obtaining a polysilicon seed layer by first annealing to further grow the grains of the first polysilicon thin film layer. Then, continue to prepare a second polysilicon thin film layer on the polysilicon seed layer to improve the influence of the substrate layer on the grains caused by low lattice matching degree, improve the lattice matching degree, reduce the difference in lattice size between the first polysilicon thin film layer and the second polysilicon thin film layer, and improve the resistance uniformity of the polysilicon layer. At the same time, by performing a second annealing treatment on the second polysilicon thin film layer, the degree of reconstruction of polysilicon grains in the subsequent high-temperature process stage can be suppressed, the difference in polysilicon lattice size can be reduced, and a polysilicon layer with large and uniformly distributed grain sizes near the substrate layer and the insulating layer can be obtained.

The present invention discloses a PECVD device for field-effect passivation of crystalline silicon cells, relating to the technical field of crystalline silicon photovoltaic cell production. The polycrystalline silicon (Poly-Si) thin film structure comprises two low-concentration doped regions and two high-concentration doped regions, which are stacked layer by layer. By stacking the low-concentration doped regions and the high-concentration doped regions layer by layer, the present invention allows free carriers in the high-concentration doped regions to diffuse into the low-concentration doped regions, leaving behind charged fixed ions, thus transforming the high-concentration doped regions into high-net-charge regions. The low-concentration doped regions have high crystallinity and high carrier mobility, and suppress the diffusion of impurity atoms. By providing the high-net-charge regions, enhanced field-effect passivation is achieved, thereby improving the efficiency of crystalline silicon photovoltaic cells.

The present invention relates to a thin film transistor circuit and a method for manufacturing the thin film transistor circuit. The polysilicon layer includes a polysilicon portion of a polysilicon thin film transistor. The first conductor layer includes a first gate electrode portion of the polysilicon thin film transistor. The first insulator layer includes a first insulator portion located between the first gate electrode portion and the polysilicon portion. The oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin film transistor. The second conductor layer includes a second gate electrode portion of the oxide semiconductor thin film transistor. The second insulator layer includes a second insulator portion located between the second gate electrode portion and the oxide semiconductor portion. The second insulator layer has a relative dielectric constant of not less than 8. The entire region of the second insulator layer is covered by the second conductor layer.

To provide a semiconductor-on-insulator structure having excellent radiofrequencydeviceperformance, and to provide a method of manufacturing the same.SOLUTION: The method of making the semiconductor-on-insulator composite structure 20 is based on depositing an undoped polycrystalline silicon film 28 on a high resistivity silicon substrate 22 and forming a stack of an oxide (e.g., a buried oxide layer 24) and a top silicon layer 26 on the polycrystalline silicon film 28. The polysilicon layer 28 serves as a high-defectivity layer between the silicon substrate 22 and the buried oxide layer 24.SELECTED DRAWING: Figure 2

The application discloses a method for improving the switching speed of a trench type SICMOSFET device, belongs to the technical field of semiconductor devices, and can form a trench on the surface of a SIC epitaxial layer, grow a gate oxide film on the bottom and sidewall of the trench, deposit a polysilicon thin film on the formed gate oxide film, etch the polysilicon film on the bottom of the trench, deposit Nitride on the polysilicon thin film, etch the Nitride in the trench, grow an oxide layer on the polysilicon from which the Nitride is etched, then remove the remaining Nitride, and deposit a layer of polysilicon on the basis to form a new device structure method for reducing Cgd, so that the technical effects of avoiding excessive Cgd, reducing the switching speed of the device and reducing the loss of the device are achieved.

To provide an etching method and an etching apparatus capable of enhancing a selective ratio of a silicon nitride film over a silicon oxide film or a polysilicon film.SOLUTION: An etching method is a method for selectively etching a first silicon film S1 of a substrate S including the first silicon film S1 and a second silicon film S2. The etching method includes: supplying a hydrogen fluoride gas to the substrate S while heating the substrate S so as to maintain a temperature of the substrate S at a predetermined temperature included in a range of a first temperature or higher and a second temperature or lower; and supplying an activated radical generated from a gas for radical generation to an etching target while heating the substrate S so as to maintain the temperature of the substrate S after the supply of the hydrogen fluoride gas at the predetermined temperature.SELECTED DRAWING: Figure 4

The invention discloses a method for forming a polycrystalline silicon thin film of a super junction device, which comprises the following steps: a first polycrystalline silicon layer is formed on an oxide layer, gas introduced in the process of forming the first polycrystalline silicon layer comprises silane and phosphorane, the oxide layer is formed on a wafer, and the wafer is used for forming the super junction device; and forming a second polycrystalline silicon layer on the first polycrystalline silicon layer, wherein the introduced gas in the process of forming the second polycrystalline silicon layer comprises silane, and phosphine is not introduced. In the manufacturing process of the super junction device, after the oxide layer is formed on the wafer, the first polycrystalline silicon layer with relatively high phosphorus doping concentration is formed on the oxide layer, and then the second polycrystalline silicon layer with relatively low phosphorus doping concentration is formed on the first polycrystalline silicon layer, so that the polycrystalline silicon thin film with relatively low surface phosphorus concentration and relatively high lower layer phosphorus concentration is formed; and the square resistance is reduced on the premise of keeping the thickness of the polycrystalline silicon thin film.

This application provides a method for fabricating a semiconductor device and the semiconductor device itself. The method includes: providing a memory array structure; forming an amorphous silicon thin film on the surface of the memory array structure; forming a capping layer on the surface of the amorphous silicon thin film away from the memory array structure; and annealing the memory array structure with the capping layer to convert the amorphous silicon thin film into a polycrystalline silicon thin film. This method ensures that the obtained polycrystalline silicon thin film has good uniformity and flatness.

The invention provides a display device of a hybrid thin film transistor, which belongs to the technical field of display, and comprises a plurality of thin film transistors formed on the same semiconductor substrate, the thin film transistors comprise a first thin film transistor and a second thin film transistor, the first thin film transistor is a low-temperature polycrystalline silicon thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor. The second thin film transistor is an oxide semiconductor thin film transistor; the shielding layer is located below the active layer of the first thin film transistor and on the projection perpendicular to the semiconductor substrate, and the shielding layer at least partially covers the active layer of the first thin film transistor and completely covers the channel region of the first thin film transistor; and the shading layer is located below the active layer of the second thin film transistor and on the projection perpendicular to the semiconductor substrate, and the shading layer at least completely covers the active layer of the second thin film transistor. The invention has the beneficial effects that the advantages of the low-temperature polycrystalline silicon thin film transistor and the oxide semiconductor thin film transistor are fully combined, the display effect is ensured while low power consumption is realized, and the device reliability is improved.

To provide a semiconductor device capable of preventing a contact barrier metal film from peeling off from the trench gate lead-out electrode. In the gate wiring lead-out region MGR defined on a semiconductor substrate, a convex portion is formed on the trench gate lead-out electrode TGI, extending towards a gate lead-out contact member. The convex portion is formed by a natural oxidation film and a polysilicon film PSF. The gate lead-out contact member is formed to cover the convex portion by interposing the contact barrier metal film.