111 results about "Polycrystalline silicon thin films" patented technology

Display baseplates, display panels and display apparatuses are provided. A display baseplate includes a substrate, a polycrystalline silicon thin film transistor structure layer located on the substrate, an insulation layer located at a side of the polycrystalline silicon thin film transistor structure layer away from the substrate, an oxide thin film transistor structure layer located at a side of the insulation layer away from the substrate, and a plurality of sub-pixels located on the substrate, at least one of the sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element and including a polycrystalline silicon active layer located on the polycrystalline silicon thin film transistor structure layer and an oxide semiconductor active layer located on the oxide thin film transistor structure layer; orthographic projections of both the polycrystalline silicon active layer and the oxide semiconductor active layer on the substrate are at least partially overlapped.

The invention discloses a POI substrate and a preparation method and application thereof, and belongs to the technical field of semiconductor preparation. The preparation method of the POI substrate comprises the following steps: S1, placing a supporting layer in a chemical vapor deposition furnace, filling a silane atmosphere, reacting at 580-650 DEG C for 30-120 minutes, growing a polycrystalline silicon thin film, and polishing the polycrystalline silicon thin film; s2, putting the supporting layer on which the polycrystalline silicon is deposited in the step S1 into spatial PEALD for deposition circulation, growing a SiO2 thin film at 60-120 DEG C, then performing annealing treatment, and then polishing the SiO2 thin film; s3, performing ion implantation on the functional layer; and S4, bonding the supporting layer on which the polycrystalline silicon and the SiO2 are deposited in the step S2 with the functional layer on which the ions are injected in the step S3, then performing annealing treatment, and then performing chemical mechanical polishing to obtain the POI substrate. The POI substrate is good in film-forming property and uniformity and good in compactness, and can be used for manufacturing a surface acoustic wave filter with excellent temperature stability and high-power processing.

The invention discloses a crystalline silicon photovoltaic cell with a novel tunneling passivation layer and production equipment of the crystalline silicon photovoltaic cell, and relates to the technical field of crystalline silicon photovoltaic cells. The gel film is prepared by adopting a sol-gel method, the carbon-doped silicon oxide film is prepared by adopting a gel film thermal oxidation method, and the carbon-doped silicon oxide film is clamped between the crystalline silicon substrate and the doped polycrystalline silicon film to serve as a junction region tunneling passivation layer, so that the performance of the crystalline silicon photovoltaic cell is improved. Through a unique stirring structure and a scraping cleaning function, the mixing effect of sol and the cleanliness of equipment are improved, and effective technical support is provided for production of crystalline silicon photovoltaic cells. The stirring equipment comprises a stirring kettle, a power structure is installed at the top of the stirring kettle, power is provided through a power part, a reciprocating part and a rotating part are matched to drive a stirring part in the stirring structure to slide up and down and rotate and stir in the stirring kettle, and mixing and stirring of various kinds of sol are achieved. A stirring rod capable of adjusting the stirring range is arranged in the stirring structure, and the stirring rod is subjected to abutting adjustment through a bottom rod in the upper adjusting part, so that the inner side wall of the stirring kettle is scraped and cleaned.

Provided in the present disclosure are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises a base and a first polysilicon thin film transistor, wherein the first polysilicon thin film transistor is located on the base; a channel of the first polysilicon thin film transistor comprises a plurality of crystal grains; and in the channel of the first polysilicon thin film transistor, the length of the crystal grains in a first direction is greater than the length thereof in a second direction, the first direction being the length direction of a channel region, and the second direction being the width direction of the channel region. Thus, the present disclosure helps to improve the resolution and refresh rate of a display panel, thereby optimizing a display effect and improving the user experience.

A surface composite film structure with longitudinal transmission cutoff and transverse transmission conduction, and a preparation method and application thereof are provided. The surface composite film structure includes a nano dielectric layer arranged on a surface of a silicon substrate, a silicide layer arranged on the nano dielectric layer and a polycrystalline silicon layer arranged on the silicide layer. A material of the nano dielectric layer is a hydrogenated silicon oxide film, a material of the silicide layer is a hydrogenated carbon nitride silicon film including phosphorus or boron, and a material of the polycrystalline silicon layer is a phosphorus-doped or boron-doped polycrystalline silicon film. The surface composite film structure can achieve an excellent passivation effect and has the characteristics of longitudinal non-conduction and transverse conduction, and the transverse sheet resistance is flexibly adjustable, meeting the performance requirements of new silicon-based semiconductor physical devices.

Provided are abrasive grains and a composition for chemical mechanical polishing which are for selectively polishing a silicon nitride film, and which are applicable not only to silicon oxide films but also to amorphous silicon films and polysilicon films. This method for manufacturing abrasive grains includes: a first step of heating a mixture which contains particles having a sulfanyl group (—SH) fixed to the surface thereof via covalent bonds, and which contains a compound having carbon-carbon unsaturated double bonds; and a second step, which is performed after the first step, of further adding a peroxide and carrying out heating.

The invention provides an excimer laser annealing device and a preparation method of a polycrystalline silicon thin film, and the device comprises a substrate carrying platform which is used for carrying a to-be-processed substrate; the laser unit is used for emitting a laser beam to the bearing surface of the substrate bearing table, the laser beam has the extension length in the first direction, and the first direction is parallel to the to-be-processed substrate; the to-be-processed substrate comprises a first side edge and a second side edge which are adjacently arranged, the to-be-processed substrate is arranged on the substrate carrying table in the mode that the first side edge inclines relative to the reference direction, the reference direction is perpendicular to the first direction, and a plane defined by the reference direction and the first direction is parallel to the to-be-processed substrate; the substrate stage is movable relative to the laser beam in a second direction, the second direction being a vector direction inclined relative to both the first direction and the reference direction. According to the excimer laser annealing device and the preparation method of the polycrystalline silicon thin film, the utilization rate of the substrate can be improved.

The invention discloses a polycrystalline silicon thin film deposition method, which comprises the following steps: carrying out film coating operation at a first process temperature in a process chamber of a furnace tube machine, and depositing a first polycrystalline silicon layer on a wafer through an LP CVD process; the steps are repeatedly executed, the thickness of the first polycrystalline silicon layer thin film formed on the surface of the inner wall of the process chamber of the furnace tube machine table in an accumulated mode is increased in the process, and tensile stress is generated; when the preset number of times of coating operation is completed and the furnace tube machine table is in a non-operation state, coating operation is conducted at the second temperature, a second polycrystalline silicon layer is deposited on the first polycrystalline silicon layer on the surface of the inner wall of the process chamber through the LPCVD process, and the second process temperature is different from the first process temperature; and the second polycrystalline silicon layer generates pressure stress opposite to the tensile stress in direction. According to the embodiment of the invention, the probability that the polycrystalline silicon thin film accumulated on the inner wall of the process chamber of the furnace tube machine table falls off due to stress increase can be reduced, so that the operation time of the furnace tube machine table is prolonged, and the reliability of products is improved.

Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a driving circuit layer on the base substrate, a light-emitting structure layer on a side of the driving circuit layer away from the base substrate, and a shield electrode layer on a side of the driving circuit layer proximal to the base substrate. The light-emitting structure layer includes a plurality of light-emitting devices. The driving circuit layer includes a plurality of pixel driving circuits. At least part of transistors in each of the pixel driving circuits are oxide thin film transistors, and at least part of transistors are low-temperature polycrystalline silicon thin film transistors.

The present invention provides a method for manufacturing an array substrate, an array substrate, and a display panel. The array substrate includes a substrate and metal oxide thin film transistors and polysilicon thin film transistors located on the substrate. The metal oxide thin film transistors and the polysilicon thin film transistors are arranged at intervals. The metal oxide thin film transistors are located in a first region and are used to drive pixel electrodes, and the polysilicon thin film transistors are located in a second region and are used to control the metal oxide thin film transistors. The method for manufacturing an array substrate, the array substrate, and the display panel provided by the embodiments of the present invention simultaneously adopt polysilicon thin film transistors and metal oxide thin film transistors, are designed in regions, are compatible in process, effectively solve the technical bottleneck of polysilicon thin film transistors, enable them to be applied to large-size display panels, and can effectively reduce the power consumption of the display panel.

Embodiments of the present application provide a semiconductor device and a method of manufacturing the same for implementing both polysilicon TFTs and oxide TFTs with less process complication. The semiconductor device includes first and second thin film transistor structures formed on a substrate. The first TFT structure includes a first transistor and a capacitor on the first transistor, and the second TFT structure includes a bottom metal layer, a second insulating layer on the bottom metal layer, and a second transistor on the second insulating layer. A lower electrode of the capacitor comprises the same metal material as the bottom metal layer, a dielectric layer of the capacitor comprises the same insulator material as the second insulating layer, and the upper electrode of the capacitor comprises the same oxide semiconductor material as a semiconductor active layer of the second transistor.

The application provides a vertical structure thin film transistor and electronic device; the vertical structure thin film transistor can realize a polysilicon thin film transistor with a minimum channel length by stacking a first doped part, a channel part and a second doped part; and the second doped part is arranged in a via of an insulating layer, the second doped part is connected to the channel part through the via and partially contacts the channel part, the contact area of the second doped part and the channel part is reduced, the ions diffused to the channel area are reduced, the device stability of the thin film transistor is improved, the projection area of the thin film transistor is reduced, the aperture ratio of the display panel is improved, and the development of high-resolution and high-refresh-rate products and even the realization of the function of part of chips are facilitated.

The invention discloses an LTPO display panel and a display device. The LTPO display panel comprises a substrate, a buffer layer, a first low-temperature polycrystalline silicon thin film transistor, a second low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor, each of the first low-temperature polycrystalline silicon thin film transistor and the second low-temperature polycrystalline silicon thin film transistor comprises a low-temperature polycrystalline silicon layer, a first gate insulating layer and a first gate layer which are stacked; the first low-temperature polycrystalline silicon thin film transistor and the second low-temperature polycrystalline silicon thin film transistor are covered with a second gate insulating layer, and at least part of the second gate insulating layer is covered with a second gate layer; the oxide thin film transistor is located above the first low-temperature polycrystalline silicon thin film transistor and / or above the second grid electrode layer. The first low-temperature polycrystalline silicon thin film transistor is of a top gate structure and can serve as a barrier layer, hydrogen ions on the low-temperature polycrystalline silicon thin film transistor are prevented from diffusing to a channel region of the oxide thin film transistor, and the stability of the oxide thin film transistor is improved.

The invention discloses a method for improving the compactness of a super back-sealing LTO film, and particularly relates to the technical field of semiconductor manufacturing processes, and the method comprises the following steps: S1, preparing an LTO film; s2, improving the compactness of the LTO film; s3, preparing a polycrystalline silicon thin film; s4, HF acid cleaning and measurement; and S5, obtaining a finished product. According to the method for improving the compactness of the super back-sealed LTO film, APCVD film forming parameters do not need to be modified or independent annealing equipment does not need to be additionally arranged, only the heat preservation time of the LPCVD non-film-forming step is adjusted, the method is seamlessly compatible with an existing AP + LP technology, the technology compatibility is high, performance improvement is achieved within a reasonable time range by setting the optimal heat preservation time to be 30 min, and the method is suitable for large-scale production. By adjusting the optimal heat preservation time of the LPCVD non-film-forming step, the single-batch processing period is prevented from being greatly prolonged, the productivity influence is small, and the compactness of the LTO film is improved to the maximum extent while the single-batch processing period is prevented from being greatly prolonged by adjusting the optimal heat preservation time of the LPCVD non-film-forming step.

The invention discloses a low-noise soft cable, which belongs to the field of cable technology, and comprises a conductor, an insulating layer, a braided shielding layer and a sheath layer arranged in sequence from the inside to the outside, wherein the conductor is formed by twisting copper wires, the insulating layer is coated on the outer wall of the conductor by wrapping and sintering, the surface of the insulating layer is coated with semi-conductive glue, the braided shielding layer is coated on the outside of the insulating layer and adhered to the outer wall of the insulating layer through the semi-conductive glue, and the sheath layer is coated on the outside of the braided shielding layer. The invention adopts a polytetrafluoroethylene film as an insulating layer, adopts a semi-insulating polycrystalline silicon material as a semi-conductive glue, and forms a semi-insulating polycrystalline silicon film after solidification, so as to achieve the effect of reducing noise; by adding magnesium hydroxide and a flame retardant to the outer sheath material, the sheath material is given a stable and lasting flame retardant effect; so that the obtained cable can simultaneously meet the requirements of low noise and fire retardancy, and has a wide range of application prospects.

The embodiment of the invention provides a semiconductor wafer and a preparation method thereof, the semiconductor wafer comprises a substrate, a polycrystalline silicon layer and a composite buffer layer arranged between the substrate and the polycrystalline silicon layer, the composite buffer layer comprises a first sub-layer used for providing a preset stress, and a second sub-layer used for providing a second stress; the average tensile stress of the polycrystalline silicon layer is at least partially counteracted; and a second sub-layer disposed between the first sub-layer and the polysilicon layer, the second sub-layer having a higher in-plane stiffness than the first sub-layer for dispersing stress generated in the polysilicon layer in a plane parallel to an interface between the first sub-layer and the second sub-layer, and transmitting the dispersed stress to the first sub-layer. Through the function-decoupled composite buffer layer structure, accurate allocation and efficient compensation of non-uniform tensile stress in the polycrystalline silicon thin film are realized, so that the problem of excessive warping of a wafer is fundamentally solved.

The invention relates to the technical field of super-large-scale integrated circuit manufacturing in the semiconductor industry, and particularly provides a low-temperature polycrystalline silicon thin film transistor, a display panel and a preparation method. The method aims at solving the problems that in the prior art, an optimization method for interface defects is still high in process complexity, cost is increased or the effect is limited. Therefore, the invention provides a preparation method of a low-temperature polycrystalline silicon thin film transistor, which comprises the following steps of: forming an amorphous silicon layer on a substrate; forming a silicon oxide layer on the amorphous silicon layer; laser annealing is carried out, so that the amorphous silicon layer is converted into a polycrystalline silicon layer, the polycrystalline silicon layer is used for forming a channel region and an electrode contact region of the low-temperature polycrystalline silicon thin film transistor, and the thickness of the silicon oxide layer is configured to be capable of inhibiting the height of protrusions formed when the amorphous silicon layer is converted into the polycrystalline silicon layer. According to the method, the protruding height of the polycrystalline silicon layer is reduced, the interface defects of polycrystalline silicon and GI are optimized, and the problems of residual images and the like caused by accumulation of the interface defects are solved.

This invention provides a stacked structure for selective contact, a front-side battery structure, and a fabrication method. The stacked structure includes a dielectric layer, a first heavily doped polysilicon layer, and an etch-resistant layer sequentially stacked on the front side of a substrate. A second heavily doped polysilicon layer is disposed on the etch-resistant layer in the region corresponding to the front-side metal electrode. This stacked structure solves the problem of difficult-to-control etching process by adding an etch-resistant layer, thereby enabling a fabrication process that allows for the full deposition of polysilicon thin films, the formation of locally patterned protective regions, and the etching away of the remaining unpatterned polysilicon thin films. This allows for the application of an ultrathin silicon oxide / heavily doped polysilicon structure to the front side of the battery, passivating the contact between the metal electrode and the silicon substrate, avoiding the existence of high recombination regions, reducing carrier recombination, and maintaining carrier collection efficiency, ultimately improving the battery's open-circuit voltage, fill factor, and conversion efficiency.

The application relates to the technical field of pressure sensor manufacturing, in particular to a high-sensitivity silicon-based piezoresistive pressure sensor and a manufacturing method. A double-throw wafer silicon chip is used as a substrate, and an insulating medium layer is grown on the top surface of the substrate; a polysilicon thin film is deposited on the insulating medium layer to form a polysilicon film layer; secondary oxidation is carried out on the polysilicon film layer to form a secondary oxidation layer with a preset thickness; ion implantation is carried out on the polysilicon film layer under vacuum conditions to form a piezoresistive sensitive device layer; the secondary oxidation layer and the polysilicon film layer are etched to form a sensitive device; annealing and rediffusion treatment are carried out on the sensitive device; a second insulating medium layer is deposited on the surface of the annealed and rediffused sensitive device; the second insulating medium layer is etched to form device connection wires; and a pad and a metal wire structure are formed on the top of the device connection wires and in the preset area outside the device connection wires through a photoetching, metal deposition and etching process, so that the problem of weak insulation performance of the silicon-based piezoresistive pressure sensor is solved.

The invention relates to a micro sensor for measuring pressure and temperature in human tissue and a packaging process thereof, a pressure sensor and a temperature sensor are arranged on a carrier plate, and a pressure signal sampling module detects a pressure signal according to the change of resistance values of monocrystalline silicon and polycrystalline silicon film piezoresistors on the pressure sensor; and the temperature signal sampling module is used for detecting a temperature signal according to the change of a resistance value of a thermistor on the temperature sensor. The pressure sensor and the temperature sensor share the grounding wire, so that micro-assembly of the pressure sensor and the temperature sensor on the carrier plate is realized, the convenience of the micro-sensor device is improved, and the packaging volume is reduced.

The application discloses a method for reducing the loss of the key size of polycrystalline silicon caused by photoresist rework, which comprises the following steps: S1, providing a semiconductor device for polycrystalline silicon LEC etching, and the process immediately before polycrystalline silicon film etching has been completed; S2, performing polymer deposition; S3, performing photoresist rework and polycrystalline silicon film etching, and obtaining a device with a polycrystalline silicon key size meeting the process control standard. The application can effectively improve the problem of the reduction of the key size of polycrystalline silicon, improve the product yield and reduce the production cost by increasing the key size of the hard mask through polymer deposition on the semiconductor device immediately before the process of polycrystalline silicon film etching has been completed without changing the pattern of the polycrystalline silicon film.

A resonant pressure sensor includes a silicon wafer, a film part, a resonant part, a resonant part fixing point, a back hole, a cap, a getter layer, a supporting silicon layer, a buried oxide layer, a top silicon film, and a polysilicon film and an oxide film alternately deposited film; the SOI wafer is composed of a top silicon film, a buried oxide layer and a supporting silicon layer; a silicon wafer or an SOI wafer is used as a substrate to form the film part of the resonant pressure sensor, or a top silicon film, a polysilicon film and an oxide film are alternately deposited on the SOI wafer substrate to form the film part of the resonant pressure sensor. A manufacturing process for a resonant pressure sensor, the resonant part is realized by depositing an epitaxial / polysilicon layer, and the substrate is formed by an etching process to form a channel for fluid to enter the film - the back hole of the resonant pressure sensor. The advantages of the present invention are: compact overall structure, high precision, simple manufacturing process, easy control, and a wide range of product applications.

The invention relates to a low-temperature polycrystalline silicon thin film transistor, a manufacturing method of the low-temperature polycrystalline silicon thin film transistor, a display panel and a display device. The manufacturing method of the low-temperature polycrystalline silicon thin film transistor comprises the following steps: sequentially forming an active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer on a buffer layer; forming a via hole which sequentially penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer to expose the active material layer; and heavy doping is carried out on the active material layer and the area corresponding to the via hole, then activating treatment is carried out, and the doping concentration is gradually reduced from the self-weight doped area to the periphery after activating treatment, so that an active layer is formed. The manufacturing method of the low-temperature polycrystalline silicon thin film transistor is simple in process, the LDD structure of the thin film transistor can be formed on the premise that Mask and process complexity are not increased by moving a source and drain electrode heavy doping process and activating treatment backwards, and the purpose of reducing electric leakage of a device is achieved.

The invention relates to a method for manufacturing a polycrystalline silicon resistor with U-shaped resistivity temperature characteristics, which comprises the following steps of: 1, depositing a polycrystalline silicon thin film (3) on a silicon oxide layer of a silicon substrate (1) by adopting an LPCVD (Low Pressure Chemical Vapor Deposition) process, 2, depositing a TEOS (Tetraethyl Orthosilicate) dielectric layer (4) on the polycrystalline silicon thin film (3), and carrying out RTA (Rapid Thermal Annealing); recrystallizing the polycrystalline silicon by adopting furnace tube process high-temperature annealing; 3, photoetching and injecting boron impurities to form a P-type polycrystalline silicon resistor (3-1); 4, photoetching a P-type polycrystalline silicon resistor pattern (3-1); and 5, depositing a dielectric layer (7) on the silicon oxide layer and the P-type polycrystalline silicon resistor. According to the polycrystalline silicon resistor prepared by the invention, the resistivity has a U-shaped characteristic along with the change of the temperature in the temperature range of-55 DEG C to + 125 DEG C, the transition temperature is about room temperature 25 DEG C, and the resistivity temperature coefficient in the temperature range of-55 DEG C to + 125 DEG C is 3.18 ppm / DEG C and is close to 0ppm / DEG C.

The invention relates to a preparation method of a mask dustproof system for extreme ultraviolet lithography. The preparation method comprises the following steps: preparing a ceramic frame; preparing an organic fluorine polymer film, and testing the uniformity; bonding the ceramic frame and the organic fluorine polymer film; depositing a catalyst on the surface of the organic fluorine polymer film; forming the graphene carbon nanotube composite film; the graphene carbon nanotube composite film is thinned; a high-temperature-resistant rubber buffer layer is adhered to the lower end of the ceramic frame; and testing the strength and the air tightness. Compared with a traditional method, the method for preparing the large-area thin film with the uniform thickness is simple, the carbon nanotube film with the thickness of 8-15 nm does not need to be operated, film damage is avoided, and the rate of finished products is high. The light transmittance of the mask dustproof system prepared by the invention is more than 90% under the irradiation of ultraviolet light with the wavelength of 13.5 nm. Compared with traditional nitrocellulose, organic fluororesin and polycrystalline silicon thin films, the light transmittance is higher, and imaging of a mask system is clearer.

The invention relates to the technical field of semiconductor manufacturing, and discloses a preparation method of a polycrystalline silicon thin film with uniform stress distribution. The method comprises the following steps: providing a substrate, and depositing a polycrystalline silicon film on the surface of the substrate by adopting an LPCVD (Low Pressure Chemical Vapor Deposition) process; detecting and acquiring the stress distribution condition of the polycrystalline silicon thin film; injecting a set material on the surface of the polycrystalline silicon thin film according to the stress distribution condition, wherein the material of the polycrystalline silicon thin film comprises the set material; and annealing the polycrystalline silicon thin film through an annealing process. Some polycrystalline silicon films contain phosphorus or boron, and the higher the doping concentration of the phosphorus or the boron is, the smaller the stress under the same condition is, so that the set material is injected into the surfaces of the polycrystalline silicon films according to the stress distribution condition, and the set material can be phosphorus or boron or other materials capable of influencing the stress; the problem that in the prior art, stress distribution of a polycrystalline silicon thin film is not uniform is solved.

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device has a source region and a drain region provided on a main surface of a semiconductor substrate, a gate insulating film provided on the main surface between the source region and the drain region, a gate electrode provided on the gate insulating film, and a drain wiring electrically connected to the drain region, the drain wiring includes a first wiring portion electrically connected to the drain region, a second wiring portion, and a polycrystalline silicon film electrically connected between the first wiring portion and the second wiring portion.SELECTED DRAWING: Figure 2

The application discloses a P-type TOPCon cell and a preparation method thereof. The P-type TOPCon cell takes P-type crystalline silicon as a substrate, and the front surface of the P-type TOPCon cell comprises, from inside to outside, a tunneling oxide layer, a phosphorus-doped polysilicon stack and a front composite passivation layer. The phosphorus-doped polysilicon stack comprises, from inside to outside, a first phosphorus-doped polysilicon film, a first silicon oxide film, a second phosphorus-doped polysilicon film, a second silicon oxide film and a third phosphorus-doped polysilicon film. The phosphorus doping concentration and the thickness of the third phosphorus-doped polysilicon film are greater than those of the first phosphorus-doped polysilicon film. The preparation method comprises preparing the tunneling oxide layer, the phosphorus-doped polysilicon stack and the front composite passivation layer on the front surface of the P-type crystalline silicon. The P-type TOPCon cell has the advantages of excellent anti-space radiation capability, high conversion efficiency, long service life and the like. As a novel solar cell with excellent performance, the P-type TOPCon cell can adapt to a harsh space environment and meet the demand of modern spacecraft for high-performance power supplies.

This technology provides a way to easily remove the gettering layer. [Solution] A processing method according to one aspect of the present disclosure comprises: preparing a substrate having a polycrystalline silicon film containing a catalyst metal on its surface; forming a gettering layer on the polycrystalline silicon film; and annealing the substrate to diffuse the catalyst metal contained in the polycrystalline silicon film into the gettering layer, wherein the gettering layer is formed of amorphous silicon germanium containing impurities that enable the diffusion of the catalyst metal into the gettering layer.

The utility model discloses an N-type TOPCon single-sided cell, which relates to the technical field of solar cells and comprises a placement box, a polycrystalline silicon layer is arranged on the bottom surface of the inner wall of the placement box, and a p-type emitter is adhered to the upper side of the polycrystalline silicon layer. According to the utility model, the polycrystalline silicon layer is made of the N-type polycrystalline silicon film and the protective layer made of the silicon nitride material, so that the uniformity of the doped polycrystalline silicon layer can be greatly improved, the overall process time is further shortened, the doped polycrystalline silicon layer is protected, the conversion efficiency of the TOPCon battery is improved, and the passivation layer made of the eva adhesive film material has high transparency and high adhesive force, so that the production efficiency of the TOPCon battery is improved. The protective layer made of the silicon nitride material has the characteristics of high hardness, lubricity, wear resistance, atomic crystal, oxidation resistance at high temperature, cold and hot impact resistance, and no fragmentation after being heated to 1000 DEG C in air; and the hardness and the service life of the battery can be ensured.