822 results about "Crystalline semiconductor" patented technology

A nanostructured composite material comprising semiconductor nanocrystals in a crystalline semiconductor matrix. Suitable nanocrystals include silicon, germanium, and silicon-germanium alloys, and lead salts such as PbS, PbSe, and PbTe. Suitable crystalline semiconductor matrix materials include Si and silicon-germanium alloys. A process for making the nanostructured composite materials. Devices comprising nanostructured composite materials.

A photovoltaic device comprising a photovoltaic cell is provided. The photovoltaic cell includes an emitter layer comprising a crystalline semiconductor material and a lightly doped crystalline substrate disposed adjacent the emitter layer. The lightly doped crystalline substrate and the emitter layer are oppositely doped. Further, the photovoltaic device includes a back surface passivated structure coupled to the photovoltaic cell. The structure includes a highly doped back surface field layer disposed adjacent the lightly doped crystalline substrate. The highly doped back surface field layer includes an amorphous or a microcrystalline semiconductor material, wherein the highly doped back surface field layer and the lightly doped crystalline substrate are similarly doped, and wherein a doping level of the highly doped back surface field layer is higher than a doping level of the lightly doped crystalline substrate. Additionally, the structure may also include an intrinsic back surface passivated layer disposed adjacent the lightly doped crystalline substrate, where the intrinsic back surface passivated layer includes an amorphous or a microcrystalline semiconductor material.

A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.

A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer.

A method of fabricating a three-dimensional semiconductor device is provided along with a three-dimensional semiconductor device fabricated thereby. The method includes forming a heat conductive plug to channel heat away from devices on a substrate, while high temperature processes are performed on a stacked semiconductor layer. The ability to use high temperature processes on the stacked semiconductor layer without adversely effecting devices on the substrate allows the formation of a high quality single-crystalline stacked semiconductor layer. The high quality single-crystalline semiconductor layer can then be used to fabricate improved thin film transistors.

Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.

A manufacturing method of a display device having TFTs capable of high-speed operation with few variations of threshold voltage is provided, in which materials are used with high efficiency and a small number of photomasks is required. The display device of the invention comprises a gate electrode layer and a pixel electrode layer formed over an insulating surface, a gate insulating layer formed over the gate electrode layer, a crystalline semiconductor layer formed over the gate insulating layer, a semiconductor layer having one conductivity type formed in contact with the crystalline semiconductor layer, a source electrode layer and a drain electrode layer formed in contact with the semiconductor layer having one conductivity type, an insulating later formed over the source electrode layer, the drain electrode layer, and the pixel electrode layer, a first opening formed in the insulating layer to reach the source electrode layer or the drain electrode layer, a second opening formed in the gate insulating layer and the insulating layer to reach the pixel electrode layer, and a wiring layer formed in the first opening and the second opening to electrically connect the source electrode layer or the drain electrode layer to the pixel electrode layer.

To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.

A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound.

A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.

A photo-electric conversion array is formed by connecting photo-electric conversion cells in series. Each photo-electric conversion cell includes: a substrate, at least one main surface of which is made of a conductor layer; plural crystalline semiconductor particles provided on the conductor surface of the substrate; an insulation layer filled in clearances among the crystalline semiconductor particles; a transparent electric conducting layer provided above the plural crystalline semiconductor particles; a collector electrode, formed on the transparent electric conducting layer, to collect electricity from the transparent electric conducting layer. The substrate is provided with a substrate electrode portion at one end portion, through which the conductor surface of the substrate is exposed, and a connection electrode is formed by extending the collector electrode, so that the connection electrode in a given photo-electric conversion cell is connected to the substrate electrode portion in another photo-electric conversion cell. It is thus possible to provide a photo-electric conversion array capable of maintaining the reliability as to the adhesion strength, with a good outward appearance as well as excellent reliability and power generation efficiency.

A crystalline semiconductor film in which the position and size of a crystal grain is controlled is fabricated, and the crystalline semiconductor film is used for a channel formation region of a TFT, so that a high performance TFT is realized. An island-like semiconductor layer is made to have a temperature distribution, and a region where temperature change is gentle is provided to control the nucleus generation speed and nucleus generation density, so that the crystal grain is enlarged. In a region where an island-like semiconductor layer 1003 overlaps with a base film 1002, a thick portion is formed in the base film 1002. The volume of this portion increases and heat capacity becomes large, so that a cycle of temperature change by irradiation of a pulse laser beam to the island-like semiconductor layer becomes gentle (as compared with other thin portion). Like this, a laser beam is irradiated from the front side and reverse side of the substrate to directly heat the semiconductor layer, and heat conduction from the semiconductor layer to the side of the substrate and heat conduction of the semiconductor layer in the horizontal direction to the substrate are used, so that the increase in the size of the crystal grain is realized.