41 results about "Crystalline semiconductor" patented technology

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

A semiconductor structure includes a substrate, two or more nanosheet channel layers disposed over a first portion of the substrate, and a source / drain region disposed over a second portion of the substrate adjacent the first portion of the substrate. The source / drain region is a crystalline semiconductor material which transfers a longitudinal stress to the two or more nanosheet channel layers.

A semiconductor memory device includes: a stacked body including conductive and insulating layers that are alternately stacked in a first direction; memory pillars extending in the first direction in the stacked body; and a structure body segmenting the memory pillars and extending in the first direction in the stacked body. The structure body includes a crystalline conductor extending in the first direction in the stacked body, a first insulating film between the stacked body and the crystalline conductor, a crystalline semiconductor film between the crystalline conductor and the first insulating film, and a second insulating film between the crystalline semiconductor film and a side surface of the crystalline conductor. The crystalline conductor includes a first crystal region in contact with the crystalline semiconductor film and containing germanium, and a second crystal region on the first crystal region and in contact with the second insulating film in a second direction.

The present disclosure relates to a unidirectional transient voltage suppression device, comprising: a single crystalline semiconductor substrate doped with a first conductivity type and comprising a first opposite surface and a second opposite surface; a semiconductor region doped with a second conductivity type opposite the first conductivity type extending into the substrate from the first surface; a first conductive electrode in contact with the semiconductor region on a first side; and a second conductive electrode in contact with the substrate on a second side; a first interface forming a junction of a TVS diode between the substrate and the semiconductor region; and a second interface forming a junction of a Schottky diode between the first conductive electrode and the semiconductor region or between the substrate and the second conductive electrode.

A semiconductor storage device having high reliability is provided. The semiconductor storage device includes: a laminate having conductive layers and insulating layers alternately laminated in a first direction; a plurality of memory pillars extending in the first direction within the laminate; and a structure body partitioning the plurality of memory pillars and extending in the first direction within the laminate. The structure body includes: a crystalline conductor extending in the first direction within the laminate; a first insulating film provided between the laminate and the crystalline conductor; a crystalline semiconductor film provided between the crystalline conductor and the first insulating film and containing silicon; and a second insulating film provided between the crystalline semiconductor film and a side surface of the crystalline conductor and containing silicon and oxygen. The crystalline conductor includes: a first crystalline region in contact with the crystalline semiconductor film and containing germanium; and a second crystalline region provided on the first crystalline region and in contact with the second insulating film in a second direction perpendicular to the first direction.

The application discloses a high-crystalline semiconductor silicon carbide powder and a preparation method thereof. High-purity silicon carbide single crystal is cracked or broken, and silicon carbide powder with a particle size of 10-200 microns is screened out and mixed with high-purity carbon powder. The mixed carbon powder and silicon powder are placed at the bottom of a graphite crucible, and the mixed silicon carbide powder and high-purity carbon powder are placed at the upper part. A graphite cover is installed to seal the graphite crucible, and the graphite crucible is placed in a high-temperature sintering furnace. The furnace chamber is closed and vacuumized. The temperature is raised to 1050-1350 DEG C, and the temperature is kept for 1-15 hours. High-purity argon is introduced into the chamber until the pressure in the chamber reaches 10000-80000 Pa. The temperature is continuously raised to 1750-2000 DEG C, and the temperature is kept for 8-15 hours to synthesize the bottom silicon carbide powder. The temperature is continuously raised to 2000-2500 DEG C, and the pressure in the chamber is reduced to 1000-10000 Pa. High-purity argon is continuously introduced at a flow rate of 5-800 sccm, and the temperature is kept for 30-80 hours. The argon introduction is stopped, and the graphite crucible is cooled to room temperature to obtain the high-crystalline semiconductor silicon carbide powder. The high-crystalline semiconductor silicon carbide powder can be applied to the preparation of the third-generation semiconductor material silicon carbide single crystal material with high performance, low defects and low inclusion density.

The present disclosure relates to a method for manufacturing a semiconductor structure. The method comprises providing a first structure. The first structure comprises a first substrate. The method comprises providing a second structure. The second structure comprises a second substrate and a first device metal layer on and in contact with the second substrate. The second substrate comprises a single crystalline semiconductor material and an implanted hydrogen layer. The method comprises bonding the first structure and the second structure by a bonding layer to form a bonded structure. The method comprises removing a portion of the second substrate from approximately the implanted hydrogen layer to form a first semiconductor layer. The method comprises patterning the first semiconductor layer. The method comprises forming at least one of a second device metal layer and a second conductive metal layer.

A method for depositing crystalline semiconductors onto a substrate is provided. In this method, an electrical voltage is applied between a metallic sputtering target and the anode of a magnetron sputtering unit to ignite a magnetron discharge. This discharge causes a particle flux from the sputtering target to the substrate and excites the reactive gas to an initial quantity of activated reactive gas plasma, resulting in the epitaxial growth of a crystalline semiconductor on the substrate.In this process, during the deposition of a semiconductor on the substrate, an additional power input is implemented into the reactive gas plasma, which excites the reactive gas to a second quantity of activated reactive gas plasma that is higher than the first quantity of activated reactive gas plasma, but which keeps the particle flux from the sputter target to the substrate the same or increases only disproportionately less than the increase in the first quantity of activated reactive gas plasma compared to the second quantity of activated reactive gas plasma.

Techniques for mitigating capacitive coupling effects associated with electrical paths extending through a stack of multiple dies. The multiple dies include a memory structure having non-volatile memory cells (such as NAND). The multiple dies may also include control circuitry that performs die-level control of the non-volatile memory cells. The control circuitry may be formed on a semiconductor substrate (such as a crystalline silicon substrate). The electrical paths may extend through the stack of dies. The electrical paths may include through-silicon vias (TSVs) extending through the crystalline semiconductor substrate, and the control circuitry is formed in the crystalline semiconductor substrate.

The invention provides a composite photonic crystal semiconductor laser with a low 95% energy divergence angle, and is applied to the field of semiconductor lasers. The semiconductor laser comprises a substrate, an N-type limiting layer, a composite photonic crystal layer, an N-type waveguide layer, an active layer, a P-type waveguide layer and a P-type limiting layer which are sequentially stacked from bottom to top, wherein the composite photonic crystal layer is composed of a plurality of photonic crystal groups of different structures stacked in the epitaxial direction, and each photonic crystal group comprises a plurality of photonic crystal pairs of the same structure; the photonic crystal pair is formed by stacking a high-refractive-index waveguide layer and a low-refractive-index waveguide layer up and down, and the high-refractive-index waveguide layer and the low-refractive-index waveguide layer are alternately arranged in the composite photonic crystal layer. Through the composite photonic crystal structure, the light field distribution can be effectively regulated and controlled, so that 95% of energy divergence angle of the far field of the semiconductor laser is remarkably reduced.

Systems and methods are provided for non-volatile optical storage devices that leverage photon avalanche-induced carrier trapping in semiconductor materials. Examples herein include a crystalline semiconductor layer disposed on a substrate and an amorphous layer disposed on the crystalline semiconductor layer. The crystalline semiconductor layer comprises an optical waveguide and a PN junction formed in the optical waveguide. An optical source is configured to emit light of a wavelength into the optical waveguide and a power source is configured to supply a first voltage bias across the PN junction that causes an amplitude of optical power of light emitted from the optical waveguide to change from a first amplitude to a second amplitude. The optical waveguide emits light at the second amplitude while the first voltage bias is supplied and after the first voltage bias is removed.

Provided is a transistor that has a small footprint, or a method for producing the same. This method for producing a semiconductor device that has a crystalline semiconductor layer has: a first step for forming a semiconductor layer on an insulating layer in which a groove section is provided; a second step for forming a mask on the semiconductor layer; a third step for etching the semiconductor layer on the insulating layer, where the mask is not formed; and a fourth step for etching the semiconductor layer in the groove section, where the mask is not formed. The surface of the semiconductor layer on the insulating layer is formed so as to have a first crystal plane, and the surface of the semiconductor layer on a side surface of the groove section is formed so as to have a second crystal plane.

An electronic device may have a touch sensitive display that is insensitive to the presence of moisture. The display may have a two-dimensional optical touch sensor that gathers touch input while the electronic device is immersed in water or otherwise exposed to moisture. The optical touch sensor may include light sources and light detectors. The light sources and the light sensors may be mounted on a common substrate with an array of image pixels. The image pixels may be formed by crystalline semiconductor light-emitting diode dies. Angular filters may be included over the light sources and / or the light detectors to improve discrimination between a user's finger and water droplets. The angular filters may be on-axis light blocking angular filters or off-axis light blocking angular filters.

The invention provides a chemiresistive substrate for a dihydrogen-sensitive amperometric gas sensor, the chemiresistive substrate comprising: a crystalline semiconductive metal oxide layer comprising an array of spaced apart hollow metal oxide micro-shells protruding from a base plane of the metal oxide layer; and metallic nanoparticles decorating the metal oxide layer.

To provide a semiconductor memory device with high reliability. [Solution] The semiconductor memory device comprises a laminate having conductive layers and insulating layers, wherein the conductive layers and insulating layers are alternately stacked in a first direction; a plurality of memory pillars extending in the first direction within the laminate; and a structure that divides the plurality of memory pillars and extends in the first direction within the laminate. The structure comprises a crystalline conductor extending in the first direction within the laminate; a first insulating film provided between the laminate and the crystalline conductor; a crystalline semiconductor film containing silicon provided between the crystalline conductor and the first insulating film; and a second insulating film containing silicon and oxygen provided between the crystalline semiconductor film and the side surface of the crystalline conductor. The crystalline conductor has a first crystalline region containing germanium that is in contact with the crystalline semiconductor film; and a second crystalline region provided on the first crystalline region that is in contact with the second insulating film in a second direction perpendicular to the first direction.

A semiconductor structure (100) includes a first semiconductor channel having a plurality of vertical nanowires (106) and a second semiconductor channel having a plurality of vertical nanowires (106). The first semiconductor channel and the second semiconductor channel are configured in a stacked configuration. The plurality of vertical nanowires (106) of the first semiconductor channel are configured to be in alternating positions relative to the plurality of vertical nanowires (106) of the second semiconductor channel.

A semiconductor integrated circuit device includes a passive device region and one or more logic region(s). The passive device region includes a semiconductor substrate region (e.g. a retained substrate structure) below a doped semiconductor region. The passive device region further includes a crystalline semiconductor material layer directly coupled with a backside of the semiconductor substrate region. The logic region(s) includes a front end of line (FEOL) transistor with a first source / drain region and a second source / drain region, and a backside contact directly coupled with the first source / drain region. A frontside surface of the crystalline semiconductor material layer is substantially coplanar with a backside surface of the backside contact. Due to the crystalline semiconductor material layer, the semiconductor material within the passive device region is relatively increased which may improve functionality of passive device(s), such as such as resistors, capacitors, inductors, transformers, diodes, that may be formed therein.

A method for filling a gap is provided, comprising: providing a semiconductor substrate having a gap in a deposition chamber, wherein a bottom of the gap comprises crystalline semiconductor material, and wherein sidewalls of the gap comprise amorphous material; depositing a silicon precursor in the gap.

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

The present invention provides a film forming apparatus including an atomizer configured to atomize a raw material solution to generate a raw material mist, a carrier gas supplier configured to supply a carrier gas that carries the raw material mist, a mist supplier configured to supply a mixture gas in which the raw material mist and the carrier gas are mixed to a surface of a substrate, a stage configured to hold the substrate, a heater configured to heat the substrate, and an exhaust unit directly or indirectly connected to the stage through piping. Thus, a film forming apparatus that can form a crystalline semiconductor film with favorable crystal orientation stably and with high productivity, and a method of forming a crystalline semiconductor film are provided.

Multi-die composite packages including directly bonded IC die and at least one electro-thermo-mechanical die (ETMD). An ETMD is distinguished from an active IC die as an ETMD is a passive die lacking any semiconductor devices, such as transistors. In exemplary embodiments, an ETMD includes a substrate, which may be a crystalline semiconductor material, for example, and one or more through substrate vias (TSVs) passing through a thickness of the substrate. The TSVs may enable a ETMD to electrically interconnect an (active) IC die of a composite package to another IC die of the package or to a package host.

The present invention relates to a crystal, a semiconductor element, a semiconductor device, and a semiconductor system. The present invention provides a crystal useful for a semiconductor element and a semiconductor element excellent in electrical characteristics. A semiconductor element is produced using a crystal having a corundum structure and including a crystalline oxide containing gallium and / or indium as a main component, characterized in that the crystalline oxide further includes a metal of Group 4 of the periodic table, a semiconductor device such as a power card is produced from the produced semiconductor element, and a semiconductor system is constructed from these semiconductor elements or semiconductor devices.

Methods and systems for cross-domain controlled stimulation of biological dynamics by AI iterative optimization physical patterns for migrating structured patterns (including crystals, semiconductors, and related processes) from physical or mineral systems to target biological systems to guide their measurable dynamic processes, such as growth, migration, proliferation, branching, and self-organization. The present application generates a defect and anisotropy mapping or descriptor delta (x) from a physical source and converts a derived stimulation pattern or stimulation recipe under constrained conditions into an executable stimulation protocol, which may include electrical stimulation or electro-physical stimulation, light stimulation, chemical stimulation, thermal stimulation or mechanical stimulation, or may be in a multi-modal form, meanwhile, the biological constraint and the executable and safety constraint of the experimental device are met; applying the stimulation protocol to a target biological system and obtaining observation data through a sensor and / or visual means (photo, video, time-lapse photography) to extract quantitative features and calculate a result indicator that can be compared to a baseline; subsequent tests are selected under constraint conditions by an artificial intelligence assisted decision engine to maximize information utility and achieve improvements while using stop rules to limit low-yield experimental activities and maintain comparability and repeatability between different runs.

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed, wherein the substrate includes an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure. An insulating layer covering the metal gate structure is formed. A semiconductive material layer is formed over the epitaxial structure and the insulating layer, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating layer comprises amorphous semiconductive material. The second portion of the semiconductive material layer is removed. A semiconductor structure thereof is also provided.

The semiconductor device includes a field effect transistor (FET). The FET comprises a first channel, a first source electrode and a first drain electrode; a second channel, a second source electrode and a second drain electrode; and a gate structure disposed over the first channel and the second channel. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystalline semiconductor layer and the second source includes a second crystalline semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more group IV elements and one or more transition metal elements. The first crystalline semiconductor layer is not in direct contact with the second crystalline semiconductor layer. The embodiment of the invention also relates to a method for manufacturing the semiconductor device.

Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a semiconductor layer comprising a crystalline semiconductor material, a waveguide core including a first sidewall and a second sidewall, and a photodetector including a light-absorbing layer, an anode, and a cathode. The light-absorbing layer includes a first portion and a second portion that are disposed on the semiconductor layer. The first portion of the light-absorbing layer is adjacent to the first sidewall of the waveguide core, and the second portion of the light-absorbing layer is adjacent to the second sidewall of the waveguide core.

Technology for mitigating capacitive coupling effects associated with electrical pathways that extend through a stack of multiple dies. The multiple dies include memory structures having non-volatile memory cells such as NAND. The multiple dies may also include control circuitry that performs die level control of the non-volatile memory cells. This control circuitry may be formed on a semiconductor substrate such as a crystalline silicon substrate. The electrical pathways may extend through a stack of dies. The electrical pathways may include through silicon vias (TSVs) that extend through the crystalline semiconductor substrate in which the control circuitry is formed.

An electronic device display can have pixels formed from crystalline semiconductor light emitting diode dies, organic light emitting diodes, or other pixel structures. These pixels can be formed in a display panel having a single substrate or an array of display panel tiles (24). The display panel has inward-facing display panel contacts (56') that mate with corresponding outward-facing interconnect substrate contacts (54) on an interconnect substrate (44). The interconnect substrate can have a region of compound curvature overlapped by the display panel. To enhance the flexibility of the interconnect substrate, the interconnect substrate can have flexibility enhancing openings, and / or can be formed from a material having a low modulus of elasticity, such as silicone or other elastomeric material.

Structure comprising a semiconductor-on-insulator, SOI, wafer (12) comprising a lower crystalline semiconductor layer (12a), a polysilicon layer (18) above the lower crystalline semiconductor layer (12a), an upper crystalline semiconductor layer (12b) above the polysilicon layer (18), a buried insulator layer (14, 20) above the upper crystalline semiconductor layer (12b), and an uppermost crystalline semiconductor layer (22) above the buried insulator layer (14, 20), wherein the polysilicon layer (18) comprises an extension region (18a) which is surrounded on its sides by the upper crystalline semiconductor layer (12b).

A backside emitter solar cell structure having a heterojunction. On one side edge of the backside emitter solar cell structure having the heterojunction, on an edge region of a crystalline semiconductor substrate of the backside emitter solar cell structure having the heterojunction having a doping of a first conductivity type, there is a layer sequence with a double intrinsic layer formed.