6 results about "Amorphous semiconductors" patented technology

A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and / or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.

Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor device comprises the steps of forming a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer on one side of a substrate in sequence; a first via hole penetrates through the third dielectric layer, the second conductive layer and the second dielectric layer, a first amorphous semiconductor layer is deposited in the first via hole, and the first amorphous semiconductor layer is in contact with the first conductive layer and the second conductive layer; the first amorphous semiconductor layer is crystallized and conducted to form a first semiconductor layer, the material of the first semiconductor layer comprises a polycrystalline or monocrystal-like semiconductor, and a first gate dielectric layer and a first gate electrode are deposited in the first via hole to obtain a first transistor; manufacturing a second transistor on the side, away from the substrate, of the first gate electrode; and the material of a second semiconductor layer of the second transistor comprises a metal oxide semiconductor, and the second semiconductor layer is connected with the first gate electrode, so that the performance of the semiconductor device is improved.

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed, wherein the substrate includes an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure. An insulating layer covering the metal gate structure is formed. A semiconductive material layer is formed over the epitaxial structure and the insulating layer, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating layer comprises amorphous semiconductive material. The second portion of the semiconductive material layer is removed. A semiconductor structure thereof is also provided.

This invention relates to a heterostructure ultraviolet photoelectric synaptic transistor, its fabrication method, and its applications. The transistor's structure, from top to bottom, consists of a glass substrate, a gate dielectric layer, an active layer, and a source-drain electrode layer. It also includes a gate electrode disposed within the gate dielectric layer and in contact with the glass substrate. The active layer comprises an indium tin zinc oxide layer and a magnesium zinc oxide layer stacked sequentially. This invention leverages the superior electron mobility and channel stability of indium tin zinc oxide amorphous semiconductors and the intrinsic absorption characteristics of magnesium zinc oxide in the ultraviolet band to achieve a more sensitive transient response and precise synaptic weight update function. This has significant application value for simulating biological visual perception and the development of neuromorphic electronics.

The objective is to provide solar cells with good power generation performance and in the desired size and shape. [Solution] A solar cell that solves the above problem includes an n-type or p-type crystalline silicon layer having a first main surface and a second main surface which is the back surface thereof, an amorphous semiconductor layer or passivation layer disposed adjacent to the first main surface of the crystalline silicon layer, and an electrode layer disposed on the first main surface of the crystalline silicon layer. At least one side surface of the crystalline silicon layer has a first region that is continuous from the first main surface side and is covered by the amorphous semiconductor layer or the passivation layer.