23 results about "Amorphous semiconductors" patented technology

The embodiment of the invention provides a back contact cell and a preparation method thereof, and a photovoltaic module, and relates to the field of solar cells, the back contact cell comprises a silicon substrate, the back surface of the silicon substrate comprises a first region, a second region and a spacer region, the first region comprises a first sub-region and a second sub-region, and the spacer region comprises a second sub-region and a third sub-region; the spacer region comprises a first spacer sub-region adjacent to the first region and a second spacer sub-region adjacent to the second region; the first carrier collection layer has a first conduction type, is arranged on the back surface of the silicon substrate and is positioned in the first region and the first spacer region; the amorphous semiconductor layer is arranged on the first carrier collection layer and is positioned in the second sub-region and the first spacer sub-region; the second carrier collection layer has an opposite second conduction type, is arranged on the back surface of the silicon substrate, is positioned in the second region, the spacer region and the second sub-region, and is positioned on the amorphous semiconductor layer in the second sub-region and the first spacer region; and the first electrode is arranged in the first sub-region and is positioned on one side, far away from the silicon substrate, of the first carrier collection layer. The back contact battery has excellent electrical properties.

The invention relates to a semiconductor structure, a semiconductor device and a forming method thereof. The present disclosure describes a semiconductor device having a semiconductor seed layer on an S / D dielectric structure. The semiconductor structure comprises a channel structure on a substrate; a gate structure surrounding the channel structure; an internal spacer adjacent to ends of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the internal spacer; an amorphous semiconductor material on the dielectric structure; and an epitaxial structure on top surfaces of the amorphous semiconductor material and the dielectric structure.

The application discloses a trench gate semiconductor device and a manufacturing method thereof, and is used for improving the reliability of the trench gate semiconductor. The trench gate semiconductor comprises a substrate with a first conductive type; an epitaxial layer with the first conductive type, which is grown on the substrate; a well region with a second conductive type, which is formed on a surface layer of the epitaxial layer; a source region with the first conductive type, which is formed on a surface layer of the well region; a first trench, which extends from a surface of the source region to the epitaxial layer through the well region; a gate, which is formed in the first trench through a gate insulating film; and an amorphous semiconductor layer, which is formed in the first trench and wraps an outer bottom wall of the gate and corner portions on both sides of the outer bottom wall through the gate insulating film, and the amorphous semiconductor layer is composed of a low dielectric constant material.

The invention discloses a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; carrying out ion implantation on the amorphous semiconductor thin film so as to implant 3A group ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface removal processing on the first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to divide the second metal layer into a source electrode and a drain electrode.

The invention relates to a solid phase epitaxy method of an amorphous semiconductor over a crystalline substrate. A semiconductor device (200) includes: a semiconductor substrate (202); a first crystalline silicon layer (204) over the semiconductor substrate (202); an electronic component (206, 208) extending into the first crystalline silicon layer (204); a second crystalline silicon layer (224) over the electronic component (206, 208) and the first crystalline silicon layer (204); and a distributed silicon oxide inclusion layer (219) between the first crystalline silicon layer (204) and the second crystalline silicon layer (224).

The invention relates to a back contact solar cell and a preparation method thereof. The back contact solar cell comprises: a semiconductor substrate having a light facing surface and a backlight surface, the backlight surface comprising a first region; the first intrinsic amorphous semiconductor layer is arranged on the backlight surface and located in the first area; the first doped microcrystalline state semiconductor layer is arranged on the first intrinsic amorphous state semiconductor layer and located on the side, away from the semiconductor substrate, of the first intrinsic amorphous state semiconductor layer; the second doped microcrystalline state semiconductor layer is arranged on the first doped microcrystalline state semiconductor layer and is positioned on one side, far away from the semiconductor substrate, of the first doped microcrystalline state semiconductor layer; wherein the conduction type of the first doped microcrystalline-state semiconductor layer is the same as that of the second doped microcrystalline-state semiconductor layer, and the doping concentration of the second doped microcrystalline-state semiconductor layer is larger than that of the first doped microcrystalline-state semiconductor layer. The photoelectric conversion efficiency can be improved.

A method includes forming a stack of nanostructures over a substrate; forming a source / drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source / drain by annealing the amorphous semiconductor layer.

A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and / or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.

Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.

The present invention provides a method for manufacturing a solar cell, comprising a step of forming a first semiconductor layer on one surface of a substrate, wherein the step of forming a first semiconductor layer comprises repeatedly performing a cycle that includes a step of forming an amorphous semiconductor layer and a step of crystallizing at least a portion of the amorphous semiconductor layer, the step of forming an amorphous semiconductor layer comprises supplying a silicon-containing gas and a first gas, and the step of crystallizing at least a portion of the amorphous semiconductor layer comprises forming plasma that includes a second gas.

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor device comprises the steps of forming a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer on one side of a substrate in sequence; a first via hole penetrates through the third dielectric layer, the second conductive layer and the second dielectric layer, a first amorphous semiconductor layer is deposited in the first via hole, and the first amorphous semiconductor layer is in contact with the first conductive layer and the second conductive layer; the first amorphous semiconductor layer is crystallized and conducted to form a first semiconductor layer, the material of the first semiconductor layer comprises a polycrystalline or monocrystal-like semiconductor, and a first gate dielectric layer and a first gate electrode are deposited in the first via hole to obtain a first transistor; manufacturing a second transistor on the side, away from the substrate, of the first gate electrode; and the material of a second semiconductor layer of the second transistor comprises a metal oxide semiconductor, and the second semiconductor layer is connected with the first gate electrode, so that the performance of the semiconductor device is improved.

A method includes a number of operations. A bottom transistor and a top transistor overlapping the bottom transistor are formed. A vertical local interconnect (VLI) structure is formed and electrically connects source / drain regions of the bottom transistor and the top transistor. A hard mask layer is formed over the VLI structure, wherein the hard mask layer includes a bottom nitride layer, a top nitride layer and an amorphous semiconductive layer directly between the bottom nitride layer and the top nitride layer. The hard mask layer is patterned. A trench is formed in the VLI structure. An isolation structure is formed in the trench. A first polishing process is performed to the isolation structure and the hard mask layer, wherein the first polishing process stops the amorphous semiconductive layer. A second polish process is performed to the isolation structure, the bottom nitride layer and the amorphous semiconductive layer.

The invention relates to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; carrying out ion implantation on the amorphous semiconductor thin film so as to implant 3A group ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface removal processing on the first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to divide the second metal layer into a source electrode and a drain electrode.

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed, wherein the substrate includes an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure. An insulating layer covering the metal gate structure is formed. A semiconductive material layer is formed over the epitaxial structure and the insulating layer, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating layer comprises amorphous semiconductive material. The second portion of the semiconductive material layer is removed. A semiconductor structure thereof is also provided.

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source / drain trenches, forming a first dielectric layer over the recessed fin structure in the source / drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source / drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source / drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

[Problem] To provide a light emitting device in which the uniformity of the in-plane distribution of optical output is increased and the exhaust heat efficiency is improved. [Solution] A light emitting device comprising: a first reflecting mirror constituted by laminating a plurality of semiconductor materials having different refractive indexes in a first direction; an active layer provided on a second surface side of the first reflecting mirror and that emits light through application of power; a second reflecting mirror constituted by laminating a plurality of non-conductive materials having different refractive indexes in the first direction or laminating a non-conductive material and an amorphous semiconductor material having different refractive indexes in the first direction; a plurality of protrusions provided between a fourth surface and a sixth surface and protruding in the first direction toward the second reflecting mirror, or a plurality of recesses recessed in the first direction from the second reflecting mirror; a first electrode electrically connected to one surface of the active layer; and a second electrode electrically connected to the other surface of the active layer.

A semiconductor device comprises a semiconductor substrate, a first crystalline silicon layer over the semiconductor substrate, an electronic component extending into the first crystalline silicon layer, a second crystalline silicon layer over the electronic component and the first crystalline silicon layer, and a layer of distributed silicon oxide inclusions between the first crystalline silicon layer and the second crystalline silicon layer.

This invention relates to a heterostructure ultraviolet photoelectric synaptic transistor, its fabrication method, and its applications. The transistor's structure, from top to bottom, consists of a glass substrate, a gate dielectric layer, an active layer, and a source-drain electrode layer. It also includes a gate electrode disposed within the gate dielectric layer and in contact with the glass substrate. The active layer comprises an indium tin zinc oxide layer and a magnesium zinc oxide layer stacked sequentially. This invention leverages the superior electron mobility and channel stability of indium tin zinc oxide amorphous semiconductors and the intrinsic absorption characteristics of magnesium zinc oxide in the ultraviolet band to achieve a more sensitive transient response and precise synaptic weight update function. This has significant application value for simulating biological visual perception and the development of neuromorphic electronics.

The objective is to provide solar cells with good power generation performance and in the desired size and shape. [Solution] A solar cell that solves the above problem includes an n-type or p-type crystalline silicon layer having a first main surface and a second main surface which is the back surface thereof, an amorphous semiconductor layer or passivation layer disposed adjacent to the first main surface of the crystalline silicon layer, and an electrode layer disposed on the first main surface of the crystalline silicon layer. At least one side surface of the crystalline silicon layer has a first region that is continuous from the first main surface side and is covered by the amorphous semiconductor layer or the passivation layer.

Method for embedding a CFET transistor device. This description relates to a method for embedding a CFET transistor device, comprising at least: - fabrication, on a first substrate (108), of a first semiconductor superlattice (102) surmounted by a first interface layer (122) comprising at least amorphous semiconductor or metal or a semiconductor-metal composite; - fabrication, on a second substrate (116), of a second semiconductor superlattice (110) surmounted by a second interface layer (128) comprising at least amorphous semiconductor or metal or a semiconductor-metal composite; - bonding the first and second interface layers to each other; and wherein the first and second interface layers are configured to be selectively etched with respect to the semiconductor superlattices. Figure for the abstract: Fig. 3

The invention discloses a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface removal processing on the first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and divide the second metal layer into a source electrode and a drain electrode.

The invention relates to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; carrying out carrier removal processing on the active layer so as to reduce the number of carriers on the side wall of the active layer; forming a second metal layer on the active layer; and performing etching treatment to divide the second metal layer into a source electrode and a drain electrode.

The invention provides a method for analyzing the defect state density of an amorphous semiconductor transistor. The method comprises the following steps: S1, carrying out a transfer characteristic curve test on an oxide device under a shading condition to obtain an initial transfer characteristic curve; s2, performing transfer characteristic curve test on the oxide device under the irradiation condition that the light source wavelength is 405-590nm to obtain test transfer characteristic curves under different light source wavelengths; and S3, comparing the initial transfer characteristic curve with the test transfer characteristic curve to obtain the defect state density of the amorphous semiconductor transistor. According to the method provided by the invention, the defect state density in the oxide device can be rapidly analyzed, so that a basis is provided for material defect and process optimization in an amorphous semiconductor transistor.