114 results about "Silicon on insulator" patented technology

Disclosed are a neuron and a neuromorphic system including the same. More particularly, a neuron according to an embodiment of the present invention includes a completely depleted Silicon-On-Insulator (SOI) device whose a depletion region is controlled according to an inputted electrical signal to perform integration and leakage.

The invention relates to a signal control circuit based on a transverse tandem photoelectric detection unit structure and a control method, and belongs to the field of photoelectric detection and control. The circuit comprises a transverse tandem detection unit structure and a post-stage signal processing circuit, wherein the post-stage signal processing circuit comprises a plurality of resistor units, a bipolar transistor and an MOS (Metal Oxide Semiconductor) tube; according to the method, an optical signal is converted into an electric signal through a transverse tandem type detection unit structure, and charge release and voltage signal output processing are carried out through a post-stage signal processing circuit. When light enters the transverse tandem type detection unit structure, the output tube is switched on; when no photo-generated current exists, the output tube is switched off; and the output tube can output a voltage control signal meeting the amplitude requirement when being switched on or switched off so as to control the working state of a rear-end circuit. By combining the photoelectric detection unit and the signal processing circuit, monolithic integration and process fusion of the silicon-on-insulator process are realized, the parasitic effect between elements can be effectively reduced, and the interconnection scheme of discrete devices is upgraded.

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: growing a polycrystalline silicon layer on a stripping surface of a current reused donor substrate, so as to form a supporting substrate; bonding the supporting substrate with a current donor substrate to be bonded through the polycrystalline silicon layer to form a current bonding wafer; performing stripping heat treatment operation on the current bonding sheet to obtain a silicon-on-insulator substrate and a reusable donor substrate; wherein the current reused donor substrate is a remaining part of a previous to-be-bonded donor substrate for preparing a previous silicon-on-insulator substrate after a previous stripping heat treatment operation. According to the preparation method, by utilizing the rough surface of the stripped substrate, the silicon-on-insulator substrate with excellent performance is provided under the condition that a reprocessing step of damaging the surface is avoided.

Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

The invention discloses an electric field sensor field enhancement cover plate and a preparation method thereof, and belongs to the technical field of micro electro mechanical system manufacturing. The method comprises the following steps: etching a groove on the silicon surface of a silicon wafer or an insulator to form a reinforcing structure; preparing a flat to-be-bonded surface through a bonding and thinning process; performing laser cutting on the glass sheet to form a reserved hole; and bonding the glass sheet and the bonding surface to form the cover plate. Optional steps include sputtering a getter and a metal bonding layer. The bonding process is used for replacing traditional glass backflow, two photoetching steps are omitted, the problems that glass filling is uneven and the surface is uneven are solved, the technological process is remarkably simplified, and the yield is improved. The method is suitable for wafer-level electric field sensor packaging, and the sensitivity and reliability are improved.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

The invention provides a silicon-on-insulator substrate and a preparation method thereof. The preparation method comprises the following steps: executing first ion implantation to obtain a first donor substrate; bonding the first donor substrate and the first support substrate into a first bonding sheet; separating the first bonding sheet to form an intermediate substrate comprising a first top silicon layer; performing intermediate planarization processing on the intermediate substrate to form a planarized intermediate substrate; performing second ion implantation on the planarized intermediate substrate to form a second stripping plane in the first top silicon layer of the planarized intermediate substrate subjected to the second ion implantation; bonding the planarized intermediate substrate subjected to the second ion implantation with a second support substrate to form a second bonding sheet; separating the second bonding sheet to form a first silicon-on-insulator structure and a second silicon-on-insulator structure, the top silicon thickness of the first silicon-on-insulator structure being smaller than the top silicon thickness of the second silicon-on-insulator structure; and performing final planarization processing on the first silicon-on-insulator structure to form a target silicon-on-insulator substrate.

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

The invention concerns a hybrid optical device combining a silicon-on-insulator (SOI) waveguide platform (1) comprising a silicon waveguide (1a) with a thin-film electro-optical (EO) material such as lithium niobate or barium titanate forming a waveguide structure (2). The EO material waveguide structure (2) is bonded in optical contact with the SOI waveguide (1a), and electrodes (6) on its sides enable refractive index modulation via the electro-optical material Pockels effect. A coupling section (7), preferably comprising a tapered SOI waveguide (7a), transfers light between the SOI and EO structures with low loss. The device may include Bragg gratings (4a) or periodically poled sections (4b) in the EO layer for tunable or wavelength-selective modulation. The structure allows fast, reconfigurable light modulation, filtering, and signal routing on a CMOS-compatible platform, suitable for high-speed communication, optical computing, and sensing, offering a compact and efficient electro-optic integration solution.

This invention provides a multifunctional, compact, and high-precision pressure measurement device. The pressure-sensing module of the device employs a MEMS pressure core, with its core being an SOI (silicon-on-insulator) piezoresistive chip. The chip uses a flip-chip structure: the front side of the chip (the side with the piezoresistive circuitry) is fused to a glass cover plate wafer via anodic bonding or glass powder sintering, forming a sealed reference vacuum chamber or atmospheric reference chamber. The back side of the chip serves as the pressure-sensing surface, directly or through a pressure-transmitting medium contacting the pressure being measured. This device is suitable for miniaturized applications in high-temperature, high-pressure, small-volume, and strong electromagnetic interference environments.

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

The invention relates to a photonic component for setting non-volatile operational states, comprising: - At least one light-guiding structure (3) formed in a silicon layer of a silicon-on- insulator substrate (2); - At least one switching element (4) formed by an optical phase change material (8) and a heating structure (7) underneath thereof, wherein the at least one switching element (4) is laterally neighbored to the at least one light-guiding structure (3) so as to provide an evanescent coupling between the at least one light-guiding structure (3) and at least one switching element (4); wherein the heating structure (7) of the switching element (4) is formed by a thinned portion of the silicon layer (22) of the silicon-on-insulator-substrate (2) with the lowest silicon thickness to provide a current path through the silicon layer (22), particularly along the direction of arrangement of the at least one light-guiding structure (3) and the at least one switching element (4), so that the current density of the current path is highest in the heating structure (7) of the at least one switching element (4).

Methods and structures are presented for mitigating back-gating effects in radio frequency (RF) silicon-on-insulator (SOI) substrates, RF-SOI. According to an aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI beneath a first circuit / device to be protected. The first implant or junction is entirely contained within the TRL. A planar surface area of the first implant and / or junction entirely contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates a BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL beneath a second circuit / device. The first implant or junction and the second implant or junction are not connected and are separated by an undoped region of the TRL.

In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+ / intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 Å, respectively, so as to realize the flatness of the silicon-on-insulator film.

The present disclosure relates to methods, devices, systems, and techniques for forming semiconductor devices. An example semiconductor device includes a semiconductor layer and an insulating layer stacked on the semiconductor layer along a first direction. The semiconductor device further includes a first transistor and a second transistor. The first transistor includes a first gate structure and a first semiconductor body. The first semiconductor body is in contact with the insulating layer. The second transistor extends into the semiconductor layer along the first direction. The second transistor includes a second gate structure and a second semiconductor body. The second gate structure includes a dielectric layer aligned with the insulating layer along a second direction perpendicular to the first direction.

The application belongs to the technical field of electric field sensing, and specifically discloses a piezoelectric-electrostatic double-regulation electric field sensor based on silicon-on-insulator, which comprises a silicon-on-insulator substrate, a piezoelectric driving unit, a composite sensing electrode plate and a signal detection circuit; the silicon-on-insulator substrate is composed of a substrate layer, a buried oxygen layer and a device layer, the substrate layer is provided with a back cavity, the device layer forms a center suspended plate and a support beam through a releasing groove, and the center suspended plate and the support beam form a sensitive thin film structure; the piezoelectric driving unit is embedded in the back cavity and is fixed to the lower surface of the sensitive thin film structure, the composite sensing electrode plate is attached to the upper surface of the center suspended plate, and the stress concentration area of the support beam is integrated with a piezoresistance element and forms a Wheatstone bridge. Through the piezoelectric-electrostatic double-regulation mechanism and the optimized structure design, the application realizes electric field detection with high sensitivity, low noise and good temperature stability, has strong process compatibility, and can be widely applied to scenes with high requirements for electric field measurement, such as power equipment monitoring and thunderstorm early warning.

The invention provides a method for monitoring the epitaxial doping concentration of an FDSOI source / drain region, and the method comprises the steps: 1, providing a silicon-on-insulator substrate, and forming a mask layer with an SIMS pad pattern on the silicon-on-insulator substrate; step 2, taking the mask layer as a mask, and removing the exposed insulator layer in the silicon-on-insulator substrate through etching; 3, after the mask layer is removed, a source / drain region epitaxial layer is formed, and preparation of the SIMS pad is completed; and step 4, carrying out SIMS testing on the SIMS pad. And before the source / drain region epitaxial layer is formed, the insulator in the SIMS pad is removed, so that the accurate FDSOI source / drain region epitaxial doping concentration is obtained.

Methods and associated devices including the fabrication of a semiconductor structure that provides a silicon-on-insulator substrate. The semiconductor structure may be formed by providing a base substrate, forming a sacrificial layer over the base structure, and forming a semiconductor layer over the sacrificial layer. The sacrificial layer is removed to form a void that is filled with oxide. The semiconductor structure includes a dielectric support feature extending through the semiconductor and oxide layers and / or a portion of the oxide layer extends to the surface of the semiconductor layer.

The invention relates to a PZT target material and a preparation process thereof, and relates to the technical field of PZT target materials. The preparation process of the PZT target material comprises the following steps: preparing an SOI silicon wafer; selecting a silicon wafer or a silicon-on-insulator wafer as a substrate; silicon wafer doping: doping silicon on the surface of the silicon wafer; depositing an insulating layer: growing a thermal oxide layer or a chemical vapor deposition SiNx layer on the surface, doped with silicon, of the silicon wafer to serve as the insulating layer; depositing a lower electrode layer; a PZT piezoelectric layer is deposited, specifically, radio frequency magnetron sputtering is conducted on the lower electrode layer at the sputtering temperature (500-600 DEG C), the deposition rate is 35-48 nm / min, and the PZT piezoelectric layer is formed; after sputtering, keeping the annealing temperature of 465 DEG C in the chamber and annealing for 5 minutes; etching the PZT piezoelectric layer; etching the lower electrode layer; depositing a top layer; etching the insulating layer; depositing a top layer electrode; etching the top layer silicon; and etching the bottom silicon and the silicon dioxide. The method has the effect of ensuring the piezoelectric property of the prepared PZT target material.

A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET) including a source region, a drain region, a body region coupled to a body resistor, and a gate region coupled to a gate resistor. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled to the body region of the switch FET through the body resistor and coupled to the gate region of the switch FET through the gate resistor. The at least one transistor is an RF silicon on insulator (SOI) device. The dynamic bias control circuit also includes a capacitor coupled to the gate resistor and the body resistor and coupled in parallel with each transistor in the dynamic bias control circuit.

A memory including a memory array having a plurality of bit line inputs and a plurality of word line inputs; a bit line decoder; and control circuitry is provided. The bit line decoder includes a first circuit and a second circuit, the second circuit including a plurality of low voltage field effect transistors (FETs). The control circuitry provides control signals to the plurality of low voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein in the pulse phase, the first circuit and the second circuit receive a desired voltage. The control circuitry provides control signals to the plurality of low voltage FETs at a voltage no greater than a low voltage in the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technology, the use of low voltage FETs in the bit line decoder and the word line decoder reduces the area of the peripheral circuitry of the memory array without requiring changes to the memory array itself.

The invention relates to a method for preparing a silicon-on-insulator substrate (S) comprising an electrical charge trapping layer (4) and having radio frequency and defectivity characteristics below predetermined thresholds. A thickness of the electrical charge trapping layer (4) is chosen to be strictly greater than 1 micrometre and less than 1.6 micrometres. The preparation method comprises a finishing sequence comprising an annealing step exposing the exposed face of the substrate to a neutral or reducing atmosphere for at least 30 minutes at a temperature strictly between 1050°C and 1100°C. According to the invention, the thickness of the electrical charge trapping layer (4) and the temperature of the annealing step are chosen so that the radio frequency and defectivity characteristics are below the respective predetermined thresholds.

The invention discloses a passive wireless MEMS temperature, pressure and humidity integrated sensor and a preparation method, the sensor takes silicon on insulator as a substrate, three independent temperature, pressure and humidity sensing units are integrated in a left-middle-right layout, each unit depends on a polycrystalline silicon support layer, and two SAW sensing structures are respectively integrated on the upper surface and the lower surface. The temperature sensing unit realizes temperature measurement and stress interference filtering through signal summation processing; the pressure sensing unit realizes pressure measurement and temperature drift suppression through signal differential processing; the humidity sensing unit is coated with a humidity sensitive layer through a second SAW humidity sensing structure, and humidity measurement and temperature drift suppression are achieved in combination with signal differential processing; isolation grooves are arranged between the sensing units to achieve signal and physical isolation, and crosstalk is reduced. The sensor is integrally manufactured through an MEMS (Micro Electro Mechanical System) process, and has the advantages of high integration level, strong anti-interference capability and accurate measurement.

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Fully-depleted silicon-on-insulator structures and methods for preparing fully-depleted silicon-on-insulator structures. The fully-depleted silicon-on-insulator structure may include a top layer, a handle structure and a dielectric layer disposed between the silicon top layer and handle structure. The dielectric layer of the silicon-on-insulator structure may be composed of hafnia, zirconia, alumina, or combinations thereof. In some embodiments, the dielectric layer is relatively thick such as at least 20 nm or even at least 50 nm.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single-crystal silicon donor substrate; forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single-crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer; bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single-crystal silicon donor substrate, the handle structure including a single-crystal semiconductor handle substrate; and removing the single-crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and a radio frequency silicon-on-insulator wafer. The silicon-on-insulator substrate comprises a substrate; the insulating layer is arranged on the substrate; and a polysilicon stack disposed on the insulating layer, the polysilicon stack comprising a plurality of polysilicon trap sub-layers separated by conductive intermediate layers, where the conductive intermediate layers are configured to cooperatively generate a potential gradient with adjacent polysilicon trap sub-layers, and free charge carriers are driven to directionally migrate to the adjacent polycrystalline silicon trap sub-layers. According to the silicon-on-insulator substrate, the conductive intermediate layer is adopted to synergistically generate the potential gradient, and active driving and directional migration of free charge carriers are realized, so that the charge capture efficiency is greatly improved, and the total parasitic capacitance is remarkably reduced.