186 results about "Silicon on insulator" patented technology

The invention provides a photonic crystal surface emitting laser and a manufacturing method thereof, the photonic crystal surface emitting laser comprises a gain assembly and a photonic crystal assembly, and the gain assembly comprises a semiconductor substrate, a carrier transport layer and an active layer which are stacked in sequence; the photonic crystal assembly comprises a silicon-on-insulator structure and a photonic crystal structure formed on the silicon-on-insulator structure; the active layer and the photonic crystal structure are combined in a bonding mode so that light feedback and surface emission can be achieved through the photonic crystal structure when the active layer emits light. According to the photonic crystal surface emitting laser and the manufacturing method thereof, the key components of the photonic crystal surface emitting laser are separately manufactured and integrated through bonding, so that the manufacturing process is simplified, the manufacturing cost is reduced, the yield is improved, the process of each module can be independently optimized, and the risk of failure of the whole process is reduced.

The invention discloses a low-power-consumption radiation-resistant quadrature voltage-controlled oscillator based on an SOI (Silicon On Insulator) process, relates to the technical field of quadrature voltage-controlled oscillators, and is used for solving the technical problems that an existing quadrature voltage-controlled oscillator is low in radiation resistance in a harsh radiation environment and does not have the characteristic of low power consumption. The invention discloses a low-power-consumption anti-radiation quadrature voltage-controlled oscillator based on an SOI process. The low-power-consumption anti-radiation quadrature voltage-controlled oscillator comprises a first voltage-controlled oscillator, a second voltage-controlled oscillator, a first tail filter and a second tail filter, the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively form an LC resonant cavity with a parasitic capacitor of an inductor and a varactor through the inductor; the first tail filter is connected with the first voltage-controlled oscillator, and the second tail filter is connected with the second voltage-controlled oscillator; two inductors of the first tail filter and the second tail filter are coupled; lC resonant cavities of the first voltage-controlled oscillator and the second voltage-controlled oscillator output oscillation waveforms, and negative impedance is formed through configured transistor pairs, so that the waveforms are output constantly.

The invention discloses a low-power-consumption voltage-controlled oscillator based on an SOI (Silicon On Insulator) process, relates to the technical field of integrated circuit design, and is used for solving the technical problem that an existing Colpitts oscillator is too high in power consumption and cannot be applied to a low-power-consumption integrated circuit. The invention discloses a low-power-consumption voltage-controlled oscillator based on an SOI (Silicon On Insulator) process. The low-power-consumption voltage-controlled oscillator comprises a Colpitts resonance circuit, a negative resistance unit and an LC filter network, the negative resistance unit is at least provided with a pair of RC network bias NMOS transistors and a pair of cross-coupled NMOS transistors, and the drain electrodes of the RC network bias NMOS transistors are connected with the Colpitts resonance circuit; the input end of the LC filter network is connected with the source electrodes of the cross-coupled NMOS transistors; the negative resistance unit biases the NMOS transistor through the RC network to introduce a feedback path to form a C-class oscillator structure, the Colpitts resonance circuit generates a first signal, and the first signal passes through the negative resistance unit and is output after common-mode noise is filtered by the LC filter network.

Disclosed are a neuron and a neuromorphic system including the same. More particularly, a neuron according to an embodiment of the present invention includes a completely depleted Silicon-On-Insulator (SOI) device whose a depletion region is controlled according to an inputted electrical signal to perform integration and leakage.

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

The disclosure relates to a method of manufacturing an avalanche photodetector (APD) (100). The method comprises: providing a silicon-on-insulator substrate comprising an oxide layer (101) and a silicon layer (102) disposed on the oxide layer, the silicon-on-insulator substrate comprising a central region (110) in which an n+ doped layer (103) is embedded in the silicon layer, an embedded intrinsic layer (104) is overlaying the n+ doped layer and an intrinsic multiplication layer (105) is overlaying the embedded intrinsic layer and the n+ doped layer; forming in the silicon layer on the central region, by a thermal drive-in process, a p+ doped charge layer (106) above the intrinsic multiplication layer, wherein the p+ doped charge layer forms with the embedded intrinsic layer, the intrinsic multiplication layer and the n+ doped layer a PIN junction of the APD which is configured to cause a photoelectric effect to convert light energy to electrical energy; and depositing on the central region a germanium absorption layer (107) overlaying the p+ doped charge layer, the germanium absorption layer being configured to function as a light absorption layer to absorb light.

A photonic edge coupler or spot size converter (SSC) includes a plurality of juxtaposed auxiliary waveguide layers, and an underlying silicon-on-insulator (SOI) waveguide. In one embodiment, the SSC includes two waveguide layers, each having four auxiliary waveguides, including two inner auxiliary waveguides interposed between two outer auxiliary waveguides. The waveguide layer includes at least two portions in total. In the first portion, each auxiliary waveguide gradually widens in the light propagation direction. In the second portion, each of the external auxiliary waveguides converges with each other. The SOI waveguide partially overlaps the first portion, completely overlaps the second portion, and extends therefrom. The SSC facilitates coupling light at 1550 nm from a flat-split standard single-mode fiber having a mode field diameter of 10.4 [mu] m to an SOI waveguide having low loss and flat band response at C-band and L-band telecommunications wavelengths.

The invention relates to a signal control circuit based on a transverse tandem photoelectric detection unit structure and a control method, and belongs to the field of photoelectric detection and control. The circuit comprises a transverse tandem detection unit structure and a post-stage signal processing circuit, wherein the post-stage signal processing circuit comprises a plurality of resistor units, a bipolar transistor and an MOS (Metal Oxide Semiconductor) tube; according to the method, an optical signal is converted into an electric signal through a transverse tandem type detection unit structure, and charge release and voltage signal output processing are carried out through a post-stage signal processing circuit. When light enters the transverse tandem type detection unit structure, the output tube is switched on; when no photo-generated current exists, the output tube is switched off; and the output tube can output a voltage control signal meeting the amplitude requirement when being switched on or switched off so as to control the working state of a rear-end circuit. By combining the photoelectric detection unit and the signal processing circuit, monolithic integration and process fusion of the silicon-on-insulator process are realized, the parasitic effect between elements can be effectively reduced, and the interconnection scheme of discrete devices is upgraded.

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: growing a polycrystalline silicon layer on a stripping surface of a current reused donor substrate, so as to form a supporting substrate; bonding the supporting substrate with a current donor substrate to be bonded through the polycrystalline silicon layer to form a current bonding wafer; performing stripping heat treatment operation on the current bonding sheet to obtain a silicon-on-insulator substrate and a reusable donor substrate; wherein the current reused donor substrate is a remaining part of a previous to-be-bonded donor substrate for preparing a previous silicon-on-insulator substrate after a previous stripping heat treatment operation. According to the preparation method, by utilizing the rough surface of the stripped substrate, the silicon-on-insulator substrate with excellent performance is provided under the condition that a reprocessing step of damaging the surface is avoided.

Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

The invention discloses an electric field sensor field enhancement cover plate and a preparation method thereof, and belongs to the technical field of micro electro mechanical system manufacturing. The method comprises the following steps: etching a groove on the silicon surface of a silicon wafer or an insulator to form a reinforcing structure; preparing a flat to-be-bonded surface through a bonding and thinning process; performing laser cutting on the glass sheet to form a reserved hole; and bonding the glass sheet and the bonding surface to form the cover plate. Optional steps include sputtering a getter and a metal bonding layer. The bonding process is used for replacing traditional glass backflow, two photoetching steps are omitted, the problems that glass filling is uneven and the surface is uneven are solved, the technological process is remarkably simplified, and the yield is improved. The method is suitable for wafer-level electric field sensor packaging, and the sensitivity and reliability are improved.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

The invention provides a silicon-on-insulator substrate and a preparation method thereof. The preparation method comprises the following steps: executing first ion implantation to obtain a first donor substrate; bonding the first donor substrate and the first support substrate into a first bonding sheet; separating the first bonding sheet to form an intermediate substrate comprising a first top silicon layer; performing intermediate planarization processing on the intermediate substrate to form a planarized intermediate substrate; performing second ion implantation on the planarized intermediate substrate to form a second stripping plane in the first top silicon layer of the planarized intermediate substrate subjected to the second ion implantation; bonding the planarized intermediate substrate subjected to the second ion implantation with a second support substrate to form a second bonding sheet; separating the second bonding sheet to form a first silicon-on-insulator structure and a second silicon-on-insulator structure, the top silicon thickness of the first silicon-on-insulator structure being smaller than the top silicon thickness of the second silicon-on-insulator structure; and performing final planarization processing on the first silicon-on-insulator structure to form a target silicon-on-insulator substrate.

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

A phase shift keying modulator. The modulator comprises: a plurality of silicon waveguides provided in a device layer of a silicon-on-insulator platform, the silicon-on-insulator platform including one or more cavities; one or more III-V semiconductor based devices located within the one or more cavities of the silicon-on-insulator platform, each III-V semiconductor-based device including a III-V semiconductor based waveguide which is coupled at an input end to one of the plurality of silicon waveguides and coupled at an output end to another of the plurality of silicon waveguides, each III-V semiconductor based waveguide comprising an active phase modulating portion; and one or more contacts in electrical contact with each active phase modulating portion, such that the phase shift keying modulator is operable to modulate the phase of an optical wave passing through each active phase modulating portion.

The invention provides a silicon-on-insulator substrate and a preparation method thereof. The preparation method comprises the following steps: providing a first substrate and a second substrate; an insulating layer and at least one heat conduction structure located in the insulating layer are formed on the surface of at least one of the first substrate and the second substrate, each heat conduction structure comprises at least one first insulating heat conduction layer and at least one second insulating heat conduction layer, the heat conductivity of the first insulating heat conduction layer is larger than that of the insulating layer, and the heat conductivity of the second insulating heat conduction layer is larger than that of the second insulating heat conduction layer. The thermal conductivity of the second insulating heat-conducting layer is greater than that of the insulating layer; the first substrate and the second substrate are bonded, and the insulating layer and the heat conduction structure are located between the first substrate and the second substrate which are bonded; the second substrate is stripped to remove part of the second substrate, the remaining second substrate serves as a top semiconductor layer, and the first substrate serves as a base layer of the silicon-on-insulator substrate. The heat conduction structure is embedded in the insulating layer, heat of the top semiconductor layer is conducted to the base layer, and the heat dissipation performance of the silicon-on-insulator substrate is improved.

The invention discloses a mode division multiplexing device based on topological optimization and a mode division multiplexing circulating system, and relates to the field of photon integration and optical communication. The manufacturing method of the mode division multiplexing device comprises the following steps: dispersing the whole design area into adjustable material pixels, wherein the design area is silicon on insulator; determining a target function of a mode division multiplexing device by taking maximization of mode conversion efficiency as a target; by taking the objective function as an optimization objective, automatically updating the distribution of material pixels in the whole design area to obtain a quasi-optimal structure; and optimizing the pixels which cannot meet the manufacturing requirements in the optimal structure until the manufacturing requirements can be met. When a mode division multiplexing device is manufactured, an optimal structure can be automatically searched in a continuous or discrete material parameter space, so that a complex geometrical shape which is difficult to intuitively conceal can be excavated, and ultra-compact, low-loss, low-crosstalk, broadband and robust mode division multiplexing multifunctional photonic devices and the like can be realized in an extremely small size.

The invention concerns a hybrid optical device combining a silicon-on-insulator (SOI) waveguide platform (1) comprising a silicon waveguide (1a) with a thin-film electro-optical (EO) material such as lithium niobate or barium titanate forming a waveguide structure (2). The EO material waveguide structure (2) is bonded in optical contact with the SOI waveguide (1a), and electrodes (6) on its sides enable refractive index modulation via the electro-optical material Pockels effect. A coupling section (7), preferably comprising a tapered SOI waveguide (7a), transfers light between the SOI and EO structures with low loss. The device may include Bragg gratings (4a) or periodically poled sections (4b) in the EO layer for tunable or wavelength-selective modulation. The structure allows fast, reconfigurable light modulation, filtering, and signal routing on a CMOS-compatible platform, suitable for high-speed communication, optical computing, and sensing, offering a compact and efficient electro-optic integration solution.

This invention provides a multifunctional, compact, and high-precision pressure measurement device. The pressure-sensing module of the device employs a MEMS pressure core, with its core being an SOI (silicon-on-insulator) piezoresistive chip. The chip uses a flip-chip structure: the front side of the chip (the side with the piezoresistive circuitry) is fused to a glass cover plate wafer via anodic bonding or glass powder sintering, forming a sealed reference vacuum chamber or atmospheric reference chamber. The back side of the chip serves as the pressure-sensing surface, directly or through a pressure-transmitting medium contacting the pressure being measured. This device is suitable for miniaturized applications in high-temperature, high-pressure, small-volume, and strong electromagnetic interference environments.

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

The invention relates to a photonic component for setting non-volatile operational states, comprising: - At least one light-guiding structure (3) formed in a silicon layer of a silicon-on- insulator substrate (2); - At least one switching element (4) formed by an optical phase change material (8) and a heating structure (7) underneath thereof, wherein the at least one switching element (4) is laterally neighbored to the at least one light-guiding structure (3) so as to provide an evanescent coupling between the at least one light-guiding structure (3) and at least one switching element (4); wherein the heating structure (7) of the switching element (4) is formed by a thinned portion of the silicon layer (22) of the silicon-on-insulator-substrate (2) with the lowest silicon thickness to provide a current path through the silicon layer (22), particularly along the direction of arrangement of the at least one light-guiding structure (3) and the at least one switching element (4), so that the current density of the current path is highest in the heating structure (7) of the at least one switching element (4).

Methods and structures are presented for mitigating back-gating effects in radio frequency (RF) silicon-on-insulator (SOI) substrates, RF-SOI. According to an aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI beneath a first circuit / device to be protected. The first implant or junction is entirely contained within the TRL. A planar surface area of the first implant and / or junction entirely contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates a BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL beneath a second circuit / device. The first implant or junction and the second implant or junction are not connected and are separated by an undoped region of the TRL.

The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer, a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.

The present application discloses a silicon-on-insulator array waveguide grating chip for dense wavelength division multiplexing, which relates to the field of integrated silicon photonics technology. The chip includes an AWG and a wavelength thermal tuning structure. The AWG is composed of an input waveguide, a first slab waveguide, an array waveguide, a second slab waveguide, and an output waveguide connected in sequence along the optical path direction. The AWG is used to implement wavelength division multiplexing and demultiplexing. The wavelength thermal tuning structure includes a thermal tuning electrode and a metal electrode. The thermal tuning electrode is located above the array waveguide and is connected to an external control circuit via the metal electrode. The thermal tuning electrode is used to heat the array waveguide according to an external voltage to achieve wavelength tuning of the AWG channel. As the voltage amplitude increases, the heat generated by the thermal tuning electrode increases, and the wavelength of the AWG channel drifts toward a longer wavelength. The technical solution of the present application can realize multi-wavelength dense wavelength division multiplexing on a compact chip, has the advantages of small size and high reliability, and can realize passband wavelength control through the wavelength thermal tuning structure to meet the application requirements of multi-wavelength optical networks.

In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+ / intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 Å, respectively, so as to realize the flatness of the silicon-on-insulator film.

The present disclosure relates to methods, devices, systems, and techniques for forming semiconductor devices. An example semiconductor device includes a semiconductor layer and an insulating layer stacked on the semiconductor layer along a first direction. The semiconductor device further includes a first transistor and a second transistor. The first transistor includes a first gate structure and a first semiconductor body. The first semiconductor body is in contact with the insulating layer. The second transistor extends into the semiconductor layer along the first direction. The second transistor includes a second gate structure and a second semiconductor body. The second gate structure includes a dielectric layer aligned with the insulating layer along a second direction perpendicular to the first direction.

The invention provides a reconfigurable photonic crystal device for optical reasoning classification and an implementation method of the reconfigurable photonic crystal device. The reconfigurable photonic crystal device comprises a silicon-on-insulator substrate and photonic crystal units, wherein the photonic crystal units are constructed on the silicon-on-insulator substrate and are formed by first silicon columns which are periodically arranged in two-dimensional square lattices; the photonic crystal unit further comprises a defect structure formed by removing a whole row of first silicon columns in the center of the photonic crystal unit and a tunable defect silicon column which is located in the defect center of the defect structure and is integrated with a micro heater, and at least one second silicon column is distributed on the two sides of the tunable defect silicon column in the lattice direction. According to the reconfigurable photonic crystal device for optical reasoning and classification and the implementation method thereof, the refractive index of the tunable defective silicon column can be dynamically adjusted through the thermo-optic effect, independent regulation and control of optical signals with different wavelengths can be achieved, accurate control of transmitted spectrum and phase response can be achieved, multiple sets of programmable wavelength channels are formed, and the reconfigurable photonic crystal device is suitable for optical reasoning and classification. And on-chip integration of multi-wavelength parallel convolution, all-optical nonlinear activation and diffraction light field modulation can be synchronously realized.

The invention discloses a tunable high-Q Fano resonance sensor based on an asymmetric SOI (Silicon On Insulator) metasurface. The sensor adopts a periodic structure design, one unit structure is composed of a silicon dioxide substrate and a silicon dielectric layer, the silicon dioxide substrate is provided with an arrow-shaped structure composed of two parallelograms, and the arrow-shaped structure forms an asymmetric structure of the unit structure about the y axis by adjusting the angle theta of the two parallelograms. When incident light enters along the y axis, the designed sensor excites sharp Fano resonance in a near-infrared fluctuation section, and the Q value reaches 3407.39 by optimizing geometric parameters of the structure. The research shows that the structure has a relatively high Q value, and the designed structure is simple, easy to manufacture and relatively low in material cost, and has a potential application prospect in promoting an integrated photonic device in the aspect of nano-scale optical sensing.