34 results about "Silicon on insulator" patented technology

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: growing a polycrystalline silicon layer on a stripping surface of a current reused donor substrate, so as to form a supporting substrate; bonding the supporting substrate with a current donor substrate to be bonded through the polycrystalline silicon layer to form a current bonding wafer; performing stripping heat treatment operation on the current bonding sheet to obtain a silicon-on-insulator substrate and a reusable donor substrate; wherein the current reused donor substrate is a remaining part of a previous to-be-bonded donor substrate for preparing a previous silicon-on-insulator substrate after a previous stripping heat treatment operation. According to the preparation method, by utilizing the rough surface of the stripped substrate, the silicon-on-insulator substrate with excellent performance is provided under the condition that a reprocessing step of damaging the surface is avoided.

The invention provides a silicon-on-insulator substrate and a preparation method thereof. The preparation method comprises the following steps: executing first ion implantation to obtain a first donor substrate; bonding the first donor substrate and the first support substrate into a first bonding sheet; separating the first bonding sheet to form an intermediate substrate comprising a first top silicon layer; performing intermediate planarization processing on the intermediate substrate to form a planarized intermediate substrate; performing second ion implantation on the planarized intermediate substrate to form a second stripping plane in the first top silicon layer of the planarized intermediate substrate subjected to the second ion implantation; bonding the planarized intermediate substrate subjected to the second ion implantation with a second support substrate to form a second bonding sheet; separating the second bonding sheet to form a first silicon-on-insulator structure and a second silicon-on-insulator structure, the top silicon thickness of the first silicon-on-insulator structure being smaller than the top silicon thickness of the second silicon-on-insulator structure; and performing final planarization processing on the first silicon-on-insulator structure to form a target silicon-on-insulator substrate.

This invention provides a multifunctional, compact, and high-precision pressure measurement device. The pressure-sensing module of the device employs a MEMS pressure core, with its core being an SOI (silicon-on-insulator) piezoresistive chip. The chip uses a flip-chip structure: the front side of the chip (the side with the piezoresistive circuitry) is fused to a glass cover plate wafer via anodic bonding or glass powder sintering, forming a sealed reference vacuum chamber or atmospheric reference chamber. The back side of the chip serves as the pressure-sensing surface, directly or through a pressure-transmitting medium contacting the pressure being measured. This device is suitable for miniaturized applications in high-temperature, high-pressure, small-volume, and strong electromagnetic interference environments.

The invention relates to a photonic component for setting non-volatile operational states, comprising: - At least one light-guiding structure (3) formed in a silicon layer of a silicon-on- insulator substrate (2); - At least one switching element (4) formed by an optical phase change material (8) and a heating structure (7) underneath thereof, wherein the at least one switching element (4) is laterally neighbored to the at least one light-guiding structure (3) so as to provide an evanescent coupling between the at least one light-guiding structure (3) and at least one switching element (4); wherein the heating structure (7) of the switching element (4) is formed by a thinned portion of the silicon layer (22) of the silicon-on-insulator-substrate (2) with the lowest silicon thickness to provide a current path through the silicon layer (22), particularly along the direction of arrangement of the at least one light-guiding structure (3) and the at least one switching element (4), so that the current density of the current path is highest in the heating structure (7) of the at least one switching element (4).

The present disclosure relates to methods, devices, systems, and techniques for forming semiconductor devices. An example semiconductor device includes a semiconductor layer and an insulating layer stacked on the semiconductor layer along a first direction. The semiconductor device further includes a first transistor and a second transistor. The first transistor includes a first gate structure and a first semiconductor body. The first semiconductor body is in contact with the insulating layer. The second transistor extends into the semiconductor layer along the first direction. The second transistor includes a second gate structure and a second semiconductor body. The second gate structure includes a dielectric layer aligned with the insulating layer along a second direction perpendicular to the first direction.

A method for forming a semiconductor structure, comprising: providing a first silicon substrate and a second silicon substrate, the first silicon substrate comprising opposite first and second surfaces; subjecting the first silicon substrate to a thermal oxidation process to form an insulating oxide layer on the second surface of the first silicon substrate; implanting ions into the first surface of the first silicon substrate to form a sacrificial layer; bonding the second surface of the first silicon substrate to the second silicon substrate; and removing the sacrificial layer by a lift-off process to form a top silicon layer, the top silicon layer, the insulating oxide layer and the second silicon substrate forming a silicon-on-insulator substrate. The sacrificial layer in the first silicon substrate is removed by a lift-off process, compared with a separation process by high-temperature annealing in the prior art, the separation process effectively reduces the preparation cost, and can precisely control the thickness of the top silicon layer and ensure the uniformity of the surface of the top silicon layer.

The invention relates to a method for preparing a silicon-on-insulator substrate (S) comprising an electrical charge trapping layer (4) and having radio frequency and defectivity characteristics below predetermined thresholds. A thickness of the electrical charge trapping layer (4) is chosen to be strictly greater than 1 micrometre and less than 1.6 micrometres. The preparation method comprises a finishing sequence comprising an annealing step exposing the exposed face of the substrate to a neutral or reducing atmosphere for at least 30 minutes at a temperature strictly between 1050°C and 1100°C. According to the invention, the thickness of the electrical charge trapping layer (4) and the temperature of the annealing step are chosen so that the radio frequency and defectivity characteristics are below the respective predetermined thresholds.

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single-crystal silicon donor substrate; forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single-crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer; bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single-crystal silicon donor substrate, the handle structure including a single-crystal semiconductor handle substrate; and removing the single-crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The application discloses a MEMS pressure and temperature integrated sensor with electromagnetic interference resistance and a preparation method thereof. The sensor is sequentially provided with silicon-on-insulator, a first interlayer, a polysilicon protective layer, a second interlayer and a metal protective layer from bottom to top. The buried oxygen layer of the silicon-on-insulator realizes dielectric isolation of a sensing unit and a silicon substrate; a P-type piezoresistor of a device layer forms a Wheatstone bridge through a metal lead wire to constitute a pressure sensing unit; and a metal thin film resistor of the first interlayer constitutes a temperature sensing unit. The polysilicon protective layer is connected with the device layer in an equipotential manner to form a Faraday cage type closed electromagnetic shielding cavity, and the metal protective layer is provided with an array of air holes matched with air holes, which is used for pressure conduction and electromagnetic protection. The application improves the measurement stability in a complex electromagnetic environment through multiple electromagnetic interference resistance designs, realizes device miniaturization through an integrated structure, and can realize batch production based on a mature MEMS process.

Fabrication of avalanche photodiodes on a first wafer for operation in Geiger mode and integration with read-out integrated circuits (ROICs), fabricated on a second wafer, are described. Photodiode arrays are fabricated using a thin epitaxial layer grown on a semiconductor-on-insulator wafer. Chips are diced from the first wafer and bump bonded to chips diced from the second wafer.

The present invention relates to a gain cell EDRAM with extended capacitance, providing a gain cell memory device including a semiconductor device layer including a silicon-on-insulator substrate of an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region to isolate a first portion of the active region from a second portion of the active region, and a capacitor coupled with the storage transistor. A bottom plate of the capacitor includes the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor includes the gate electrode of the storage transistor and a metal structure over the gate electrode.

Methods for maintaining stable resistivity of a high resistivity silicon-on-insulator (HR-SOI) wafer are presented. The HR-SOI wafer includes a HR-Si substrate having a resistivity that is higher than about 1000 ohm. cm and a dopant concentration that is smaller than about 1013×cm-3. Packaging processing steps of the HR-SOI wafer are performed at a peak temperature that is below about 250 degrees centigrade. According to one aspect, a polyimidization processing step according to the present disclosure is performed at a peak temperature that is below about 250 degrees centigrade. According to another aspect, the packaging processing steps do not include the polyimidization processing step.

Embodiments of the present disclosure provide to a quantum radar apparatus based on NV-centers where, by default, each electromagnetic sensing element is built around one or alternatively two Field Effect Transistor (FET) on silicon over insulator, placed across a drain-source channel, and having their corner front-gate facing a NV-based nanostructure.

The invention provides a silicon-on-insulator substrate and a preparation method thereof. The silicon-on-insulator substrate comprises a support wafer; the silicon oxide layer is arranged on the supporting wafer; the stacked monocrystalline silicon layer is arranged on the silicon oxide layer; wherein the stacked monocrystalline silicon layer at least comprises a first sub monocrystalline silicon layer and a second sub monocrystalline silicon layer, and the first sub monocrystalline silicon layer and the second sub monocrystalline silicon layer are connected through a first silicon-silicon bonding interface without a dielectric layer. The silicon-on-insulator substrate has the advantages of both thickness and uniformity, and breaks through the technical bottleneck existing in the industry. According to the silicon-on-insulator substrate provided by the embodiment of the invention, the thickness can be accumulated by stacking the sub monocrystalline silicon layers with relatively good uniformity, so that the thickness required by a high-voltage device and the high-precision uniformity required by large-scale manufacturing are structurally integrated.

The invention relates to a method for preparing a silicon-on-insulator substrate (S) comprising an electrical charge trapping layer (4) and exhibiting radio frequency and defect characteristics below predetermined thresholds. The thickness of the electrical charge trapping layer (4) is chosen to be strictly greater than 1 micrometer and less than 1.6 micrometers. The preparation method includes a finishing sequence comprising an annealing step exposing the exposed face of the substrate to a neutral or reducing atmosphere for at least 30 minutes at a temperature strictly between 1050°C and 1100°C. According to the invention, the thickness of the electrical charge trapping layer (4) and the temperature of the annealing step are chosen so that the radio frequency and defect characteristics are below the respective predetermined thresholds. No figure

Method for manufacturing a silicon-on-insulator substrate. This description relates to a method for manufacturing a silicon-on-insulator substrate comprising the successive steps of: a) forming a silicon-germanium layer on an upper surface of a silicon substrate (10); b) forming a silicon layer (20) on an upper surface of the silicon-germanium layer; c) forming at least one opening (28) through the silicon layer (20) and into the silicon-germanium layer; d) selectively removing at least a portion of the silicon-germanium layer through the opening (28) so as to create a cavity between the silicon substrate (10) and the silicon layer (20); and e) filling the cavity, through the opening (28), with an insulating material (32). Figure for the abstract: Fig. 11

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: carrying out the ion beam planarization processing of the top silicon of a silicon-on-insulator intermediate, so as to obtain the silicon-on-insulator substrate, the ion beam planarization treatment comprises the following steps: determining reference thermal deformation of the silicon-on-insulator intermediate caused in the process of performing ion beam planarization treatment on top silicon of the silicon-on-insulator intermediate by an ion beam with reference treatment parameters; according to the reference thermal deformation of the silicon-on-insulator intermediate and the difference between the initial morphology and the target morphology of the top silicon before ion beam planarization processing, determining a design film thickness removal amount matrix for scanning and etching the top silicon of the silicon-on-insulator intermediate; and according to the designed film thickness removal amount matrix, carrying out scanning etching on the top silicon of the silicon-on-insulator by adopting an ion beam so as to obtain a silicon-on-insulator substrate of which the thickness deviation of the top silicon is smaller than a preset threshold value.

A germanium-on-silicon avalanche photodetector includes a silicon device layer of a silicon-on-insulator substrate having a central region characterized by modest-heavy n+ doping state between a first electrode region and a second electrode region in heavy n++ doping state; a first sub-layer of the central region modified to nearly neutral doping state and located from a first depth down to a second depth below a top surface of the silicon device layer; a second sub-layer of the central region modified to modest p doping state embedded from the top surface down to the first depth to interface with the first sub-layer; a layer of germanium with a bottom side attached to the top surface of the second sub-layer; and a third sub-layer embedded into a top side of the layer of germanium, characterized by heavy p++ doping state.

This invention belongs to the field of electric field sensing technology, specifically disclosing a micro electric field sensor based on silicon-on-insulator (SOI) and its fabrication method. The sensor, from top to bottom, includes a piezoelectric block, a SOI structural layer, and a supporting substrate. The SOI structural layer comprises a substrate layer, an insulating layer, a device layer, and metal electrodes. The substrate layer has a hollow structure, and the four protrusions of the device layer form a peninsula beam membrane structure. The piezoresistive elements in the region of maximum strain form a Wheatstone bridge. After sensing an external electric field, the piezoelectric block drives the peninsula beam membrane to vibrate based on the inverse piezoelectric effect, and the Wheatstone bridge converts the mechanical strain into an electrical signal. The fabrication method uses an SOI wafer as the substrate and completes the process through photolithography, ion implantation, etching, and bonding. This invention improves stress concentration and sensing efficiency, while also possessing low power consumption and MEMS process compatibility. It exhibits excellent measurement accuracy and stability, making it suitable for scenarios such as power transmission and transformation equipment monitoring.

A method for forming a semiconductor structure comprises: providing a first silicon substrate, a second silicon substrate and a third silicon substrate; performing a thermal oxidation process on the first silicon substrate to form a first insulating oxide layer and a second insulating oxide layer; implanting ions into the first silicon substrate to form a first top layer of silicon, a second top layer of silicon and a sacrificial layer between the first top layer of silicon and the second top layer of silicon; using a bonding process, bonding a first surface of the first silicon substrate to the second silicon substrate and the third silicon substrate respectively; removing the sacrificial layer to expose a surface of the first top layer of silicon and a surface of the second top layer of silicon, the first top layer of silicon, the first insulating oxide layer and the second silicon substrate forming a first silicon-on-insulator substrate, and the second top layer of silicon, the second insulating oxide layer and the third silicon substrate forming a second silicon-on-insulator substrate. The method forms two silicon-on-insulator substrates after a thermal oxidation process, ion implantation and bonding process, thereby improving the efficiency of the semiconductor process.

The present application relates to radio frequency silicon on insulator structures with superior performance, stability and manufacturability. A semiconductor-on-insulator (e.g., silicon-on-insulator) structure with superior radio frequency device performance and a method of making such a structure are provided by utilizing single crystal silicon handle wafers sliced from float zone grown single crystal silicon ingots.

This disclosure relates to methods, devices, systems, and techniques for forming semiconductor devices. An example semiconductor device includes a semiconductor layer and an insulating layer stacked on the semiconductor layer along a first direction. The semiconductor device also includes a first transistor and a second transistor. The first transistor includes a first gate structure and a first semiconductor body. The first semiconductor body is in contact with the insulating layer. The second transistor extends into the semiconductor layer along the first direction. The second transistor includes a second gate structure and a second semiconductor body. The second gate structure includes a dielectric layer aligned with the insulating layer along a second direction perpendicular to the first direction.

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: providing a donor substrate and a supporting substrate, the donor substrate is provided with an ion implantation layer, and a first oxide layer is formed on the surface of the donor substrate; depositing a charge trapping layer on the surface of the supporting substrate at a first temperature, wherein the charge trapping layer is a nitrogen-containing dielectric material layer; performing heat treatment on the support substrate deposited with the charge trapping layer at a second temperature, wherein the second temperature is higher than the first temperature; bonding the side, provided with the first oxide layer, of the donor substrate with the side, provided with the charge trapping layer, of the supporting substrate to form a bonding structure; the donor substrate is peeled off along the ion implantation layer, a part of the donor substrate is transferred to the supporting substrate, an insulating buried layer and top silicon are formed on the supporting substrate, and the insulating buried layer comprises the charge trapping layer and the first oxide layer which are stacked.

The application discloses a DSOI wafer preparation method for pseudo-MOS characterization, and the method comprises the following steps: providing a plurality of original wafers, respectively preparing corresponding bottom wafers and top wafers by using the original wafers, preparing a double buried oxygen silicon-on-insulator (DSOI) wafer with a pseudo-MOS characterization structure by using the bottom wafers and the top wafers, and performing layer-by-layer etching and metal electrode etching on a step structure of the DSOI wafer with the pseudo-MOS characterization structure, so as to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization. By using the application, the problem that the interface characteristics are less in the prior art based on an SOI process for supporting characterization of a pseudo-MOS characterization structure is solved, and the interface characteristic parameter characterization of multiple interfaces is realized.

A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

This invention provides a novel silicon-on-insulator (SOI) wafer and its fabrication method. The fabrication method of the novel SOI wafer of this invention includes the following steps: S1: Fabricating a TRL or porous silicon on a silicon wafer and implanting hydrogen to form a hydrogen-implanted silicon wafer; S2: Growing SiO2 on a substrate as BOX2, flipping the hydrogen-implanted silicon wafer and bonding it to BOX2 at low temperature; S3: After high-temperature peeling, growing SiO2 on the TRL or porous silicon as BOX1; S4: Implanting hydrogen into the silicon wafer, then flipping it and bonding it to BOX1 at low temperature, followed by high-temperature peeling to form SOI, thus obtaining the novel SOI wafer. The novel SOI wafer of this invention has a lower back-gate leakage current capability.

This invention relates to the field of optical refractive index sensing technology, and discloses a biatomic lattice metasurface and a method for fabricating a refractive index sensor. Two cubic lattices are nested together to form a biatomic lattice. Symmetry breaking is achieved by applying a micro-perturbation in the y-direction to one sublattice, creating a resonant structure. This structure is then placed on a silicon-on-insulator substrate to form a biatomic lattice metasurface. The metasurface is then transferred from the silicon-on-insulator substrate to a target substrate with a refractive index matching that of the solution being measured using a water-floating method. This creates a symmetrical dielectric environment, suppressing the leakage of electric field energy to the high-refractive-index substrate, increasing the proportion of electric field energy in the environmental medium, and thus improving the refractive index sensing sensitivity.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single crystal silicon donor substrate, forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer, bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure, the handle structure including a single crystal semiconductor handle substrate, to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single crystal silicon donor substrate, and removing the single crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The present application relates to a silicon-on-insulator semiconductor component including a substrate, a buried dielectric layer, a first electrode, a second electrode, and a drift region, the buried dielectric layer being disposed on the substrate, the drift region being disposed on the buried dielectric layer, a stepped structure formed on an upper surface of the drift region, the stepped structure including a first side proximate to the first electrode, a second side proximate to the second electrode, and a transition region between the first and second sides, the upper surface of the second side being higher than the lower surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side, and the first and second electrodes being configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.