353 results about "Direct bonding" patented technology

The invention discloses a long-term vacuum maintenance type Fabry-Perot cavity and a preparation method thereof. An annular gasket is clamped between two reflecting lenses to directly bond in a vacuum environment through Van der Waals force, a vacuum core cavity which is permanently sealed and is vacuum in the air is formed, the vacuum core cavity is fixedly placed in a glass sleeve, and the two ends of the glass sleeve are sealed through an ultraviolet light adhesive bonding interface by adopting optical window pieces. After the interior of the glass sleeve is vacuumized through the exhaust pipe, the glass sleeve is sealed through local heating sintering, and a two-stage vacuum barrier is formed; the Fabry-Perot cavity is long in vacuum holding time and small in size, and does not need to be externally connected with a vacuum pump to maintain vacuum; the device is simple, and the vacuum degree of the Fabry-Perot cavity can be maintained for more than two years under the condition that the processing difficulty is not improved.

Methods for fabricating branched substrates having conductive contact pads and hybrid dielectric bonding surfaces for directly bonding dies and electrically connecting them to the contact pads. A branched substrate can include a main portion and one or more branch portions hybrid bonded to the main portion. Some sections of the branched substrate can be flexible to allow deformable electrical connection between components that are hybrid bonded to different regions of the branched substrate. A flexible branch portion may provide electrical connection between vertically separated layers of two components. The method includes directly bonding a branch portion of the branched substrate to the main portion of the branched substrate via a hybrid bonding interface comprising a conductive interface between contact pads of the main and branch portions and a hybrid bonded dielectric interface between dielectric surfaces of the of the main and branch portions.

Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

A method for fabricating a MEMS device comprising the following steps: providing a first bonding surface (1) on a first substrate (2) with a first substrate doping; providing a second bonding surface (3) on a second substrate (4) with a second substrate doping; aligning and joining the first and second bonding surfaces (1, 3) by a Si-Si direct bonding process, wherein both bonding surfaces (1, 3) have a silicon surface, and wherein an additional near-surface first doping layer (5) is produced below at least one of the bonding surfaces (1).

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and / or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds. The example techniques can direct-bond lithium tantalate LiTaO3 to various conventional substrates in a process for making various novel optical and acoustic devices.

The invention provides a large-size semiconductor wafer and a preparation method and application thereof. The preparation method comprises the following steps: selecting a plurality of first semiconductor wafers, and modifying the first semiconductor wafers to obtain second semiconductor wafers; wherein the crystal orientation error of the first semiconductor wafer is smaller than a set error value, and the surface roughness of the second semiconductor wafer is smaller than set roughness; performing wafer alignment on the second semiconductor wafer along the crystal orientation, and performing direct bonding along the splicing surface at a set temperature to obtain a bonded wafer; performing post-processing on the bonded wafer to obtain a large-size semiconductor wafer; wherein the size of the large-size semiconductor wafer is at least larger than the sizes of the two first semiconductor wafers; the set temperature is less than 300 DEG C. According to the invention, direct bonding without an intermediate layer can be realized, and a semiconductor wafer which is continuous in structure, matched in crystal orientation and excellent in thermal performance is obtained; the process does not need an epitaxial process, and the process complexity and cost are reduced.

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

The invention relates to the technical field of pressure sensors, and provides a pressure sensor and a preparation method thereof. The pressure sensor comprises an upper pole plate, a pressure sensing film and a metal base. The upper pole plate is made of an aluminum oxide crystal material; the pressure sensing film is made of an aluminum oxide crystal material and is arranged on one side of the upper polar plate, and the pressure sensing film and the upper polar plate form a capacitor structure; the metal base is arranged on one side, deviating from the upper polar plate, of the pressure-sensitive film and used for supporting the upper polar plate and the pressure-sensitive film; wherein the upper pole plate is provided with a pole plate gap, the upper pole plate is in direct bonding connection with the pressure sensing film, and the pressure sensing film is in direct bonding connection with the metal base. The high-temperature-resistant corrosion-resistant pressure sensor overcomes the defects that in the prior art, a pressure sensor is prone to generating stress in a high-temperature environment, so that the zero-bias stability of the sensor is poor, and the precision is reduced after long-term use, and the high-temperature-resistant corrosion-resistant pressure sensor is achieved.

Aspects disclosed in the detailed description include an impure Indium Phosphide (InP) semiconductor substrate. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a semiconductor substrate comprising a silicon layer and an impure InP layer adjacent to the silicon layer. The impure InP layer may be epitaxially grown on a Silicon (Si) nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Utilizing an impure InP layer advantageously provides structural strength to be deployed in a 300 millimeter wafer process while achieving the electrical and thermal characteristic of InP it provides in a semiconductor substrate.

An integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening; and an outlet opening. The top portion, the sidewalls, the divider and the backside of the semiconductor device collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening. A channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in in the same direction; and a portion of the first coolant channel is disposed above a hotspot region of the semiconductor device.

Embodiments herein provide for probe cards and methods related thereto. A probe card comprises a probe and a substrate. The probe comprises a probe stand, a probe beam, and a probe tip. The probe tip and probe stand extend in a first direction, and the probe beam extends in a second direction different than the first direction. The substrate comprises a conductive feature disposed in a material layer. The probe stand of the probe is directly bonded to the conductive feature of the substrate via direct metal bonds.

The invention provides a DBA ceramic substrate low-temperature brazing manufacturing method based on laser surface modification, and relates to the technical field of brazing, the DBA ceramic substrate low-temperature brazing manufacturing method based on laser surface modification comprises the following steps: constructing a micro-nano groove in the surface of an aluminum nitride ceramic substrate through femtosecond laser; al particles are subjected to magnetron sputtering on the surface of the aluminum nitride ceramic substrate with the micro-nano grooves; and the Al-Si eutectic brazing filler metal is selected for brazing the aluminum nitride ceramic substrate and the aluminum material. Micro-nano grooves are constructed in the surface of the aluminum nitride ceramic substrate through femtosecond laser, and surface activation of the aluminum nitride ceramic substrate is achieved; al particles are subjected to magnetron sputtering on the surface of the aluminum nitride ceramic substrate with the micro-nano grooves, direct bonding of the aluminum material and AlN is promoted, meanwhile, Al-N-Al bonds are formed, connection of the aluminum material and AlN ceramic can be achieved through low-temperature brazing, the joint strength reaches 110 MPa, and the heat conductivity coefficient reaches 220 W / (m.K).

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.

A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provide a bonded structure with reliable electrical contacts.

A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

Integrated circuit ("IC") structures and electronic packages that utilized an inorganic-convertible polymer to improve bond strength and thermal conductivity are described. In one embodiment, the inorganic-convertible polymer acts as a side fill material to seal a die periphery and improve direct bonding strength. In another embodiment, the inorganic-convertible polymer acts as a thermal bonding layer to increase the thermal conductivity between a die and a thermal solution.

Fluid-cooled power modules (90) are disclosed, in which high power semiconductor chips (204) are mounted on direct bonded metal (DBM) structures (209 / 709) implemented with various cooling options. Such fluid-cooled power modules (90) are suitable for use in electric vehicles or industrial applications. A cooling unit (500) can be attached to the DBM structure (209 / 709), to provide a flow (120) of cooling fluid that can be routed through a heat sink (215 / 415 / 425), or through channels formed in different layers of the DBM structure (209 / 709). A fluid pipe (1320) can route coolant through an encapsulant (101), to surround the semiconductor chips (204) on multiple sides. A pair of DBMs can be included to provide double-sided cooling, or to accommodate multiple arrays of chips (204).

This application discloses a method and device for fabricating a periodically polarized ultrathin lithium niobate / lithium tantalate device, belonging to the field of nonlinear optical device manufacturing. The method includes: fabricating and polarizing periodic electrodes on a provided ferroelectric crystal wafer to form a periodically polarized master wafer; bonding the master wafer to a carrier substrate using optical resin-assisted bonding or direct bonding to form a composite structure; thinning and polishing the side of the master wafer away from the carrier substrate to obtain an ultrathin periodically polarized crystal functional layer; and fabricating the structure of the ultrathin periodically polarized crystal functional layer to obtain a periodically polarized ultrathin lithium niobate / lithium tantalate device. This method avoids the inherent problems of high-voltage breakdown and poor domain quality in existing technologies when directly polarizing ultrathin crystals by placing the high-risk polarization step on a thick, stable wafer.

The disclosure is related to structures and method of making thermoelectric devices. The structures include an electrically nonconductive and thermally conductive substrate with direct bonded or electroplated copper. Thermoelement pairs are formed on a barrier layer deposited on the outer layers of the substrate in gaps formed from insulator material deposited on the barrier layer. Openings in the barrier layer may be filled with an insulator to isolate thermoelements, which may then be bridged by a metal layer. Thermoelement pairs may be combined to form larger devices.

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

This invention provides a directly coupled stacked structure for improved image quality in optical devices. [Solution] Optical surfaces are planarized and plasma activated to laminate them together, and then a direct bond is formed between the two surfaces without adhesive or an adhesive layer. This process provides an improved optical element with higher image brightness, lower light scattering, better resolution, and higher image fidelity. Direct bonding also provides a heat-resistant interface that can withstand much higher temperatures than conventional optical adhesives. Exemplary processes can be used to manufacture many types of improved optical components such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and specular waveguides for smart glasses and head-up displays (HUDs), which provide better image quality and elimination of dark lines of sight that are apparent to the human observer when conventional adhesives are used in conventional lamination.

A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding.

The utility model discloses a test device for verifying the influence of epoxy glue high-temperature gas release on a gold-aluminum bonding point, which comprises a shell, the inner wall of the shell is provided with a gold-plated layer, and the thickness of the gold-plated layer is 1-5 microns; the edge of the chip is bonded on the inner wall of the shell through a plurality of gold bonding wires; an epoxy glue layer is coated on the part, which is not bonded with the chip, of the inner wall of the shell; the cover plate is installed at the opening of the shell in a sealed mode. The inner wall of the shell is provided with the gold-plated layer, and the chip can be directly bonded on the gold-plated layer in the shell, so that the test process is free from interference of external factors. The shell is made of ceramic, the main component of the ceramic is Al2O3, the high-temperature resistance is excellent, excessive gas and stress release are avoided in the test process, and the interference to the test result is avoided. The airtight grade in the shell is 10-9, and the sealing requirement is met. In the test process, gas released by the epoxy glue layer cannot leak and can continuously act on the bonding points, and the test effect can be improved.

A method for bonding semiconductor dies, resulting semiconductor devices, and associated systems and methods are disclosed. In some embodiments, the method includes depositing a first material on the first semiconductor die. The first material has a first outer surface and a first chemical composition at the first outer surface. The method also includes depositing a second material on the second semiconductor die. The second material has a second outer surface and a second chemical composition at the second outer surface that is different from the first chemical composition. The method also includes stacking the dies. The second outer surface of the second semiconductor die is in contact with the first outer surface of the first semiconductor die in the stack. The method also includes reacting the first outer surface with the second outer surface. The reaction causes the first outer surface to bond to the second outer surface.

A method for bonding chips including the following steps: a) providing a donor substrate wherein chips are formed, the donor substrate including a front face and a back face, b) mounting the front face of the donor substrate to a temporary substrate, by direct bonding, c) preferably thinning the donor substrate, d) bonding the assembly consisting of donor substrate and temporary substrate on a handling device including a solid frame and an adhesive film, with the back face of the donor substrate bonded to the adhesive film, e) separating the temporary substrate from the donor substrate, f) cutting the donor substrate so as to singularize the chips, g) bonding the chips to the receiver substrate by direct bonding.

Semiconductor component manufacturing process, including: a step which provides a wafer source (1) having a first principal surface (2) on one side and a second principal surface (3) on the other side, and a first support element (11) and a second support element (21); a support step with a first support step in which the wafer source (1) is supported on the side of the first main surface (2) by the first support element (11), and with a second support step in which the wafer source (1) is supported on the side of the second main surface (3) by the second support element (21), wherein the second support step includes bonding a first plate surface (22) of the second support element (21) to the second main surface (3) of the wafer source (1) by a direct bonding process, and wherein a second amorphous bond layer (32) is formed between the second main surface (3) and the first plate surface (22) after bonding, the procedure further features: a step of forming a modified layer (33) in which a modified layer (33) is formed along a horizontal direction parallel to the first principal surface (2) in a thickness-direction intermediate section of the wafer source (1); and a wafer separation step in which a wafer structure (35) containing the second support element (21) and a wafer (34) is separated from the wafer source (1) by means of the modified layer (33), wherein the wafer structure (35) with the second support element (21) and the wafer (34) includes the second amorphous bond layer (32) which bonds the second support element (21) and the wafer (34), and wherein the second amorphous bond layer (32) is formed as a starting point for separating the second support element (21) and the wafer (34) in a subsequent step.

The invention relates to a method of directly bonding (200) a first microelectronic device (100) on a second microelectronic device, comprising: providing a first device having a first flat surface (110) and a second device having a second flat surface (210), at least the first and second surfaces are treated with a plasma gas comprising at least a first fluorine-containing gas (having an atomic percentage F of fluorine), the first and second devices are transferred to a bonding apparatus, the first and second surfaces are immersed in a bonding atmosphere (1), and the first and second surfaces are bonded under the bonding atmosphere. By cooperatively controlling the atomic percentage F of fluorine and the relative humidity RH, the bonding speed Vc is less than or equal to 15 mm / s, more particularly less than 10 mm / s. The reduced bonding speed significantly reduces the deformation in the bonding process, and can obtain sufficiently high bonding energy, thereby ensuring good bonding between the two surfaces.