450 results about "Direct bonding" patented technology

A semiconductor package includes semiconductor chips each including at least one of a front insulating layer or a rear insulating layer, the semiconductor chips bonded to each other through direct bonding between the front insulating layer and the rear insulating layer. At least one of the semiconductor chips includes a device layer including an interconnection structure, and a conductive pattern on a front surface of the device layer. The conductive pattern includes pad patterns electrically connected to the interconnection structure, and a dummy pattern spaced apart from the pad patterns. The dummy pattern includes first dummy patterns between the pad patterns to overlap the pad patterns in a first direction, and a second dummy patterns between the first dummy patterns to overlap the pad patterns in the second direction. The second dummy patterns are spaced apart from the first dummy patterns.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

The invention discloses a long-term vacuum maintenance type Fabry-Perot cavity and a preparation method thereof. An annular gasket is clamped between two reflecting lenses to directly bond in a vacuum environment through Van der Waals force, a vacuum core cavity which is permanently sealed and is vacuum in the air is formed, the vacuum core cavity is fixedly placed in a glass sleeve, and the two ends of the glass sleeve are sealed through an ultraviolet light adhesive bonding interface by adopting optical window pieces. After the interior of the glass sleeve is vacuumized through the exhaust pipe, the glass sleeve is sealed through local heating sintering, and a two-stage vacuum barrier is formed; the Fabry-Perot cavity is long in vacuum holding time and small in size, and does not need to be externally connected with a vacuum pump to maintain vacuum; the device is simple, and the vacuum degree of the Fabry-Perot cavity can be maintained for more than two years under the condition that the processing difficulty is not improved.

Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

Methods for fabricating branched substrates having conductive contact pads and hybrid dielectric bonding surfaces for directly bonding dies and electrically connecting them to the contact pads. A branched substrate can include a main portion and one or more branch portions hybrid bonded to the main portion. Some sections of the branched substrate can be flexible to allow deformable electrical connection between components that are hybrid bonded to different regions of the branched substrate. A flexible branch portion may provide electrical connection between vertically separated layers of two components. The method includes directly bonding a branch portion of the branched substrate to the main portion of the branched substrate via a hybrid bonding interface comprising a conductive interface between contact pads of the main and branch portions and a hybrid bonded dielectric interface between dielectric surfaces of the of the main and branch portions.

Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

In an embodiment, a semiconductor device may include an interposer. The semiconductor device may also include a plurality of chiplets directly bonded to the interposer. The device may furthermore include a plurality of interposer dies directly bonded to the interposer adjacent to the plurality of chiplets, the plurality of interposer dies having through-substrate vias. The device may additionally include a memory package over and bonded to at least one of the plurality of interposer dies.

Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

A method for fabricating a MEMS device comprising the following steps: providing a first bonding surface (1) on a first substrate (2) with a first substrate doping; providing a second bonding surface (3) on a second substrate (4) with a second substrate doping; aligning and joining the first and second bonding surfaces (1, 3) by a Si-Si direct bonding process, wherein both bonding surfaces (1, 3) have a silicon surface, and wherein an additional near-surface first doping layer (5) is produced below at least one of the bonding surfaces (1).

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.

A method of bonding substrates comprises depositing a fluorine-doped dielectric layer on a first substrate, exposing the fluorine-doped dielectric layer to a hydrogen-containing plasma, and directly bonding the fluorine-doped dielectric layer to a surface of a second substrate without the use of an intervening adhesive.

Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and / or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds. The example techniques can direct-bond lithium tantalate LiTaO3 to various conventional substrates in a process for making various novel optical and acoustic devices.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

The invention provides a large-size semiconductor wafer and a preparation method and application thereof. The preparation method comprises the following steps: selecting a plurality of first semiconductor wafers, and modifying the first semiconductor wafers to obtain second semiconductor wafers; wherein the crystal orientation error of the first semiconductor wafer is smaller than a set error value, and the surface roughness of the second semiconductor wafer is smaller than set roughness; performing wafer alignment on the second semiconductor wafer along the crystal orientation, and performing direct bonding along the splicing surface at a set temperature to obtain a bonded wafer; performing post-processing on the bonded wafer to obtain a large-size semiconductor wafer; wherein the size of the large-size semiconductor wafer is at least larger than the sizes of the two first semiconductor wafers; the set temperature is less than 300 DEG C. According to the invention, direct bonding without an intermediate layer can be realized, and a semiconductor wafer which is continuous in structure, matched in crystal orientation and excellent in thermal performance is obtained; the process does not need an epitaxial process, and the process complexity and cost are reduced.

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

The invention relates to the technical field of pressure sensors, and provides a pressure sensor and a preparation method thereof. The pressure sensor comprises an upper pole plate, a pressure sensing film and a metal base. The upper pole plate is made of an aluminum oxide crystal material; the pressure sensing film is made of an aluminum oxide crystal material and is arranged on one side of the upper polar plate, and the pressure sensing film and the upper polar plate form a capacitor structure; the metal base is arranged on one side, deviating from the upper polar plate, of the pressure-sensitive film and used for supporting the upper polar plate and the pressure-sensitive film; wherein the upper pole plate is provided with a pole plate gap, the upper pole plate is in direct bonding connection with the pressure sensing film, and the pressure sensing film is in direct bonding connection with the metal base. The high-temperature-resistant corrosion-resistant pressure sensor overcomes the defects that in the prior art, a pressure sensor is prone to generating stress in a high-temperature environment, so that the zero-bias stability of the sensor is poor, and the precision is reduced after long-term use, and the high-temperature-resistant corrosion-resistant pressure sensor is achieved.

Aspects disclosed in the detailed description include an impure Indium Phosphide (InP) semiconductor substrate. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a semiconductor substrate comprising a silicon layer and an impure InP layer adjacent to the silicon layer. The impure InP layer may be epitaxially grown on a Silicon (Si) nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Utilizing an impure InP layer advantageously provides structural strength to be deployed in a 300 millimeter wafer process while achieving the electrical and thermal characteristic of InP it provides in a semiconductor substrate.

A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

The utility model discloses a stainless steel air-conditioning ventilating duct which comprises a body fixing part, a stainless steel air-conditioning ventilating duct body and a stainless steel air-conditioning ventilating duct body. The sound insulation component comprises a supporting pipeline, sound insulation cotton, a limiting buckle, a clamping plate, a limiting clamping groove and a limiting groove; the middle of the pipeline shell is a cavity, the outer surface of the supporting pipeline is connected with sound insulation cotton in a bonding mode, limiting clamping grooves are evenly formed in the front end and the rear end of the outer surface of the sound insulation cotton, and the clamping plates are evenly installed at the front end and the rear end of the outer surface of the supporting pipeline. The limiting buckles are connected into the limiting clamping grooves in a buckled mode. The utility model relates to a ventilation pipeline, in particular to a ventilation pipeline, and aims to solve the problems that when an existing ventilation pipeline is actually used, the pipeline has a sound insulation effect, sound insulation cotton is generally mounted in the pipeline in a direct bonding manner, the bonding property of the sound insulation cotton is reduced along with the increase of time, and the sound insulation cotton in the pipeline is warped, so that the sound insulation property of the pipeline is reduced.

Provided is a proximity sensor capable of sufficiently extending a detection distance by suppressing an influence of embedded metal. A coil of a proximity sensor includes a first coil and a second coil. The second coil is disposed concentrically with the first coil. The proximity sensor detects a detection object on the basis of a change in voltage or current generated in each of the first coil and the second coil. The coil wire of the first coil is electrically connected to the in-head substrate through direct bonding.

An integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening; and an outlet opening. The top portion, the sidewalls, the divider and the backside of the semiconductor device collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening. A channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in in the same direction; and a portion of the first coolant channel is disposed above a hotspot region of the semiconductor device.

Dies and / or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Embodiments herein provide for probe cards and methods related thereto. A probe card comprises a probe and a substrate. The probe comprises a probe stand, a probe beam, and a probe tip. The probe tip and probe stand extend in a first direction, and the probe beam extends in a second direction different than the first direction. The substrate comprises a conductive feature disposed in a material layer. The probe stand of the probe is directly bonded to the conductive feature of the substrate via direct metal bonds.