216 results about "Metallic bonding" patented technology

A semiconductor element is provided with a micro-structured metal oxide layer over a conductive feature at a hybrid bonding surface. The micro-structured metal oxide layer comprises fine metal oxide grains, such as nanograins. The grains can be formed over the conductive feature by oxidizing a metal comprised in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the micro-structured metal oxide layer can form strong bonds at the bonding interface at substantially reduced annealing temperature.

The invention provides a light-emitting diode chip and a preparation method thereof, and the light-emitting diode chip comprises a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulation protection layer, a P-type conductive metal layer, a P-type reflection metal layer, a current blocking layer, a current expansion layer, and an epitaxial layer which are stacked from bottom to top. The projection of the edge of the P-type conductive metal layer on the current expansion layer is located in the projection of the isolation groove on the current expansion layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current expansion layer and the projection of the edge of the isolation groove on the current expansion layer to the width of the isolation groove is 1 / 3-2 / 3. The isolation groove and the cutting wall are arranged on the current expansion layer, and the distance proportion relation between the edge of the P-type conductive metal layer and the isolation groove is favorable for controlling the distribution of current in the light-emitting diode chip, so that the current is prevented from being excessively concentrated, the current is more uniformly expanded to the epitaxial layer, and the overall light-emitting efficiency and stability of the light-emitting diode chip are improved.

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing two wafers to be mixed and bonded; forming a bonding layer; etching the metal layer of the first wafer to enable the surface of the metal layer to be lower than the surface of the dielectric layer; forming a nano bridge metal layer on the surface of the metal layer of the first wafer; forming a nano bridge dielectric layer; bonding the first wafer and the second wafer; leading out a metal connecting piece; and applying voltage by using the metal connecting pieces so as to conduct the nano-bridge dielectric layer between the metal layers. According to the invention, the nanometer bridge structure is formed in the metal bonding area of the first wafer and the second wafer, so that metal bonding is realized by using the nanometer bridge structure under a power-on condition, metal layers do not need to be bonded by using annealing thermal expansion, and the height of the metal layers relative to a dielectric layer and the surface pattern of the metal layers do not need to be strictly controlled; and high-temperature annealing is not needed, so that the process difficulty is reduced, the performance of the device is ensured, and the problems of high difficulty and influence on the performance of the device in the existing mixed bonding process method are solved.

The invention discloses a solar cell with alloy as a flexible substrate and a preparation method thereof, a kovar alloy sheet is used as the flexible substrate to be bonded with an epitaxial layer, the coefficient of thermal expansion of the kovar alloy sheet is similar to that of an epitaxial material, and dark cracks of the epitaxial layer caused by cold and hot temperature difference are avoided; moreover, the metal bonding layer adopts a thick-silver thin-gold structure taking silver as a substrate, so that the production cost is greatly reduced, and the weldability of the back electrode is enhanced; and the back electrode also adopts a thick silver and thin gold structure taking silver as a substrate, so that the front warping of the Kovar alloy sheet can be balanced, the weldability of the back electrode is enhanced, the drawing force of the back electrode is improved, the thin gold plated on the thick silver can also prevent silver oxidation and resist the impact of atomic oxygen, and the service life of the solar cell is prolonged.

A device structure includes: an interposer including interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads; at least one semiconductor die having formed therein in-die bonding pads that are bonded to a respective one of the die-side interposer bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die. The composite die frame includes a molding compound die frame portion including a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and including a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.

A bulk acoustic wave (BAW) resonator includes: a substrate; a piezoelectric layer disposed above the substrate; a first electrode disposed below the piezoelectric layer and including a first portion and a second portion spaced apart from each other; a second electrode disposed above the piezoelectric layer; a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially disposed between the substrate and the piezoelectric layer in an order from the piezoelectric layer to the substrate; a cavity disposed below the first portion of the first electrode; a metal bonding layer disposed between the third dielectric layer and the substrate; and a ground pad metal layer disposed on the piezoelectric layer and electrically connected to the metal bonding layer.

The invention relates to the technical field of semiconductor photoelectrons, and discloses a vertical-cavity surface-emitting laser with an inverted structure and a preparation method of the vertical-cavity surface-emitting laser. The vertical cavity surface emitting laser with the inverted structure comprises a heterogeneous substrate, wherein a heat dissipation functional layer, a metal adhesion layer and a metal bonding layer are arranged on the surface of the heterogeneous substrate from bottom to top; the epitaxial structure comprises a p-type electrode, an ITO current expansion layer, a SiO2 current limiting layer, a first dielectric DBR layer, a p-type GaN layer, an electron blocking layer, a quantum well active region, an n-type GaN layer, a second dielectric DBR layer and an n-type electrode from bottom to top; and the p-type electrode is positioned at the bottom of the epitaxial structure and is bonded with the metal bonding layer to form an inverted structure. According to the vertical cavity surface emitting laser with the inverted structure provided by the invention, the heat dissipation function layer and the inverted structure design effectively improve the heat dissipation capability and the current uniformity of the device, and the service life, the performance stability and the reliability of the device are remarkably improved.

Vertically stacked semiconductor devices and methods of fabrication thereof that include a first device structure bonded to a second device structure via bonding layers having compressible metal bonding structures. The compressible metal bonding structures may be fabricated using an electroless deposition (ED) process, and may be less dense with a greater degree of compressibility than equivalent materials deposited by related processes. Accordingly, mating pairs of metal bonding structures may have a degree of compliance that enables effective metal-to-metal contact during a subsequent bonding process. Recrystallization of the metal material during an annealing process may produce shrinkage of the metal material and the formation of void areas between the metal bonds and the surrounding dielectric layers, thereby reducing stress on the surrounding dielectric-to-dielectric interface. Accordingly, bonding defects may be minimized and the performance and yields of vertically stacked semiconductor devices may be improved.

A semiconductor comprises a first substrate with a device region and a ring region surrounding the device region, a first interconnect structure above the first substrate, the first interconnect structure comprising a first via tower and a second via tower, a first bonding layer above the first interconnect structure and with a first metal bonding element, a second bonding layer above the first bonding layer and with a second metal bonding element contacting the first metal bonding element, and a second interconnect structure above the second bonding layer and with a third via tower extending through the second interconnect structure and located directly above the ring region. The first via tower is electrically connected to the second via tower via a first metal conductor.The first via tower is electrically connected to the third via tower via the first metal bonding element and the second metal bonding element.

The invention discloses a method for preparing a Micro-LED light-emitting module through a semitransparent metal bonding layer. The method comprises the following steps: growing an epitaxial layer with light transmission on a substrate; depositing a semitransparent metal bonding layer on the whole surface of the epitaxial layer; preparing a metal bonding unit and a photoetching register mark on the driving substrate, wherein the metal bonding unit is arranged on the surface of a driving electrode of the driving substrate; bonding the semitransparent metal bonding layer and the metal bonding unit; removing the substrate; and carrying out photoetching and patterning treatment on the epitaxial layer and the semitransparent metal bonding layer according to the photoetching register mark, reserving the epitaxial layer and the semitransparent metal bonding layer at the positions corresponding to the metal bonding units, preparing a single Micro-LED pixel unit, and completing the preparation of the Micro-LED light-emitting module. According to the method for preparing the Micro-LED light-emitting module through the semitransparent metal bonding layer, not only can non-aligned bonding be achieved, but also the semitransparent metal bonding layer does not affect subsequent photoetching register, and the preparation efficiency and the yield of Micro-LED light-emitting module preparation are improved.

A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

A semiconductor device assembly including a first semiconductor die having a first dielectric region and a first bond pad that are disposed on a first side of the first semiconductor die; a second semiconductor die having a second dielectric region and a second bond pad that are disposed on a second side of the second semiconductor die; and a hybrid bonding interface between the first side of the first semiconductor die and the second side of the second semiconductor die, the hybrid bonding interface including a gap free metal-metal bonding region between the first and the second bond pads and a gap free dielectric-dielectric bonding region between the first and the second dielectric regions, wherein the dielectric-dielectric bonding region includes a nitrogen gradient with a concentration that increases with proximity to the metal-metal bonding region.

A bonded assembly of a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes first dielectric material layers located on first semiconductor devices, first metal interconnect structures embedded in the first dielectric material layers and electrically connected to the first semiconductor devices, and a first bonding-level dielectric layer located on the first dielectric material layers and embedding first metallic bonding structures that are electrically connected to a respective one of the first metal interconnect structures, and further embedding first dummy metallic bonding structures having a lesser vertical extent than the first metallic bonding structures and electrically isolated from the first metal interconnect structures.

The invention provides low-temperature sintered silver-copper slurry, a perovskite laminated cell and a preparation method, and belongs to the technical field of crystalline silicon cells. The low-temperature sintered silver-copper paste comprises the following components in parts by mass: 15-30 parts of silver powder; 63-77 parts by mass of silver coated copper powder; the surface of the silver-coated copper powder is coated with acrylic acid and an oleylamine coating agent; 3-15 parts by mass of a resin; 0.2 to 2.8 parts by mass of a curing agent; 0.05 to 0.5 part by mass of a leveling agent; and 0.05 to 0.5 part by mass of a dispersant. The present disclosure achieves low temperature (llt; in addition, the silver-coated copper powder and the silver powder are mixed, the silver powder is replaced with low cost, the material cost is reduced, meanwhile, the silver-coated copper powder forms a three-dimensional conductive network at the low temperature of less than 120 DEG C through metal bonding of a silver shell and contact between particles, and the high conductivity of the electrode is ensured.

The invention discloses a preparation method of transition metal ion modified bimetallic MXene, which comprises the following steps: preparing different metal ions (Co < 2 + >, Ni < 2 + > and Mn < 2 + >) and Mo2TiC2Tx materials (marked as Mo2TiC2Tx-M) with different intercalation concentrations through electrostatic interaction, and carrying out detailed characterization and analysis on the Mo2TiC2Tx materials to explore the feasibility of MXene material modification. By analyzing the phase and morphology of the prepared sample, the transition metal ion intercalation enables the structure of Mo2TiC2Tx to become looser, and meanwhile, the interlayer spacing of Mo2TiC2Tx is remarkably increased. By introducing metal ions, a new metal bond can be formed, and electrons can be efficiently transferred. The research on the electrochemical performance of the material finds that the bimetallic MXene of the metal ion intercalation has excellent electro-catalytic hydrogen evolution performance and good stability.

To provide an underfill material that has photosensitivity, flux functionality, and adhesiveness, and can be patterned to form a film solely on required areas of an array substrate, which enables mass transfer of LED devices and efficient metal bonding.SOLUTION: A thermosetting positive photosensitive adhesive composition contains the following component (A), component (B), component (C) and component (D). Component (A): an alkali-soluble resin that includes a phenolic hydroxy group and has a polymeric glass transition temperature (Tg) of 60°C or lower. Component (B): a crosslinker. Component (C): a photosensitizer with quinonediazide. Component (D): a solvent.SELECTED DRAWING: None

A 3D microstructure is formed by bonding an upper wafer (1) to a lower wafer (2), by hybrid bonding with metallic bonding pads (17b, 17c; 27b, 27c) at the interface between the upper metallization level (HBM) of the respective interconnection structure of each of the wafers. These interconnection structures further comprise a horizontal interconnection level (MX) which is directly below the upper interconnection level (HBM). These pads are distributed horizontally in a substantially homogeneous manner and with a fine bonding pitch. Among these pads, bonding pads (17b; 27b) only are electrically isolated from any horizontal metallization element (15; 25) of the horizontal interconnection level (MX).Conversely, bonding and electrical connection pads (17c; 27c) are electrically coupled, without vias, to an underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX). Figure 2.

A substrate structure includes a first substrate and a second substrate. The first substrate includes a first glass plate and at least one first conductive via penetrating the first glass plate. The second substrate includes a second glass plate and at least one second conductive via penetrating the second glass plate. The second substrate is connected to the first substrate. The second glass plate is bonded to the first glass plate through chemical bonding force and defines a chemical bonding contact surface with the first glass substrate. The at least one second conductive via is bonded to the at least one first conductive via through metal diffusion and defines at least one metal bonding contact surface with the at least one first conductive via.

Methods and apparatus for substrate processing include: depositing a bulk layer of a dielectric material comprising a metal onto a device attached to a device substrate; depositing a graded layer of the dielectric material with a compositional gradient, onto the bulk layer; and depositing a bonding cap layer of the metal, having a purity of at least 99% by weight, onto the graded layer, wherein the graded layer has a dielectric gradient from substantially dielectric adjacent to the bulk layer to substantially conductive adjacent the bonding cap layer.

The present invention relates to a package or pre-package (100a, 100b) comprising: a semiconductor die (140) and two contact bonding pads (200, 300) encapsulating the semiconductor die (140). The two contact bonding sheets (200, 300) are bonded to each other. Each contact bonding pad includes a core layer (210, 310) and a bonding layer (220, 320). The core layer includes a core insulating layer (110a, 130a) and one or more metal through connections (110b, 110c, 130b) through the core insulating layer (110a, 130a). The bonding layer includes an insulating bonding layer (120a, 120b) formed on the core insulating layer (110a, 130a) and a metal bonding layer (120g, 120c, 120d) formed on the one or more metal through connections (110b, 110c, 130b). The metal bonding layer is designed to electrically and thermally connect the semiconductor die. The insulating bonding layers are bonded to each other to form a homogeneous insulating layer encapsulating the semiconductor die.

The invention relates to a high-heat-dissipation vertical-structure Ga2O3 Schottky diode and a preparation method thereof, and the preparation method comprises the steps: S1, obtaining a single-crystal gallium oxide substrate, preparing a highly-doped gallium oxide layer on the single-crystal gallium oxide substrate, and depositing a Schottky contact metal layer on one surface, far away from the highly-doped gallium oxide layer, of the single-crystal gallium oxide substrate; s2, obtaining a heat-conducting and electric-conducting substrate, and depositing an ohmic contact metal layer on the heat-conducting and electric-conducting substrate; s3, bonding the deposited Schottky contact metal layer in the step S1 and the ohmic contact metal layer in the step S2 to obtain a heterostructure; and S4, depositing a cathode metal layer on the highly-doped gallium oxide layer with the heterostructure to obtain the high-heat-dissipation vertical-structure Ga2O3 Schottky diode. In the technical scheme of the invention, an efficient longitudinal heat conduction path is constructed, so that heat generated during working can be quickly conducted to the heat-conducting and electric-conducting substrate from the active region through the Schottky junction and the metal bonding layer, and the thermal resistance of the device during working is reduced.

The application provides a Mini LED COG line structure and a manufacturing method thereof, and comprises a bearing substrate, a primer layer, a first transition film layer, a first metal layer, a second transition film layer, an insulating layer, a first photosensitive protective layer, a third transition film layer, a second metal layer, an insulating protective layer and a second photosensitive protective layer are sequentially arranged on the bearing substrate. Compared with the prior art, the transition film layer and the metal layer are combined, the transition film layer has the advantages of metal bond combination and diffusion, the high adhesion between the film layer and the metal layer is improved, good structural stability is achieved, and the thickness and efficiency problems of the thick metal layer are further improved by the combination of the metal layer and the transition film layer. Moreover, the structure of the application is simple, the preparation method is simple, and mass production is possible.

Various embodiments include die structures and methods of forming die structures. In an embodiment, a device includes: a lower substrate; upper integrated circuit dies bonded to the lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds, the upper integrated circuit dies including a semiconductor material; a buffer layer around the upper integrated circuit dies, the buffer layer including a stress reduction compound, a coefficient of thermal expansion of the stress reduction compound being greater than a coefficient of thermal expansion of the semiconductor material; and an encapsulant around the buffer layer and the upper integrated circuit dies, the encapsulant including a molding compound, a coefficient of thermal expansion of the molding compound being greater than the coefficient of thermal expansion of the stress reduction compound.

The invention belongs to the technical field of fuel cells, and particularly relates to an amorphous electrocatalyst Co / MoO2, and the amorphous electrocatalyst Co / MoO2 is prepared by the following steps: S1, obtaining a precursor material through a solvent method: S11, respectively stirring and dissolving molybdenum salt, aliphatic diamine and cobalt salt in water, and then mixing to obtain a solution A; s12, dropwise adding 1M of HCl aqueous solution into the solution A until precipitate appears; s13, carrying out heat preservation on the whole solution A system, centrifuging to obtain a precipitate, washing the precipitate, and drying to obtain a material B; and S2, preparing the metal oxide composite amorphous material doped with the elemental metal through high-temperature calcination. The anchoring of polysulfide is enhanced by the strong polarity of the metal oxide, the shuttle effect is effectively inhibited, the loss of positive electrode sulfur substances is reduced, and the capacity retention ratio is improved. Meanwhile, the metal simple substance Co is introduced into the amorphous material, a large number of metal bonds are generated, the inherent low conductivity problem of amorphous can be effectively solved, the overall conductivity of the catalyst is improved, and the catalyst has good application prospects in preparation of lithium-sulfur battery anode and cathode diaphragms.

The invention relates to a method for manufacturing a piezoelectric transducer (1) comprising a front electrode (10a), a rear electrode (10b) and a piezoelectric ceramic (50) made of lithium niobate. The method comprises: a step (a) of depositing on each opposite face of the ceramic (50) a primary metallic bonding layer (40a, 40b); a step (b) of depositing on each electrode (10a, 10b) a compliance layer (20a, 20b) made of an electrically conductive material with Tmelting > 700°C and δrupture > 20%; a step (c) of placing a foil (30a, 30b) based on an Ag-Cu alloy on each primary bonding layer (40a, 40b); a step (d) of forming an assembly (60) by stacking in this order the elements (10a, 20a, 30a, 40a, 50, 40b, 30b, 20b, 10b); a step (e) of brazing the assembly (60) in compression in a furnace at more than 450°C in a non-oxidizing atmosphere. Figure 1

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

The invention discloses an electric field sensor field enhancement cover plate and a preparation method thereof, and belongs to the technical field of micro electro mechanical system manufacturing. The method comprises the following steps: etching a groove on the silicon surface of a silicon wafer or an insulator to form a reinforcing structure; preparing a flat to-be-bonded surface through a bonding and thinning process; performing laser cutting on the glass sheet to form a reserved hole; and bonding the glass sheet and the bonding surface to form the cover plate. Optional steps include sputtering a getter and a metal bonding layer. The bonding process is used for replacing traditional glass backflow, two photoetching steps are omitted, the problems that glass filling is uneven and the surface is uneven are solved, the technological process is remarkably simplified, and the yield is improved. The method is suitable for wafer-level electric field sensor packaging, and the sensitivity and reliability are improved.

The invention relates to a transmission electron microscope high-resolution in-situ fluid turbulence heating chip, which has the structure that an upper chip and a lower chip are combined through a metal bonding layer to form a self-sealed ultrathin chamber; the upper chip has two sample injection ports and an upper central window; the lower chip is provided with a fluid inlet, a fluid outlet, a fluid flow channel, a lower central window, a micro-turbulence column array, a heating layer and an insulating layer; the heating layer has four contact electrodes and a spiral ring heating wire; the fluid inlet and the fluid outlet are symmetrically arranged about the central window, with the lower central window being the center and in the central area of ​​the spiral ring heating wire; the lower central window is located at the center of the heating layer; the micro-turbulence column array is arranged on the lower central window, and the chip has the advantages of rapid temperature rise and fall, high resolution, precise temperature control, controllable fluid flow direction and low sample drift rate.

The invention provides a vertical-structure Micro-LED chip and a preparation method thereof, and belongs to the technical field of semiconductor light-emitting devices. The vertical-structure Micro-LED chip comprises a conductive substrate, a metal bonding layer, an epitaxial structure, a quantum dot structure and a passivation layer, the conductive substrate, the metal bonding layer and the epitaxial structure are sequentially stacked, and the epitaxial structure comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked in the direction away from the metal bonding layer. The through hole penetrates through the first semiconductor layer, the multi-quantum well layer and the second semiconductor layer; the quantum dot structure is filled in the through hole and is in contact with the metal bonding layer; the passivation layer is arranged on the side wall of the through hole and located between the quantum dot structure and the epitaxial structure. The light transmission loss can be reduced, the light conversion efficiency is improved, and the heat dissipation performance and reliability of the chip are improved.

The invention discloses a wafer room temperature bonding method and application thereof, and belongs to the technical field of semiconductor advanced packaging and three-dimensional integration. The method comprises the following steps: providing a first wafer, and sequentially preparing a metal plane layer and an oxide layer on the surface of one side of the first wafer to form a metal / oxide composite layer; selectively etching the metal / oxide composite layer to remove the oxide layer and form a metal nanowire array layer on the metal plane layer; providing a second wafer, and preparing a metal material layer on the surface of one side of the second wafer; and aligning the surface, with the metal nanowire array layer, of the first wafer with the surface, with the metal material layer, of the second wafer, and then bonding. According to the invention, the metal nanowire array is introduced into the bonding interface, so that the nanowires are subjected to plastic deformation and local surface diffusion under the action of external pressure, that is, compact and reliable metal-metal bonding can be realized in a room temperature environment, and the requirements of a low-temperature process window and high strength are both considered.