86 results about "Metallic bonding" patented technology

A semiconductor device assembly including a first semiconductor die having a first dielectric region and a first bond pad that are disposed on a first side of the first semiconductor die; a second semiconductor die having a second dielectric region and a second bond pad that are disposed on a second side of the second semiconductor die; and a hybrid bonding interface between the first side of the first semiconductor die and the second side of the second semiconductor die, the hybrid bonding interface including a gap free metal-metal bonding region between the first and the second bond pads and a gap free dielectric-dielectric bonding region between the first and the second dielectric regions, wherein the dielectric-dielectric bonding region includes a nitrogen gradient with a concentration that increases with proximity to the metal-metal bonding region.

Methods and apparatus for substrate processing include: depositing a bulk layer of a dielectric material comprising a metal onto a device attached to a device substrate; depositing a graded layer of the dielectric material with a compositional gradient, onto the bulk layer; and depositing a bonding cap layer of the metal, having a purity of at least 99% by weight, onto the graded layer, wherein the graded layer has a dielectric gradient from substantially dielectric adjacent to the bulk layer to substantially conductive adjacent the bonding cap layer.

The present invention relates to a package or pre-package (100a, 100b) comprising: a semiconductor die (140) and two contact bonding pads (200, 300) encapsulating the semiconductor die (140). The two contact bonding sheets (200, 300) are bonded to each other. Each contact bonding pad includes a core layer (210, 310) and a bonding layer (220, 320). The core layer includes a core insulating layer (110a, 130a) and one or more metal through connections (110b, 110c, 130b) through the core insulating layer (110a, 130a). The bonding layer includes an insulating bonding layer (120a, 120b) formed on the core insulating layer (110a, 130a) and a metal bonding layer (120g, 120c, 120d) formed on the one or more metal through connections (110b, 110c, 130b). The metal bonding layer is designed to electrically and thermally connect the semiconductor die. The insulating bonding layers are bonded to each other to form a homogeneous insulating layer encapsulating the semiconductor die.

The invention relates to a high-heat-dissipation vertical-structure Ga2O3 Schottky diode and a preparation method thereof, and the preparation method comprises the steps: S1, obtaining a single-crystal gallium oxide substrate, preparing a highly-doped gallium oxide layer on the single-crystal gallium oxide substrate, and depositing a Schottky contact metal layer on one surface, far away from the highly-doped gallium oxide layer, of the single-crystal gallium oxide substrate; s2, obtaining a heat-conducting and electric-conducting substrate, and depositing an ohmic contact metal layer on the heat-conducting and electric-conducting substrate; s3, bonding the deposited Schottky contact metal layer in the step S1 and the ohmic contact metal layer in the step S2 to obtain a heterostructure; and S4, depositing a cathode metal layer on the highly-doped gallium oxide layer with the heterostructure to obtain the high-heat-dissipation vertical-structure Ga2O3 Schottky diode. In the technical scheme of the invention, an efficient longitudinal heat conduction path is constructed, so that heat generated during working can be quickly conducted to the heat-conducting and electric-conducting substrate from the active region through the Schottky junction and the metal bonding layer, and the thermal resistance of the device during working is reduced.

The invention discloses an electric field sensor field enhancement cover plate and a preparation method thereof, and belongs to the technical field of micro electro mechanical system manufacturing. The method comprises the following steps: etching a groove on the silicon surface of a silicon wafer or an insulator to form a reinforcing structure; preparing a flat to-be-bonded surface through a bonding and thinning process; performing laser cutting on the glass sheet to form a reserved hole; and bonding the glass sheet and the bonding surface to form the cover plate. Optional steps include sputtering a getter and a metal bonding layer. The bonding process is used for replacing traditional glass backflow, two photoetching steps are omitted, the problems that glass filling is uneven and the surface is uneven are solved, the technological process is remarkably simplified, and the yield is improved. The method is suitable for wafer-level electric field sensor packaging, and the sensitivity and reliability are improved.

The invention provides a vertical-structure Micro-LED chip and a preparation method thereof, and belongs to the technical field of semiconductor light-emitting devices. The vertical-structure Micro-LED chip comprises a conductive substrate, a metal bonding layer, an epitaxial structure, a quantum dot structure and a passivation layer, the conductive substrate, the metal bonding layer and the epitaxial structure are sequentially stacked, and the epitaxial structure comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked in the direction away from the metal bonding layer. The through hole penetrates through the first semiconductor layer, the multi-quantum well layer and the second semiconductor layer; the quantum dot structure is filled in the through hole and is in contact with the metal bonding layer; the passivation layer is arranged on the side wall of the through hole and located between the quantum dot structure and the epitaxial structure. The light transmission loss can be reduced, the light conversion efficiency is improved, and the heat dissipation performance and reliability of the chip are improved.

The invention discloses a wafer room temperature bonding method and application thereof, and belongs to the technical field of semiconductor advanced packaging and three-dimensional integration. The method comprises the following steps: providing a first wafer, and sequentially preparing a metal plane layer and an oxide layer on the surface of one side of the first wafer to form a metal / oxide composite layer; selectively etching the metal / oxide composite layer to remove the oxide layer and form a metal nanowire array layer on the metal plane layer; providing a second wafer, and preparing a metal material layer on the surface of one side of the second wafer; and aligning the surface, with the metal nanowire array layer, of the first wafer with the surface, with the metal material layer, of the second wafer, and then bonding. According to the invention, the metal nanowire array is introduced into the bonding interface, so that the nanowires are subjected to plastic deformation and local surface diffusion under the action of external pressure, that is, compact and reliable metal-metal bonding can be realized in a room temperature environment, and the requirements of a low-temperature process window and high strength are both considered.

The invention provides an MEMS device preparation method and an MEMS device, and the method comprises the steps: providing an MEMS assembly which comprises a first wafer and a first metal bonding layer located on the first wafer; forming an anti-bonding layer on the surface, close to the first metal bonding layer, of the first wafer; removing the anti-bonding layer on the surface of the first metal bonding layer in an illumination mode; providing a second wafer with a second metal bonding layer, and bonding the first metal bonding layer and the second metal bonding layer so as to bond the first wafer and the second wafer to obtain the MEMS device; the invention solves the technical problem that when a functional structure of an MEMS device is covered with a hydrophobic layer, a bonding surface is also covered with the hydrophobic layer, and in the prior art, the hydrophobic layer on the functional layer is difficult to well retain while the hydrophobic layer on the bonding surface is removed, so that the performance of the MEMS device is influenced.

This invention discloses a method for metal hot-press bonding and its application. The method specifically includes: providing a first substrate and a second substrate, the first substrate having a first metal bonding surface and the second substrate having a second metal bonding surface; aligning the first and second substrates to bring the first and second metal bonding surfaces into contact; and performing hot-press bonding by controlling temperature and applying pressure. The hot-press bonding includes a heating and high-pressure stage, a heat-holding and low-pressure stage, and a cooling and pressure-releasing stage; the temperature of the heat-holding and low-pressure stage is the bonding temperature. This invention achieves hot-press bonding of metals in an air environment through coordinated temperature and pressure control, resulting in a well-bonded interface that is free of oxidation, dense, and pore-free.

The application relates to a metal bonding method and application thereof, and belongs to the technical field of microelectronic interconnection. The metal bonding method comprises the following steps: step 1, cleaning a bonding surface; step 2, depositing a metal nanometer film on the cleaned bonding surface; and step 3, aligning and adhering two bonding surfaces completed in the step 2, and then bonding, wherein the bonding temperature is 300-600 DEG C, and the bonding pressure is 3-10 MPa. The metal bonding method can be used for bonding at a lower temperature.

This invention discloses a method and application for preparing metal-doped composite catalysts based on ZIF-67, relating to the field of wastewater treatment technology. This invention constructs a multi-component synergistic system through the coordination of functional groups on the surface of biochar with ZIF-67 and the electronic coupling effect between rare earth metals and Co. Compared with traditional pure chemical support synthesis methods, this reduces costs and improves environmental compatibility. The metal-doped composite catalyst prepared by this invention is a novel heterogeneous catalyst. Through the electrostatic interaction between the biochar support and Co ions, and the metal-metal bonds formed between La / Ce and Co, it significantly enhances the stability of Co ions, effectively avoiding secondary pollution. The metal-doped composite catalyst prepared by this invention can efficiently activate persulfate to generate reactive oxygen species and synergistically remove multiple pollutants from complex water bodies containing sulfamethoxazole, tetracycline, levofloxacin, and other antibiotics such as methylene blue.

The application provides a hybrid bonding structure, a three-dimensional packaging structure and a preparation method thereof. The preparation method of the hybrid bonding structure comprises the following steps: providing an initial hybrid bonding structure, wherein the hybrid bonding structure comprises a medium layer, a bonding medium layer, a diffusion barrier layer, a bonding metal layer and a regulation layer; performing a first grinding process to remove the diffusion barrier layer and the regulation layer, and forming a convex part protruding from the top surface of the bonding medium layer; and performing a second grinding process to remove the convex part of the bonding metal layer, and forming a first recessed part on the top surface of the bonding metal layer, which is lower than the top surface of the bonding medium layer. The hybrid bonding structure is a product prepared by the above method. The three-dimensional packaging structure comprises the hybrid bonding structure prepared by the above method. By adding the regulation layer, the convex part is formed when the diffusion barrier layer and the regulation layer are removed in the first grinding process, and the second grinding process is performed on the convex part to effectively control the depth of the first recessed part on the bonding metal layer. Therefore, the metal bonding interface cavity during hybrid bonding is reduced, and the bonding strength is improved.

A MEMS device and a manufacturing method thereof, the manufacturing method comprising: providing a first substrate, the first substrate being formed with a cavity and a lead layer, the lead layer comprising a strip-shaped lead and a ring-shaped lead arranged around the cavity, the ring-shaped lead having a broken area, the strip-shaped lead passing through the broken area, and the strip-shaped lead and the ring-shaped lead having a gap at the broken area; forming a first dielectric layer covering the lead layer, wherein the first dielectric layer is formed with a recessed area corresponding to the gap; forming a metal filling layer in the recessed area; forming a metal bonding layer arranged around the cavity on the first dielectric layer; and providing a second substrate, the bonding surface of the second substrate being bonded with the metal bonding layer, the metal filling layer being capable of deforming and filling the recessed area during the bonding process. The application can effectively eliminate the recessed defects of the metal bonding layer, reduce the process difficulty of the bonding, ensure the close fit of the bonding interface, prevent the generation of void defects, and improve the sealing reliability.

Package, containing: a first interposer (111A) wherein the first interposer (111A) has a first redistribution structure (160); a first die (50A) which is bonded to a first surface of the first redistribution structure (160) by a dielectric-dielectric bond and a metal-metal bond; a second interposer (111B) adjacent to the first interposer (111A), wherein the second interposer (111B) has a second redistribution structure (160); a second die (50B) which is bonded to a first surface of the second redistribution structure (160) by a first lot bond (128); an encapsulation material (133) around the first die (50A) and the second die (50B); and several conductive connectors (128) on a second side of the first redistribution structure (160) opposite the first die (50A) and the second die (50B).

A miniature LED comprises a bonding layer, an N-type semiconductor layer formed on the bonding layer, a light-emitting layer formed on the N-type semiconductor layer and a P-type semiconductor layer formed on the light-emitting layer. The bonding layer comprises a first metal bonding layer and a second metal bonding layer bonded with the N-type semiconductor layer; and the transparent bonding layer is formed between the first metal bonding layer and the second metal bonding layer. The thickness of the transparent bonding layer is one fourth of the wavelength of light emitted by the light-emitting layer.

The invention discloses a semiconductor chip adopting a diamond heat sink and a preparation method of the semiconductor chip, and the semiconductor chip comprises a power chip which is a high-power semiconductor chip with high energy density and high heating; the heat conduction substrate is a common heat sink substrate; the diamond deposition layer is a patterned diamond film deposited on the heat conduction substrate; the transition layer is arranged on the side, away from the heat conduction substrate, of the diamond deposition layer and used for enhancing the binding force and preventing interface reaction; and the graphical metallization layer is arranged on one side, far away from the diamond deposition layer, of the transition layer and is used for realizing welding or eutectic bonding with the power chip. A high-efficiency heat conduction path is adopted, a thick metal bonding area directly located below the chip provides a low-thermal-resistance vertical heat conduction channel, and a graphical stress buffer structure ensures transverse heat conduction and avoids huge thermal stress caused by full coverage of metal at the same time.

A new species of capacitive mass energy storage system employing eutectic liquid metallic materials and 2D / 2.5D electrode structures to achieve energy densities capable of replacing battery chemistries as well as petrochemical fuels. The system utilizes metallic bonding principles and submicron-scale electrode separation to sequester high electrical and ionic charge values. Operating at substantially higher voltages than conventional capacitors, the system employs synergistic charge storage mechanisms, and specialized fabrication techniques including capillary printing. Simulations show that the technology provides high energy density simultaneous with rapid charging and near instant discharging capabilities, configurable power output in DC or AC forms, and thermal stability at elevated temperatures. Applications include electric vehicles, autonomous robotics, and medical devices, among others.

The embodiment of the invention provides a wafer and a preparation method thereof, a wafer lamination, a light-emitting device and a terminal, relates to the technical field of semiconductors, and is used for optimizing the performance of the light-emitting device. The light-emitting device comprises a transparent conductive layer, an adhesion layer, a metal reflection layer, a blocking layer, a seed layer and a metal bonding layer which are arranged in a stacked mode. The seed layer with the same crystal phase as the metal bonding layer is arranged in the light-emitting device, so that the seed layer can control the crystal growth process of the metal bonding layer, the crystal quality of the metal bonding layer is ensured, and the bonding effect of the metal bonding layer is improved. In addition, the seed layer is located on the side, away from the metal reflecting layer, of the blocking layer, and when the metal reflecting layer and the metal bonding layer deform at high temperature, the seed layer with high rigidity can apply a reverse acting force to the blocking layer to prevent the blocking layer from breaking. That is, the seed layer can improve the problem of metal diffusion caused by holes generated by fracture of the barrier layer, and the effect of blocking metal diffusion is further enhanced. Therefore, the effect of optimizing the performance of the light-emitting device is achieved.

The application provides an LED chip and a manufacturing method thereof, which comprises the following steps: a metal bonding layer, an insulating layer, a metal connecting layer, an adhesive layer, a metal reflecting layer and a dielectric layer are arranged between the substrate and the epitaxial stack; the dielectric layer is arranged on the side of the epitaxial stack facing the substrate and extends to the through hole sidewall of the epitaxial stack; the dielectric layer has a dielectric hole exposing the second type semiconductor layer; the metal reflecting layer is formed on the horizontal surface of the epitaxial stack by being stacked on the surface of the dielectric layer; the adhesive layer is arranged at the edge of the metal reflecting layer; and the metal connecting layer is in contact with the metal reflecting layer by covering the adhesive layer. Thus, the material layer with limiting effect on the upper and lower surfaces of the edge of the metal reflecting layer is realized, the metal reflecting layer can be prevented from being eroded by chemical reagents, and the pattern integrity of the metal reflecting layer and the dielectric layer at the edge is well protected.

A substrate structure includes a first substrate and a second substrate bonded thereon. The first substrate includes a first dielectric substrate, a first conductive via, a first bonding layer, and a first electroless metal block. The first bonding layer has a first opening exposing the first conductive via, and the first electroless metal block is positioned within the first opening. The second substrate includes a second dielectric substrate, a second conductive via, a second bonding layer, and a second electroless metal block. The second bonding layer has a second opening exposing the second conductive via, and the second electroless metal block is positioned within the second opening. The second bonding layer is bonded to the first bonding layer to define a non-metal contact interface. The second electroless metal block is bonded to the first electroless metal block to define a metal bonding contact interface.

The application discloses a bonding method of a multilayer chip stack and a multilayer chip stack structure. An insulating layer, a barrier layer, a metal seed layer and a photoetchable insulating bonding adhesive are prepared on the surface of a chip respectively, metal interconnection windows are opened on the insulating bonding adhesive layers of two chips through a photoetching process respectively, the two-layer chip stack structure is realized through alignment bonding of the insulating bonding adhesives on the two chips, and then the metal bonding of the two-layer chip is realized by using a copper electroplating process and an electroplating filling mode. The electroplating process and the electroplating filling can be carried out in a room temperature environment, thereby avoiding high-temperature residual thermal stress. The metal bonding is realized through the electroplating process, an integrated metal connection structure is formed, the metal-metal bonding interface is eliminated, the van der Waals force suffered by the atoms of the upper and lower bonding interfaces is reduced, and the shear force and von Mises stress suffered by the bonding interface are reduced.

A first bond pad of a first device and a second bond pad of a second device are implanted with metal ions. The first and second semiconductor device are bonded together using a direct metal-to-metal bond and an overlay offset occurs between the bond pads such that a portion of the first bond pad and a portion of the second bond pad overlaps and contacts a dielectric material layer. During the bonding process, however, diffusion of the metal ions provides a barrier layer at the interface of the bond pads and the dielectric layers.

The invention relates to a fluorine ion battery negative electrode material and a preparation method and application thereof. The fluorine ion battery negative electrode material comprises metal fluoride MFy, carbon fluoride CFx and metal bonded carbon C-M, 0 < = x < x + y < = 4, preferably 0.01 < = x < x + y < = 2; the metal M is at least one of alkaline earth metal, rare earth metal, Al, Sn and Pb, preferably at least one of Ca, Mg, Al, Y, Sr, La, Ce and Pb.

The invention discloses a Micro-LED display device which comprises a light-emitting epitaxial layer, a first metal bonding layer and a stress buffer layer, the first metal bonding layer is arranged on one side of the light-emitting epitaxial layer in a stacked mode in the stacking direction, the stress buffer layer is arranged between the light-emitting epitaxial layer and the first metal bonding layer, and the stress buffer layer is arranged between the light-emitting epitaxial layer and the first metal bonding layer. The stress buffer layer comprises a plurality of stress buffer patterns arranged in an array mode, the light-emitting epitaxial layer and the first metal bonding layer make contact with each other on the periphery of each stress buffer pattern, or the stress buffer layer forms a plurality of contact windows arranged in an array mode, and the light-emitting epitaxial layer and the first metal bonding layer make contact with each other in each contact window. The stress buffer layer is embedded in at least one of the light-emitting epitaxial layer and the first metal bonding layer. Through the mode, the conditions of deformation, damage and the like of the light-emitting epitaxial layer and the first metal bonding layer can be reduced, so that the stability and the yield of the Micro-LED display equipment are improved.

A method for manufacturing multiple crystal oscillators includes the steps of: providing a first wafer containing a piezoelectric crystal; forming a first patterned metal layer having a plurality of lower electrodes on a first surface of the first wafer; providing a second wafer; forming a second patterned metal layer having a plurality of connection pads on a first surface of the second wafer; defining a plurality of first cavities within the second wafer below the first surface of the second wafer; joining the first and second wafers to form a bonded structure by directly joining the first and second patterned metal layers by metal bonding; thinning the first wafer from the second surface opposite the first surface of the first wafer; patterning the thinned first wafer to define a plurality of first suspension portions; and dicing the bonded structure into multiple crystal oscillators.

The application relates to a plastic surface metallization manufacturing process based on friction stir welding, which comprises the following steps: S1, a roughening stage; S2, a chemical plating-electroplating stage; S3, a friction stir welding stage: direct friction stir welding with a metal sheet. The direct friction stir lap welding process with a metal sheet adopted by the application can form firm metallurgical bonding between the metal transition layer and the metal sheet through metal bonding, element diffusion, recrystallization and the like, and can further strengthen the mechanical locking effect of the metal / plastic interface, and high-performance connection of metal / plastic heterogeneous materials is realized through the composite chemical plating-electroplating and friction stir welding process.

To provide a two-component treatment agent that is capable of easily making a metal surface composed of a variety of metals antibacterial by application thereof and can be used in an antibacterial treatment of a metal surface, a treatment method for making a metal surface antibacterial using the two-component treatment agent, and an antibacterial treatment agent that can be incorporated in the two-component treatment agent. An antibacterial treatment is carried out on a metal surface using a two-component treatment agent composed of a primer solution containing a metallic bonding compound (A) having a functional group capable of bonding to the metal surface and an antibacterial solution containing an antibacterial layer-forming compound (B), wherein the metallic bonding compound (A) and the antibacterial layer-forming compound (B) are capable of forming a covalent bond.

A bulk acoustic wave (BAW) resonator includes: a substrate; a piezoelectric layer disposed above the substrate; a first electrode disposed below the piezoelectric layer; a second electrode disposed above the piezoelectric layer; a first dielectric layer disposed below the piezoelectric layer; a second dielectric layer disposed below the first dielectric layer; a cavity disposed below the first electrode; a first grounded through hole disposed in the first dielectric layer and the second dielectric layer and spaced away from the cavity; a metal bonding layer disposed between the second dielectric layer and the substrate; a second grounded through hole disposed in the piezoelectric layer and aligned with the first grounded through hole, and a ground pad metal layer disposed on the piezoelectric layer and in the second grounded through hole, and electrically connected to the metal bonding layer.

This invention provides an atomic spin-resolved probe, its fabrication method, and its applications, belonging to the field of materials science and technology. The atomic spin-resolved probe includes: a tip base with a flat end face; a functional tip bonded to the tip base, the functional tip having a tapered structure that tapers continuously away from the tip base; and a metallic bonding layer for bonding the end face of the tip base to the functional tip; wherein the functional tip is a single-crystal material with topological edge states. This atomic spin-resolved probe alleviates the uncertainty of traditional magnetic probes that rely on magnetic field reversal for spin selection, achieving in-plane spin detection without external magnetization, and providing a high-precision detection tool for studying the spin structure of complex quantum materials.