296 results about "Sic substrate" patented technology

A SiC substrate includes a main body, a first power connection, and a second power connection. The main body has a length that extends between the first power connection and the second power connection. The first power connection is configured to conduct power into the main body for heating the main body. The second power connection is configured to conduct electric power conducted via the first power connection into the main body out of the main body. The main body forms a surface for deposition of SiC for growing a SiC crust. The main body is configured to resist forces generated during growth of the SiC crust having a minimal thickness for preventing cracking of the main body due to the generated forces at least in a volume section of the main body. The volume section is formed between a first plane and a second plane.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The embodiment of the invention provides a semiconductor substrate, an epitaxial wafer and a semiconductor device. The semiconductor substrate comprises a silicon carbide substrate layer, a transition layer arranged on the carbon surface of the silicon carbide substrate layer, and a stress regulation and control layer arranged on the side, away from the silicon carbide substrate layer, of the transition layer. The transition layer comprises a two-dimensional material layer, and the stress regulation layer comprises a 3C-SiC layer; or the transition layer comprises a polycrystalline 3C-SiC layer, and the stress regulation layer comprises a single crystal 3C-SiC layer. According to the semiconductor substrate provided by the embodiment of the invention, the transition layer and the stress regulation and control layer are arranged on the silicon carbide substrate layer, so that the surface type of the SiC substrate can be effectively improved, and the problem of non-uniform thickness distribution of the epitaxial layer caused by an overlarge bow value of the substrate in a SiC epitaxial process is solved to a certain extent, thereby improving the manufacturing yield of an epitaxial wafer, and improving the yield of the epitaxial wafer. Manufacturing cost is reduced, and semiconductor device performance is improved.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.0×1014 cm−3 at any position in the plane of the epitaxial layer.

The invention discloses a high-quality silicon carbide homoepitaxial wafer and a preparation method thereof, the epitaxial wafer comprises an epitaxial layer, a SiC substrate and a regulation and control layer, the regulation and control layer is located outside the back surface of the substrate or inside the back surface of the substrate, and the epitaxial layer is located on the front surface of the substrate; wherein the lattice mismatch degree between the regulation and control layer and the substrate has the same sign as the lattice mismatch degree between the epitaxial layer and the substrate, but the absolute value is larger; the preparation method comprises the following steps: preparing the regulation and control layer on the back surface of the SiC substrate; front deposition and surface scratch of the substrate caused by the previous step are eliminated through chemical mechanical polishing; growing an epitaxial layer on the front surface of the substrate through epitaxial deposition; and finally, chemically and mechanically polishing to eliminate micro pits and step coalescence morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. The regulation and control layer is introduced to the back surface of the substrate, lattice mismatch between the epitaxial layer and the substrate is weakened through the regulation and control layer, dislocation proliferation and slippage are reduced, and the high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation is prepared.

The invention relates to the technical field of semiconductor cleaning agents, and particularly discloses an etching solution for SiC surface silicon and a preparation method of the etching solution. The etching solution for SiC surface silicon comprises an aqueous solution of a component A and an aqueous solution of a component B. The component A comprises the following raw materials in parts by weight: 3-8 parts of nitric acid, 1-2 parts of hydrofluoric acid, 0.5-1 part of a complexing agent and 0.1-1 part of a surfactant; the raw materials of the component B comprise modified citric acid and citric acid in a mass ratio of (2.2-5.7): (1-1.8), and the modified citric acid is obtained by modifying a dihydroxy compound. The etching solution for the SiC surface silicon has higher selectivity on the SiC substrate surface silicon and other impurities, the etching effect and the etching rate of the etching solution on the SiC surface silicon are effectively improved, the loss of the SiC substrate is reduced, and the problem of environmental pollution is also reduced.

The invention provides a 3C-SiC epitaxial layer and a preparation method thereof, and the preparation method comprises the steps: firstly, placing a 4H-SiC substrate in a reaction chamber, and carrying out the homoepitaxial growth on the surface of the 4H-SiC substrate to obtain a 4H-SiC buffer layer; secondly, performing heteroepitaxial growth on the surface of the 4H-SiC buffer layer to obtain a sacrificial layer made of a C or Si material; thirdly, completely converting the sacrificial layer into a 3C-SiC buffer layer by adjusting process parameters of the reaction chamber; and finally, carrying out homoepitaxial growth on the surface of the 3C-SiC buffer layer to obtain a 3C-SiC epitaxial layer. The sacrificial layer made of C or Si is introduced to the surface of the 4H-SiC substrate, the key effect that the sacrificial layer passivates the activity of atomic steps on the surface of 4H-SiC is utilized, the multi-type mixing phenomenon is reduced fundamentally, and therefore the growth quality and the yield of the 3C-SiC epitaxial layer are improved.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

The invention discloses a diode avalanche shaping device with a composite terminal structure and secondary avalanche resistance. The diode avalanche shaping device comprises a negative electrode, a SiC substrate, a P-type control region, a SiC epitaxial layer, a corrugated P + region, a JTE region, a passivation layer and a positive electrode, a first protrusion of the corrugated P + region is embedded in the SiC epitaxial layer, and the orthographic projection of the first protrusion on the SiC substrate coincides with the orthographic projection of a control block of the P-type control region on the SiC substrate. And the widths of the spacer regions formed in the JTE region are sequentially increased along the direction far away from the corrugated P + region. According to the diode avalanche shaping device provided by the invention, the corrugated P + region, the JTE region with the interval regions of different widths and the control block arranged on the SiC substrate are arranged, so that the reliability of the device during the first avalanche can be improved, and the second avalanche of the device can be avoided at the same time.

The invention provides a method for reducing the laser annealing carbon precipitation amount of a SiC material and the SiC material. The method comprises the steps that (1) a silicon-nickel alloy layer is formed on the back face of a SiC substrate; (2) laser annealing treatment is carried out on the surface of the formed silicon-nickel alloy layer, so that ohmic contact is formed between the silicon-nickel alloy layer and the SiC substrate; by adopting the method disclosed by the invention, not only can the precipitation of carbon be effectively reduced and the particle size of the precipitated carbon be reduced, but also good ohmic contact is formed between the silicon-nickel alloy layer and the SiC substrate, and the specific contact resistivity is relatively low.

The invention relates to the field of semiconductor devices, and particularly discloses a photoelectric heterogeneous integrated microwave emission chip and a preparation method thereof, the chip is composed of a GaN HEMT amplifier and an InP UTC type detector on a SiC substrate; the preparation method comprises the following steps: preparing an amplifier on a SiC epitaxial wafer; growing a UTC type detector epitaxial layer on the InP substrate, and preparing a mesa structure; bonding the sapphire slide and the detector wafer; the InP epitaxial wafer substrate is removed; transferring the detector to an amplifier wafer through metal bonding; removing the temporary sapphire slide; and the detector is in electric signal communication with the amplifier. Compared with a method of firstly transferring an InP epitaxial layer and then preparing a detector device, the method has the advantages that the adverse effect of an InP-based detector processing technology on an amplifier is avoided; and secondly, the InP-based detector prepared by the method has the characteristic that the N-type contact metal faces downwards, and the structure is beneficial to reducing the junction region temperature and enhancing the heat dissipation capability of the device.

The application provides a method for forming a semiconductor structure, comprising the following steps: providing a SiC substrate, and forming a photoresist pattern on the back surface of the substrate; forming a mask layer on the back surface of the substrate and the photoresist pattern by a first evaporation process; removing the photoresist pattern and the mask layer covering the photoresist pattern, and retaining the mask layer with a mask window, wherein the mask window corresponds to a to-be-formed-hole area of the substrate; etching the to-be-formed-hole area of the substrate along the mask window of the mask layer, and forming a back hole in the substrate. By the above arrangement, the process window capability of the back hole stripping process can be improved, and the process steps can be simplified.

The application belongs to the technical field of gallium nitride substrate preparation, and particularly relates to a preparation method of n-type gallium nitride self-supporting substrate and a heavily doped GaN substrate and application. The preparation method of the n-type gallium nitride self-supporting substrate comprises the following steps: (1) sequentially epitaxially growing a buffer layer and a gallium nitride thick film on an original substrate; (2) peeling off the gallium nitride thick film to obtain a gallium nitride peeled sheet; (3) according to a germanium atom theoretical doping concentration of the gallium nitride peeled sheet, performing neutron irradiation treatment on the gallium nitride peeled sheet to obtain a germanium-doped gallium nitride peeled sheet; and (4) performing annealing treatment on the germanium-doped gallium nitride peeled sheet to obtain an n-type gallium nitride self-supporting substrate. The n-type gallium nitride self-supporting substrate obtained by the preparation method has a carrier concentration of 5x10 19 / cm 3 Without exogenous silicon or germanium dopants, the n-type gallium nitride self-supporting substrate obtained by the preparation method can be doped after the gallium nitride peeled sheet is formed, and the doping amount and doping concentration of the germanium element can be accurately controlled, which is suitable for large-scale production.

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.

A SiC epitaxial wafer according to an embodiment includes a SiC substrate, and a SiC epitaxial layer on one surface of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate, and has an impurity concentration higher than an impurity concentration of the drift layer. The impurity concentration of the buffer layer is 2.0×1018 cm−3 or more. In a case where the impurity concentration at a center in plan view in a laminating direction is measured in the laminating direction, uniformity of the impurity concentration in the buffer layer is 50% or less.

This SiC composite substrate (1) comprises: a polycrystalline SiC substrate (11); a single crystal SiC layer (13) laminated over the polycrystalline SiC substrate (11); and an SiC bonding layer (12) that is interposed between the polycrystalline SiC substrate (11) and the single crystal SiC layer (13), bonds the polycrystalline SiC substrate (11) and the single crystal SiC layer (13), and includes SiC crystal grains having an aspect ratio in a range greater than 2 and less than 200 with the longitudinal direction defined as the lamination direction.

A silicon carbide semiconductor device includes a drift layer, a first doped region, a second doped region, a gate trench, a third doped region and a gate electrode. The drift layer is disposed on a SiC substrate. The first doped region is disposed on the drift layer. The second doped region is disposed on the first doped region. The gate trench is extended from an upper surface of the second doped region through the first doped region and into the drift layer. The gate trench is formed in a manner dividing the drift layer into a plurality of mesas encircled by the gate trench, each of the mesas comprises a center portion and a plurality of leg portions extended from the center portion. The third doped region is arranged in the center portion of the mesa, and is disposed in the first doped region and adjacent to the second doped region. The gate electrode is arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator.

A silicon carbide semiconductor device includes an n-type epitaxial layer provided on a SiC substrate, a front surface electrode provided on the epitaxial layer, and a p-type electric field relieving region provided in the upper layer of the epitaxial layer in a terminal region. On the epitaxial layer, a first protective film composed of an interlayer insulating film and a protective oxide film that covers at least a part of the electric field relieving region is provided. A second protective film composed of a polyimide protective film is provided via a silicon nitride film so as to cover the outer end portion of the surface electrode, the first protective film, and at least a part of the epitaxial layer. The silicon nitride film protrudes from the second protective film at both an inner side end portion and an outer side end portion.

This method for manufacturing a SiC composite substrate includes: a step of providing a single crystal SiC substrate having a graphene film formed on a main surface; a step of epitaxially growing a single crystal SiC layer on the main surface of the single crystal SiC substrate via the graphene film; a step of peeling the single crystal SiC layer from the graphene film; and a step of laminating the single crystal SiC layer by interposing an adhesive layer containing a metal compound on a main surface of a polycrystalline SiC substrate.

A method of growing epitaxial 4H-SiC on 4H-SiC comprising: Heating a 4H-SiC substrate 2 to a temperature equal to or greater than 1200℃ and less than or equal to 1600℃ to anneal the substrate; and, depositing an epitaxial layer 12 of 4H-SiC on the substrate at a second temperature equal to or greater than 1400℃ and equal to or less than 1600℃. The substrate may be subdivided into a plurality of mesa regions 6 by at least one cavity 9 and the epitaxial deposition occurs in the cavity. The deposition may be in the presence of a chlorine-containing gas such as hydrogen chloride. The substrate and epitaxial layer may have opposite conductivity types. The method may produce a homostructure or a superfunction structure, and may be used in a power semiconductor device.

The application discloses a kind of based on threshold voltage regulation Multi-heterojunction GaN HEMT preparation method, comprising: growing GaN buffer layer and multiple periodic arrangement, including GaN channel layer and InAlN barrier layer channel barrier structure on SiC substrate;Surface preparation source drain and realize device active area isolation on side face;Surface deposition passivation layer and etching on the aperture of gate position;Etching channel barrier structure downward at the aperture of gate position, until etching period number makes threshold voltage regulation to pre-set requirement obtains recess;Gate preparation is completed in recess, and obtains threshold voltage regulation after Multi-heterojunction GaN HEMT.The application is designed by the thickness of GaN channel layer and InAlN barrier layer or the doping concentration design of additional InAlN barrier layer, and is designed in combination with etching formula of each material in channel barrier structure, so that etching depth and threshold voltage present linear variation, can realize threshold voltage accurate regulation.

The invention relates to a cleaning agent used after SiC substrate grinding and a preparation method thereof, and relates to the field of semiconductor cleaning agents, and the cleaning agent is prepared from the following raw materials by mass: 4-8% of an anionic surfactant, 2-6% of a nonionic surfactant, 2-6% of a cleaning auxiliary agent, 8-12% of sodium hydroxide, 2-4% of a bio-based modified antistatic agent, and the balance of water. The preparation method comprises the following steps: heating water, adding sodium hydroxide, stirring, adding the cleaning aid, stirring, adding the premixed anionic surfactant and nonionic surfactant, stirring, adding the bio-based modified antistatic agent, stirring, cooling, and filtering to obtain the cleaning agent for grinding the SiC substrate. The cleaning agent has a good cleaning effect, can effectively remove impurities after grinding, and meets the requirement of the semiconductor industry for high-quality cleaning of SiC wafers.

This utility model discloses a SiC packaging structure based on flip-chip bonding, including a heat sink and a SiC substrate disposed on the heat sink. A bottom copper electrode is formed on the surface of the SiC substrate, and the bottom copper electrode is connected to the SiC substrate through a bonding layer. Multiple chips connected in parallel are disposed on the bottom copper electrode, and the top of the multiple parallel chips is connected to a top copper electrode. The bottom copper electrode and the multiple parallel chips, as well as the top copper electrode and the multiple parallel chips, are connected through a copper sintering layer. The packaging structure reduces the use of traditional bonding wires through flip-chip design and copper sintering process, significantly reducing parasitic inductance and contact resistance, and improving thermal conductivity and electrical performance. At the same time, the top and bottom copper electrodes achieve double-sided electrode leads, effectively improving the integration and heat dissipation efficiency of the package.

The present invention provides a novel technique for manufacturing a SiC substrate that can reduce material loss when removing a strain layer. The present invention is a method for manufacturing a SiC substrate (30) that includes a strain layer thinning step (S1) that thins a strain layer (12) of a SiC substrate body (10) by moving the strain layer (12) to the surface side. In this way, by including the strain layer thinning step (S1) that moves (concentrates) the strain layer (12) to the surface side, material loss (L) when removing the strain layer (12) can be reduced.

Aspects provide forming hLDD SiC substrate wafers having a number of defects per square centimeter in excess of a predetermined threshold, and using the hLDD SiC substrate wafers to make vertical diffused metal oxide semiconductor (DMOS) field effect transistors (FET). In particular, methods comprise: growing by deposition a SiC ingot; slicing the SiC ingot to produce a plurality of base drift wafers; identifying base drift wafers having a number of defects per square centimeter in excess of a predetermined threshold; and forming a respective device layer on the identified base drift wafers. An aspect provides a DMOS FET having a base drift layer on the device layer and comprising SiC and having a number of defects per square centimeter in excess of a predetermined threshold.

The application provides a semiconductor structure forming method, which comprises the following steps: providing a SiC substrate, and the SiC substrate is subjected to a first rapid thermal annealing treatment; forming a SiC epitaxial layer on the SiC substrate; performing a second rapid thermal annealing treatment on the SiC substrate and the SiC epitaxial layer, and when the first rapid thermal annealing treatment and the second rapid thermal annealing treatment are performed, the temperature of the SiC substrate and the SiC epitaxial layer is raised to a first temperature at a first time, and then the temperature of the SiC substrate and the SiC epitaxial layer is lowered to a second temperature; the operation of raising the temperature and then lowering the temperature of the SiC substrate and the SiC epitaxial layer is repeated for several times; forming a well region, a source region and a gate trench in the source region, the well region and the SiC epitaxial layer, and a third rapid thermal annealing is performed after the well region, the source region and the gate trench are formed. The semiconductor structure forming method provided by the application can improve the bipolar degradation problem of the SiC MOSFET.

A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AIN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AIN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.

An embodiment of a SiC transistor includes a SiC substrate and a layer of metallization, which forms a drain terminal of the transistor. The SiC substrate includes a first horizontal N-doped region disposed above the layer of metallization, a second horizontal region disposed above the first horizontal region and including an N-doped region beside a P-doped region, a gate conductor disposed above the N-doped region, an N-doped source disposed above the P-doped region, and a source metal that bisects the source and that is electrically coupled to the P-doped region and the source. As compared to a SiC power transistor lacking the second generally horizontal region or the bisected source, an embodiment of the SiC power transistor can have, for a given maximum-blocking-voltage rating, a thinner substrate region, and, therefore, a lower RdsON over a range of transistor-operating temperatures (e.g., at room temperature and at higher temperatures).

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.