386 results about "Sic substrate" patented technology

To provide a SiC ingot easily processed during laser processing.SOLUTION: A SiC ingot has a facet surrounded with the minimum area when setting a diameter to D and plan-viewed from a crystal growth direction. When setting the length of the first side of a virtual rectangle having a first side parallel to a <11-20>direction and a second side parallel to a <1-100>direction to Lx, Lx / D<0.3 is satisfied in a first end being an end in the crystal growth direction.SELECTED DRAWING: Figure 3

An objective of the present invention is to provide a SiC epitaxial wafer with a large diameter, a low triangular defect density, and high carrier concentration uniformity. According to the present invention, a SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more. The SiC epitaxial layer has a triangular defect density of 0.2 pieces / cm2 or less and a carrier concentration variation of 20% or less.

The invention relates to the technical field of chip processing, and discloses an intelligent temperature control heating platform based on a SiC substrate and a chip processing method. The method comprises the following steps: modeling SiC substrate temperature distribution characteristics to obtain a three-dimensional temperature field distribution model; performing temperature parameter analysis to obtain a SiC substrate surface temperature distribution parameter set; performing hot area analysis to obtain a heating unit contribution degree coefficient matrix and a target hot area distribution map; calculating a power distribution value to obtain a heating power setting matrix; performing four-stage hierarchical control on the heating power setting matrix to obtain a stable transition control curve; according to the method, stable transition from the room temperature to the process temperature is achieved, extra preheating equipment is not needed, a stable processing temperature environment is provided for the SiC substrate, energy consumption is reduced, and efficient utilization of energy in the processing process of the SiC substrate chip is achieved.

A SiC substrate includes a main body, a first power connection, and a second power connection. The main body has a length that extends between the first power connection and the second power connection. The first power connection is configured to conduct power into the main body for heating the main body. The second power connection is configured to conduct electric power conducted via the first power connection into the main body out of the main body. The main body forms a surface for deposition of SiC for growing a SiC crust. The main body is configured to resist forces generated during growth of the SiC crust having a minimal thickness for preventing cracking of the main body due to the generated forces at least in a volume section of the main body. The volume section is formed between a first plane and a second plane.

To provide an SiC ingot capable of realizing both of high quality and workability.SOLUTION: This SiC ingot has a step-flow growth region, and a facet. On a cross section passing through a center in a <11-20> direction, an inside boundary between the facet and the step flow growth region has: a first slope inclined in a [-1-120] direction with respect to a crystal growth direction; and a second slope inclined in a [11-20] direction with respect to the crystal growth direction. An inflection point between the first and second slopes is nearer a first end on a Si face side than a center position of ingot length.SELECTED DRAWING: Figure 1

To provide an SiC epitaxial wafer with large diameter, thin thickness, and high uniformity of carrier concentration.SOLUTION: An SiC epitaxial wafer according to the present embodiment has an SiC substrate and an SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more and a thickness of 460 μm or less. The SiC epitaxial layer has a carrier concentration variation of 20% or less.SELECTED DRAWING: Figure 1

To provide an SiC ingot easy to be laser-processed.SOLUTION: This SiC ingot is made of an SiC single crystal inclined by an offset angle from a (0001) face and crystal-grown from a first end toward a second end, and has a step-flow growth region, and a facet. On a cross section passing through a center in a <11-20> direction, an angle θ1 formed by an inside boundary between the facet and the step flow growth region and a crystal growth direction is 56° or less.SELECTED DRAWING: Figure 1

The invention provides a SiC epitaxial wafer and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to reduce the defect density of the SiC epitaxial wafer, and the SiC epitaxial wafer comprises a SiC substrate and an epitaxial layer arranged on one side of the SiC substrate. The epitaxial layer comprises a C surface and a Si surface which are oppositely arranged, any one of the C surface and the Si surface is close to the SiC substrate, the thickness range of the epitaxial layer is 50-500 microns, and the defect density range of the epitaxial layer is 0.02 / cm < 2 >-1 / cm < 2 >.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The embodiment of the invention provides a semiconductor substrate, an epitaxial wafer and a semiconductor device. The semiconductor substrate comprises a silicon carbide substrate layer, a transition layer arranged on the carbon surface of the silicon carbide substrate layer, and a stress regulation and control layer arranged on the side, away from the silicon carbide substrate layer, of the transition layer. The transition layer comprises a two-dimensional material layer, and the stress regulation layer comprises a 3C-SiC layer; or the transition layer comprises a polycrystalline 3C-SiC layer, and the stress regulation layer comprises a single crystal 3C-SiC layer. According to the semiconductor substrate provided by the embodiment of the invention, the transition layer and the stress regulation and control layer are arranged on the silicon carbide substrate layer, so that the surface type of the SiC substrate can be effectively improved, and the problem of non-uniform thickness distribution of the epitaxial layer caused by an overlarge bow value of the substrate in a SiC epitaxial process is solved to a certain extent, thereby improving the manufacturing yield of an epitaxial wafer, and improving the yield of the epitaxial wafer. Manufacturing cost is reduced, and semiconductor device performance is improved.

A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AlN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AlN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.0×1014 cm−3 at any position in the plane of the epitaxial layer.

The invention discloses a high-quality silicon carbide homoepitaxial wafer and a preparation method thereof, the epitaxial wafer comprises an epitaxial layer, a SiC substrate and a regulation and control layer, the regulation and control layer is located outside the back surface of the substrate or inside the back surface of the substrate, and the epitaxial layer is located on the front surface of the substrate; wherein the lattice mismatch degree between the regulation and control layer and the substrate has the same sign as the lattice mismatch degree between the epitaxial layer and the substrate, but the absolute value is larger; the preparation method comprises the following steps: preparing the regulation and control layer on the back surface of the SiC substrate; front deposition and surface scratch of the substrate caused by the previous step are eliminated through chemical mechanical polishing; growing an epitaxial layer on the front surface of the substrate through epitaxial deposition; and finally, chemically and mechanically polishing to eliminate micro pits and step coalescence morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. The regulation and control layer is introduced to the back surface of the substrate, lattice mismatch between the epitaxial layer and the substrate is weakened through the regulation and control layer, dislocation proliferation and slippage are reduced, and the high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation is prepared.

The invention relates to silicon carbide powder as well as a preparation method and application thereof. Comprising the following steps: mixing silicon powder with negative charges and graphite powder with positive charges to obtain a mixture; and heating the mixture to enable the silicon powder with the negative charges and the graphite powder with the positive charges to react, so as to prepare the silicon carbide powder. The relatively compact and uniform structure formed by electrostatic self-assembly of the positively charged silicon powder and the negatively charged graphite powder is beneficial to self-propagating reaction synthesis of silicon carbide, so that the reaction is more sufficient, the carbon wrapping of the silicon carbide powder is reduced, and a foundation is laid for subsequent preparation of high-quality SiC substrate wafers or SiC-based devices.

The invention relates to the technical field of semiconductor cleaning agents, and particularly discloses an etching solution for SiC surface silicon and a preparation method of the etching solution. The etching solution for SiC surface silicon comprises an aqueous solution of a component A and an aqueous solution of a component B. The component A comprises the following raw materials in parts by weight: 3-8 parts of nitric acid, 1-2 parts of hydrofluoric acid, 0.5-1 part of a complexing agent and 0.1-1 part of a surfactant; the raw materials of the component B comprise modified citric acid and citric acid in a mass ratio of (2.2-5.7): (1-1.8), and the modified citric acid is obtained by modifying a dihydroxy compound. The etching solution for the SiC surface silicon has higher selectivity on the SiC substrate surface silicon and other impurities, the etching effect and the etching rate of the etching solution on the SiC surface silicon are effectively improved, the loss of the SiC substrate is reduced, and the problem of environmental pollution is also reduced.

An objective of the present invention is to provide a SiC epitaxial wafer with a large diameter, a thin thickness, and few triangular defects. A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more and a thickness of 460 μm or less. The SiC epitaxial layer has a triangular defect density of 0.2 pieces / cm2 or less.

The present application discloses a SiC substrate and a SiC crystal with uniform three-dimensional directional stress distribution, belonging to the technical field of SiC production and processing. The SiC substrate includes a first surface layer, a second surface layer and an intermediate layer; on the same axis, at any plane parallel to the first main surface or the second main surface in the first surface layer, Smax1 represents the maximum absolute value of the radial stress in the first surface layer, Smax2 represents the maximum absolute value of the radial stress in the intermediate layer, Smax3 represents the maximum absolute value of the radial stress in the second surface layer, △S1 = Smax2 - Smax1, △S2 = Smax2 - Smax3, -15 MPa ≤ △S1 ≤ 10 MPa, -15 MPa ≤ △S2 ≤ 10 MPa. The radial stress in the SiC substrate in the above first surface layer, second surface layer and intermediate layer is relatively low, and the stress distribution uniformity between each layer is good, which can improve the quality of the SiC substrate, expand the use range of the SiC substrate, and is beneficial to the production and processing of downstream epitaxial wafers and crystals.

An objective of the present invention is to provide a SiC epitaxial wafer with a large diameter, a thin thickness, and high carrier concentration uniformity. A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more and a thickness of 460 μm or less. The SiC epitaxial layer has a carrier concentration variation of 20% or less.

The invention provides a 3C-SiC epitaxial layer and a preparation method thereof, and the preparation method comprises the steps: firstly, placing a 4H-SiC substrate in a reaction chamber, and carrying out the homoepitaxial growth on the surface of the 4H-SiC substrate to obtain a 4H-SiC buffer layer; secondly, performing heteroepitaxial growth on the surface of the 4H-SiC buffer layer to obtain a sacrificial layer made of a C or Si material; thirdly, completely converting the sacrificial layer into a 3C-SiC buffer layer by adjusting process parameters of the reaction chamber; and finally, carrying out homoepitaxial growth on the surface of the 3C-SiC buffer layer to obtain a 3C-SiC epitaxial layer. The sacrificial layer made of C or Si is introduced to the surface of the 4H-SiC substrate, the key effect that the sacrificial layer passivates the activity of atomic steps on the surface of 4H-SiC is utilized, the multi-type mixing phenomenon is reduced fundamentally, and therefore the growth quality and the yield of the 3C-SiC epitaxial layer are improved.

To provide an SiC epitaxial wafer with large diameter, low triangular defect density, and high uniformity of carrier concentration.SOLUTION: An SiC epitaxial wafer according to the present embodiment has an SiC substrate and an SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more. The SiC epitaxial layer has a triangular defect density of 0.2 defects / cm2 or less and a carrier concentration variation of 20% or less.SELECTED DRAWING: Figure 1

To provide an SiC epitaxial wafer with large diameter, thin thickness, and low triangular defects.SOLUTION: An SiC epitaxial wafer according to the present embodiment has an SiC substrate and an SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more and a thickness of 460 μm or less. The SiC epitaxial layer has a triangular defect density of 0.2 piece / cm2 or less.SELECTED DRAWING: Figure 1

Disclosed are a dielectric structure, a semiconductor device structure, and manufacturing methods therefor. The manufacturing method for the dielectric structure includes: performing Al doping to a surface of a SiC substrate to form an Al-doped SiC layer and then oxidizing the Al-doped SiC layer to form a dielectric layer including at least a SiAlO layer. On one hand, thermal oxidation temperature required for oxidizing SiC to SiO2 may be reduced, so that an interface state with a high density at an interface of SiC / SiO2 is reduced, and quality of the dielectric layer is improved. On the other hand, original Si in the SiO2 is replaced with Al, a more stable structure may be formed, and the quality of the dielectric layer is further improved.

A drain electrode is located at the bottommost part, a substrate is arranged above the drain electrode, the substrate is a heavily-doped N-type SiC substrate, highly-doped SiC of the substrate and metal tungsten of the drain electrode form ohmic contact, an epitaxial layer is located above the substrate and made of an N-type doped SiC material, the doping concentration of the epitaxial layer is lower than that of the substrate, the epitaxial layer comprises a P region, and the P region is located at the bottom of the epitaxial layer. The P region is formed by ion implantation of a P-type doped SiC belt in an N-type doped epitaxial layer, so that a PN junction is formed between the P-type doped SiC belt and the N-type doped SiC of the epitaxial layer, the P-type doped SiC belt in the epitaxial layer is arranged at a position 5 [mu] m above the substrate, two P-type doped base regions are symmetrically arranged above the P region, a P + source region and an N + source region are symmetrically arranged above the two P-type doped base regions, and the P + source region and the N + source region are symmetrically arranged above the N + source region. The SiC MOSFET has the advantages of being small in size, resistant to high voltage and high temperature, fast in switching, low in on resistance and low in loss, and is mainly applied to a new energy automobile standard-level SiC MOSFET with high performance and high gate oxide reliability.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

The invention discloses a diode avalanche shaping device with a composite terminal structure and secondary avalanche resistance. The diode avalanche shaping device comprises a negative electrode, a SiC substrate, a P-type control region, a SiC epitaxial layer, a corrugated P + region, a JTE region, a passivation layer and a positive electrode, a first protrusion of the corrugated P + region is embedded in the SiC epitaxial layer, and the orthographic projection of the first protrusion on the SiC substrate coincides with the orthographic projection of a control block of the P-type control region on the SiC substrate. And the widths of the spacer regions formed in the JTE region are sequentially increased along the direction far away from the corrugated P + region. According to the diode avalanche shaping device provided by the invention, the corrugated P + region, the JTE region with the interval regions of different widths and the control block arranged on the SiC substrate are arranged, so that the reliability of the device during the first avalanche can be improved, and the second avalanche of the device can be avoided at the same time.

The invention provides a method for reducing the laser annealing carbon precipitation amount of a SiC material and the SiC material. The method comprises the steps that (1) a silicon-nickel alloy layer is formed on the back face of a SiC substrate; (2) laser annealing treatment is carried out on the surface of the formed silicon-nickel alloy layer, so that ohmic contact is formed between the silicon-nickel alloy layer and the SiC substrate; by adopting the method disclosed by the invention, not only can the precipitation of carbon be effectively reduced and the particle size of the precipitated carbon be reduced, but also good ohmic contact is formed between the silicon-nickel alloy layer and the SiC substrate, and the specific contact resistivity is relatively low.

The invention relates to the field of semiconductor devices, and particularly discloses a photoelectric heterogeneous integrated microwave emission chip and a preparation method thereof, the chip is composed of a GaN HEMT amplifier and an InP UTC type detector on a SiC substrate; the preparation method comprises the following steps: preparing an amplifier on a SiC epitaxial wafer; growing a UTC type detector epitaxial layer on the InP substrate, and preparing a mesa structure; bonding the sapphire slide and the detector wafer; the InP epitaxial wafer substrate is removed; transferring the detector to an amplifier wafer through metal bonding; removing the temporary sapphire slide; and the detector is in electric signal communication with the amplifier. Compared with a method of firstly transferring an InP epitaxial layer and then preparing a detector device, the method has the advantages that the adverse effect of an InP-based detector processing technology on an amplifier is avoided; and secondly, the InP-based detector prepared by the method has the characteristic that the N-type contact metal faces downwards, and the structure is beneficial to reducing the junction region temperature and enhancing the heat dissipation capability of the device.

The application provides a method for forming a semiconductor structure, comprising the following steps: providing a SiC substrate, and forming a photoresist pattern on the back surface of the substrate; forming a mask layer on the back surface of the substrate and the photoresist pattern by a first evaporation process; removing the photoresist pattern and the mask layer covering the photoresist pattern, and retaining the mask layer with a mask window, wherein the mask window corresponds to a to-be-formed-hole area of the substrate; etching the to-be-formed-hole area of the substrate along the mask window of the mask layer, and forming a back hole in the substrate. By the above arrangement, the process window capability of the back hole stripping process can be improved, and the process steps can be simplified.

The application belongs to the technical field of gallium nitride substrate preparation, and particularly relates to a preparation method of n-type gallium nitride self-supporting substrate and a heavily doped GaN substrate and application. The preparation method of the n-type gallium nitride self-supporting substrate comprises the following steps: (1) sequentially epitaxially growing a buffer layer and a gallium nitride thick film on an original substrate; (2) peeling off the gallium nitride thick film to obtain a gallium nitride peeled sheet; (3) according to a germanium atom theoretical doping concentration of the gallium nitride peeled sheet, performing neutron irradiation treatment on the gallium nitride peeled sheet to obtain a germanium-doped gallium nitride peeled sheet; and (4) performing annealing treatment on the germanium-doped gallium nitride peeled sheet to obtain an n-type gallium nitride self-supporting substrate. The n-type gallium nitride self-supporting substrate obtained by the preparation method has a carrier concentration of 5x10 19 / cm 3 Without exogenous silicon or germanium dopants, the n-type gallium nitride self-supporting substrate obtained by the preparation method can be doped after the gallium nitride peeled sheet is formed, and the doping amount and doping concentration of the germanium element can be accurately controlled, which is suitable for large-scale production.

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.