1146 results about "Sic substrate" patented technology

A method for fabricating light emitting diode (LEDs) comprises providing a plurality of LEDs on a substrate wafer, each of which has an n-type and p-type layer of Group-III nitride material formed on a SiC substrate with the n-type layer sandwiched between the substrate and p-type layer. A conductive carrier is provided having a lateral surface to hold the LEDs. The LEDs are flip-chip mounted on the lateral surface of the conductive carrier. The SiC substrate is removed from the LEDs such that the n-type layer is the top-most layer. A respective contact is deposited on the n-type layer of each of the LEDs and the carrier is separated into portions such that each of the LEDs is separated from the others, with each of the LEDs mounted to a respective portion of said carrier.

Provided is a process for preparing graphene on a SiC substrate, based on metal film-assisted annealing, comprising the following steps: subjecting a SiC substrate to a standard cleaning process; placing the cleaned SiC substrate into a quartz tube and heating the quartz tube up to a temperature of 750 to 1150° C.; introducing CCl₄vapor into the quartz tube to react with SiC for a period of 20 to 100 minutes so as to generate a double-layered carbon film, wherein the CCl₄ vapor is carried by Ar gas; forming a metal film with a thickness of 350 to 600 nm on a Si substrate by electron beam deposition; placing the obtained double-layered carbon film sample onto the metal film; subsequently annealing them in an Ar atmosphere at a temperature of 900 to 1100° C. for 10-30 minutes so as to reconstitute the double-layered carbon film into double-layered graphene; and removing the metal film from the double-layered graphene, thereby obtaining double-layered graphene. Also provided is double-layered graphene prepared by said process.

In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of delta-doped layers and undoped layers and are integrated in a common substrate.

A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a δ doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration δ doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle α. The trench is formed with the standard deviation σ in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2σ] to [(90 degrees)−tan⁻¹ (0.87×tan α)−2σ] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)−tan⁻¹ (0.87×tan α)] can be obtained.

A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction termination region formed to surround the junction forming region, and including a semiconductor region of a conductivity type different from the SiC layer formed as a substantially quadrangular doughnut ring, having two edges facing each other, each crossing a projection direction, which is obtained when the off direction is projected on the upper surface of the SiC layer, at a right angle, wherein a width of one of the two edges on an upper stream side of the off direction is L1, that of the other edge on a down stream side is L2, and a relation L1>L2 is satisfied.

A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas atmosphere containing SiH₄ and Ar at a temperature between 1600° C. and 1800° C., and thereafter in a hydrogen gas atmosphere at a temperature between 1400° C. and 1500° C. The present manufacturing method smoothens the trench inner surface and rounds the corners in the trench to prevent the electric field from localizing thereto.

A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region.

A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.

A semiconductor device includes an SiC substrate, an SiC layer of a first conductivity type disposed on the upper surface of the SiC substrate, a first SiC region of a second conductivity type disposed on the SiC layer, a second SiC region of the first conductivity type disposed on a surface region of the first SiC region, including a nitrogen-added first sub-region and a phosphorus-added second sub-region disposed in contact with the first sub-region, a gate insulating film disposed to extend over the SiC layer, first SiC region, and first sub-region of the second SiC region, a gate electrode formed on the gate insulating film, a first electrode formed on the second sub-region of the second SiC region and the first SiC region, and a second electrode formed on the lower surface of the SiC substrate.

Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.

The surface 1a of a single crystal alpha -SiC substrate 1 is adjusted so as to have a surface roughness equal to or lower than 2,000 angstroms RMS, and preferably equal to or lower than 1,000 angstroms RMS. On the surface 1a of the single crystal alpha -SiC substrate 1, a polycrystalline alpha -SiC film 2 is grown by thermal CVD to form a complex is placed in a porous carbon container and the carbon container is covered with alpha -SiC powder. The complex is subjected to a heat treatment at a temperature equal to or higher than a film growing temperature, i.e., in the range of 1,900 to 2,400 DEG C. in an argon gas flow, whereby single crystal alpha -SiC is integrally grown on the single crystal alpha -SiC substrate 1 by crystal growth and recrystallization of the polycrystalline alpha -SiC film 2. It is possible to stably and efficiently produce single crystal SiC of a large size which has a high quality and in which any crystal nucleus is not generated.

A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N⁺ type SiC substrate constituting a drain layer; an N⁻ type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N⁺ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N⁺ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N⁻ type drift layer and lower than that of the P type body layer.

Atomic wires of great length and great stability are formed on the surface of a SiC substrate as straight chains of dimers of an element chosen from amongst SiC and C. In order to produce same, layers of the element are formed on the surface and the assembly is constructed by means of annealings of the surface provided with the layers. The resulting wires have application to nanoelectronics.

A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

In one embodiment of the present invention, a monocrystal SiC epitaxial substrate is produced which includes a monocrystal SiC substrate; a buffer layer made of a first SiC epitaxial film formed on the monocrystal SiC substrate; and an active layer made of a second SiC epitaxial film formed on the buffer layer. The buffer layer is grown by heat-treating a set of the monocrystal SiC substrate, a carbon source plate, and a metal Si melt layer having a predetermined thickness and interposed between the monocrystal SiC substrate and the metal Si melt layer, so as to epitaxially grow monocrystal SiC on the monocrystal SiC substrate. The active layer is grown by epitaxially growing monocrystal SiC on the buffer layer by vapor phase growth method. This allows for production of a monocrystal SiC epitaxial substrate including a high-quality monocrystal SiC active layer being low in defects.

A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.