35 results about "Sic substrate" patented technology

The application provides a method for forming a semiconductor structure, comprising the following steps: providing a SiC substrate, and forming a photoresist pattern on the back surface of the substrate; forming a mask layer on the back surface of the substrate and the photoresist pattern by a first evaporation process; removing the photoresist pattern and the mask layer covering the photoresist pattern, and retaining the mask layer with a mask window, wherein the mask window corresponds to a to-be-formed-hole area of the substrate; etching the to-be-formed-hole area of the substrate along the mask window of the mask layer, and forming a back hole in the substrate. By the above arrangement, the process window capability of the back hole stripping process can be improved, and the process steps can be simplified.

The application belongs to the technical field of gallium nitride substrate preparation, and particularly relates to a preparation method of n-type gallium nitride self-supporting substrate and a heavily doped GaN substrate and application. The preparation method of the n-type gallium nitride self-supporting substrate comprises the following steps: (1) sequentially epitaxially growing a buffer layer and a gallium nitride thick film on an original substrate; (2) peeling off the gallium nitride thick film to obtain a gallium nitride peeled sheet; (3) according to a germanium atom theoretical doping concentration of the gallium nitride peeled sheet, performing neutron irradiation treatment on the gallium nitride peeled sheet to obtain a germanium-doped gallium nitride peeled sheet; and (4) performing annealing treatment on the germanium-doped gallium nitride peeled sheet to obtain an n-type gallium nitride self-supporting substrate. The n-type gallium nitride self-supporting substrate obtained by the preparation method has a carrier concentration of 5x10 19 / cm 3 Without exogenous silicon or germanium dopants, the n-type gallium nitride self-supporting substrate obtained by the preparation method can be doped after the gallium nitride peeled sheet is formed, and the doping amount and doping concentration of the germanium element can be accurately controlled, which is suitable for large-scale production.

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.

This utility model discloses a SiC packaging structure based on flip-chip bonding, including a heat sink and a SiC substrate disposed on the heat sink. A bottom copper electrode is formed on the surface of the SiC substrate, and the bottom copper electrode is connected to the SiC substrate through a bonding layer. Multiple chips connected in parallel are disposed on the bottom copper electrode, and the top of the multiple parallel chips is connected to a top copper electrode. The bottom copper electrode and the multiple parallel chips, as well as the top copper electrode and the multiple parallel chips, are connected through a copper sintering layer. The packaging structure reduces the use of traditional bonding wires through flip-chip design and copper sintering process, significantly reducing parasitic inductance and contact resistance, and improving thermal conductivity and electrical performance. At the same time, the top and bottom copper electrodes achieve double-sided electrode leads, effectively improving the integration and heat dissipation efficiency of the package.

A multilayer semiconductor device includes: a substrate comprising silicon carbide (SiC); and an epitaxial transition layer on the substrate, the epitaxial transition layer comprising a first epitaxial oxide material or SiC. One or more epitaxial active regions comprising one or more second epitaxial oxide materials are formed on the epitaxial transition layer, and a metal layer is formed over the one or more epitaxial active regions, the metal layer comprising one or more electrical contacts. The multilayer semiconductor device includes one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET), a vertically conductive MOSFET, a lateral MOSFET, a metal-semiconductor field-effect transistor (MSFET), a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-insulator-semiconductor (MIS) device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor (IGBT).

The application discloses a MOSFET device and a preparation method thereof, and relates to the technical field of SiC power device design and manufacturing. The MOSFET device comprises a plurality of strip cells, and the strip cells are sequentially stacked from bottom to top with a metal drain, a SiC substrate of a first doping type, a SiC buffer layer of the first doping type and a SiC epitaxial layer of the first doping type, and a plurality of stepped grooves of a symmetrical structure are formed in the SiC epitaxial layer. The MOSFET device utilizes a longitudinal space region to form a multi-directional current channel, under the premise of ensuring the reliability of a gate oxide and the reverse breakdown performance, the multi-directional current channel can effectively improve the channel density and the current density per unit area, the SiC epitaxial layer surface and the metal source electrode above the ohmic contact area of the source groove guarantee the concentrated export of the source current, and the whole realizes the synergistic optimization of low specific on-resistance, high gate oxide reliability and high integration, and the device manufacturing cost is reduced.

The present application relates to the technical field of semiconductor materials, in particular to a method for peeling off a silicon carbide single crystal film, a silicon carbide epitaxial substrate and a semiconductor device. The method comprises the following steps: bonding a temporary carrier substrate with a controllable dissociation layer on the surface to a donor substrate; then peeling off; and then bonding and peeling off the composite structure formed by peeling off to a target receptor substrate, wherein the crystal form of the temporary carrier substrate and the donor substrate is the same or compatible. The method does not directly transfer the SiC film from the donor carrier to the receptor substrate at one time, but creatively introduces a "homogeneous temporary carrier substrate" as a buffer and transfer platform, and designs a "controllable dissociation layer" to realize accurate secondary separation. Through the "two-step transfer method", the three problems of thermal mismatch, high-temperature damage and recovery loss are decoupled, which has originality and systematic advantages in the process path, and provides a new route for the manufacture of ultra-low-cost and large-size SiC substrates.

This invention discloses a method for assembling ceramic-based composites and metal to improve the accuracy of connecting holes. The method includes steps S1, assembling the composite component; S2, placing the assembled composite component in a CVI deposition furnace to deposit a SiC substrate; S3, placing the composite component with the deposited SiC substrate on a CNC milling machine and machining positioning holes on the composite component that match the solid cylindrical pins of the metal part; S4, placing the composite component in a CVI deposition furnace and depositing a silicon carbide protective coating on the surface; S5, using the solid cylindrical pins on the metal part to position and test-fit the positioning holes on the composite component, and applying adhesive to the mating surfaces; S6, machining the connecting holes; and S7, surface cleaning. In this invention, the solid cylindrical pins are embedded in the positioning holes, achieving rapid positioning of the composite component and the metal part. The assembly is simple, and if dimensional deviations occur, only the metal part needs to be replaced. The product has high maintainability and a short maintenance cycle.

This invention provides a method for fabricating a substrate using the head and tail portions of a silicon carbide (SiC) crystal rod, comprising: acquiring the thickness and a first appearance image of the wafer; if the thickness is greater than or equal to a first preset thickness value and there are no defects in the appearance, marking the uncut side of the wafer; grinding this side until the thickness of the wafer is within a second preset range; grinding the wafer on both sides until the thickness is within a third preset range; acquiring the surface quality parameters and a second appearance image of the wafer; if the surface quality parameters meet the target parameters and there are no defects in the appearance, performing circumferential chamfering according to preset process parameters; polishing the wafer on both sides until the thickness of the wafer is within a fourth preset range; and selecting qualified wafers according to preset requirements. This method can reprocess the head and tail portions of the SiC crystal rod to fabricate SiC substrates with thinner or smaller thickness specifications, thereby reducing material waste.

Disclosed are a SiC crystal and SiC substrate having small axial and radial optical path differences, belonging to the technical field of SiC material preparation. On any one horizontal line of the SiC crystal, the maximum optical path difference does not exceed 6.503 nm, and the standard deviation does not exceed 1.271 nm; and on any axis of the SiC crystal, the maximum optical path difference does not exceed 9.334 nm, and the standard deviation does not exceed 1.506 nm.

This invention discloses a contamination-free transfer method for MoS2 thin films on wide-bandgap semiconductors, comprising: spin-coating a PMMA solution onto the surface of a MoS2 / SiC substrate and curing it to form a PMMA / MoS2 / SiC composite substrate, and drawing an opening at its edge; tilting the composite substrate with the opening into deionized water, allowing the deionized water to enter between the PMMA / MoS2 layer and the SiC layer through the opening, and using the surface tension of the water to completely separate the PMMA / MoS2 layer from the SiC layer; transferring the separated PMMA / MoS2 layer onto a target substrate; and performing resist removal, cleaning, and drying on the transferred sample to complete the transfer of the MoS2 thin film. This method abandons the traditional etching process, utilizes the hydrophilic properties of SiC to achieve peeling through water-assisted interfacial energy control, effectively avoiding substrate structure damage and irreversible damage, and improving the substrate's reusability and process compatibility.

The present application belongs to the technical field of SiC material preparation, and provides an SiC crystal and an SiC substrate having low defect stress. Several SiC substrates are prepared from the SiC crystal. High-pass signals and low-pass signals are distinguished on the basis of the Laplace pyramid principle. Under the high-pass signals, the overall optical path difference of any SiC substrate is less than 6 nm, the maximum value of the optical path difference is less than 12 nm, and the standard deviation of the optical path difference is less than 3 nm.

The SiC wafer is smoothed after mechanical polishing, supporting the epitaxial growth of SiC films with a low defect rate. [Solution] The method comprises the steps of placing a workpiece equipped with a SiC substrate on a substrate support in a plasma chamber, introducing a process gas into the plasma chamber, and reducing the surface roughness of the SiC substrate by plasma etching the SiC substrate, and alternately performing the steps of generating reactive ion etching plasma in the plasma chamber by applying bias RF power to the substrate support and etching the SiC substrate at a first plasma chamber pressure for a first period, and generating inductively coupled plasma in the plasma chamber by applying source RF power to the plasma chamber, applying bias RF power to the substrate support and etching the SiC substrate at a second plasma chamber pressure for a second period.

This invention discloses a SiC substrate MOCVD gallium oxide epitaxial wafer, belonging to the field of wide-bandgap semiconductor epitaxial material preparation technology. The epitaxial wafer comprises, from bottom to top, a silicon carbide substrate, a β-Ga2O3 carbon getter layer, and a β-Ga2O3 drift layer. The carbon concentration ratio of the β-Ga2O3 carbon getter layer to the β-Ga2O3 drift layer is not less than 100, forming a decreasing carbon concentration gradient. The β-Ga2O3 drift layer contains periodically distributed annealing repair interfaces. The preparation method employs a precursor spatiotemporal separation alternating gas supply mode to grow the β-Ga2O3 drift layer, with periodic insertion of in-situ flash annealing steps. A three-stage carbon purification mechanism synergistically removes carbon from three stages: carbon source generation, defect complex formation, and cumulative stabilization, solving the technical bottleneck of uncontrollable carrier compensation ratio caused by organometallic precursor carbon contamination during MOCVD growth of ultra-thick drift layers.

This application discloses a SiC substrate and a SiC crystal having a uniform stress distribution in three dimensions, and belongs to the technical field of SiC production and processing. The SiC substrate includes a first surface layer, a second surface layer and an intermediate layer, and on the same axis, in any plane parallel to the first principal surface or the second principal surface of the first surface layer, Smax1 represents the maximum absolute value of the radial stress in the first surface layer, Smax2 represents the maximum absolute value of the radial stress in the intermediate layer, and Smax3 represents the maximum absolute value of the radial stress in the second surface layer, with △S1 = Smax2 - Smax1, △S2 = Smax2 - Smax3, -15MPa ≤ △S1 ≤ 10MPa, and -15MPa ≤ △S2 ≤ 10MPa. The radial stress in the SiC substrate in the first surface layer, the second surface layer, and the intermediate layer is relatively low, and the uniformity of the stress distribution between each layer is high. This improves the quality of the SiC substrate, expands the range of applications for the SiC substrate, and is advantageous for the downstream production and processing of epitaxial wafers and crystals.

A setter for firing according to the present invention is formed by providing a mullite-containing layer that includes mullite on an SiC substrate. The cordierite content of the mullite-containing layer is 3–50 mass% and / or the potassium content of the mullite-containing layer is 1–5 mass%.

This application provides a semiconductor structure and its formation method. The semiconductor structure includes: a SiC substrate with a SiC epitaxial layer on the SiC substrate; and a gate structure located on or within the SiC epitaxial layer. The gate structure includes a passivation layer and a gate layer located on the passivation layer, wherein the passivation layer includes a first film with a thermal conductivity of 10 W / m·K to 28 W / m·K. This application can improve the channel carrier mobility of SiC MOSFET devices.

A SiC device includes an n-type semiconductor layer provided on a SiC substrate; a p-type first well region is provided in an upper layer part of the semiconductor layer; an n-type first impurity region is provided in an upper layer part of the first well region; a p-type first well contact region is provided in the upper layer part of the first well region and having a side surface joined to the first impurity region; a first contact electrically connected to the first impurity region and the first well contact region and electrically connected to a first main electrode provided over the semiconductor layer; a second well region separated from the first well region; a p-type second well contact region is provided in an upper layer part of the second well region; and a second contact electrically connected to the second well contact region.

This application provides a silicon carbide trench MOSFET with integrated heterojunction diode and its fabrication method. Applied to the field of power semiconductor technology, it includes: an N+ type SiC substrate; an N- type SiC drift layer disposed above the N+ type SiC substrate; a P-type base region disposed above the N- type SiC drift layer; an N+ type source region disposed above the P-type base region; a trench gate structure including: a gate trench, a gate oxide layer, and a gate conductive material, the gate oxide layer being disposed on the inner wall of the gate trench, and the gate conductive material filling the gate trench; a source metal electrically connected to both the N+ type source region and the P-type base region; and a drain metal disposed below the N+ type SiC substrate. This invention reduces on-resistance, gate-drain capacitance, and switching losses, and fundamentally eliminates the risk of bipolar degradation.

The present invention relates to a method of treating a catalyst made from SiC substrates. The method includes subjecting the catalyst made from SiC substrates in the presence of at least a fluxing agent to heat from a flame generated from oxyfuel gas flowing from the lance, thereby resulting in the oxidation of the SiC bearing material.

This invention discloses a transfer device and method for low-dimensional thin films, belonging to the field of materials science and technology. The transfer device includes a tank containing a base, with a support frame mounted above the base. A spinning assembly is mounted on the support frame. The spinning assembly includes a spinning column and an eccentric floating joint and a pressure head sequentially connected below the spinning column. The spinning column and the support frame are movably connected via a connecting mechanism. During the low-dimensional thin film transfer process, rotating the spinning column causes the pressure head to move downwards, pressing the sample to be transferred tightly against the target substrate. Adding liquid to the tank removes the sacrificial layer, separating the thin film from the original substrate. Subsequent heat treatment achieves the transfer of the functional thin film to the target substrate. This device and method can compensate for flatness deviations between the sample and the substrate, reduce local stress concentration, improve the integrity of low-dimensional thin film transfer, and the transfer process does not require a flexible support substrate.

A method of forming two semiconductor wafers from a single reuseable semiconductor wafer is disclosed. The two semiconductors can be used for wafer processing or to generate new semiconductor wafers. A patterned layer is formed in a silicon carbide (SIC) substrate. The patterned layer includes a heatable material. An epitaxial layer is grown by epitaxial lateral overgrowth overlying the patterned layer to form a surface overlying the SiC substrate. At least one epitaxial layer by epitaxial vertical overgrowth is grown overlying the epitaxial layer. The heatable material is heated by one or more lasers to fracture or weaken the patterned layer. The epitaxial layer and the at least one epitaxial layer comprises a SiC epitaxial substrate. The SiC substrate is separated from the SiC epitaxial substrate.

The application provides a SiC substrate and an interface state improvement method thereof, and the interface state improvement method comprises the following steps: performing vapor phase cleaning on the surface of the SiC substrate by using dichloroethylene in an oxygen-containing atmosphere; performing first annealing on the cleaned SiC substrate in a mixed atmosphere of N2 and N2O; performing oxidation treatment on the surface of the SiC substrate after the annealing treatment, so as to form a silicon oxide layer; performing second annealing on the SiC substrate after the oxidation treatment in a mixed atmosphere of N2 and N2O; and the volume ratio of N2O to N2 in the second annealing atmosphere is greater than the volume ratio of N2O to N2 in the first annealing atmosphere. By gradient design and synergistic optimization of the gas partial pressure and temperature of the annealing process before and after the oxidation, gradient and controllable doping of nitrogen atoms are realized, and then accurate control from "surface pre-passivation" to "interface depth modification" is realized, so that the interface quality of the gate oxide layer is more effectively improved, and the SiC / SiO2 interface state density is obviously reduced.

A semiconductor structure 200 comprising: a first semiconductor layer 110 (e.g. SiC substrate); a second semiconductor layer 115 (e.g. AlN nucleation layer); and an interlayer region 210 (e.g. carbon

The application relates to the technical field of conductor devices, and provides a gallium nitride HEMT device, which comprises a P-type polycrystalline SiC substrate, macroscopically measured physical properties of the polycrystalline SiC substrate are isotropic, formation of a single crystal SiC layer is excluded on the polycrystalline SiC substrate, an N-type gallium nitride buffer layer is formed on the polycrystalline SiC substrate, macroscopically measured physical properties of the gallium nitride buffer layer are anisotropic, and an HEMT functional layer is formed on the gallium nitride buffer layer; heat of the HEMT functional layer is transmitted to the isotropic polycrystalline SiC substrate through the anisotropic gallium nitride buffer layer. The application solves the technical problems of poor heat dissipation and high cost of a high-resistance single crystal SiC substrate of a traditional gallium nitride HEMT device.

A graphene / 4H-SiC alpha particle detector and a preparation method thereof, and relate to the technical field of semiconductor radiation detectors. The detector comprises: a 4H-SiC substrate, and an n-type epitaxial layer located on the upper surface of the 4H-SiC substrate; an ohmic contact electrode formed on the lower surface of the 4H-SiC substrate; and a Schottky incident window electrode formed on the upper surface of the n-type epitaxial layer; wherein the Schottky incident window electrode is composed of graphene with an atomic level thickness, and the graphene forms a Schottky contact with the n-type epitaxial layer. The atomic level thickness of graphene is used to suppress the "dead layer" effect of the incident window, thereby improving the energy resolution of the detector.

Provided is a silicon carbide semiconductor device capable of suppressing discharge occurring when a reverse bias is applied. A silicon carbide semiconductor device (100) has an n-type epitaxial layer (2) provided on a SiC substrate (1), a surface electrode (10) provided on the epitaxial layer (2), and a p-type electric field relaxation region (3) provided in an upper layer portion of the epitaxial layer (2) in a terminal region. A first protective film composed of an interlayer insulating film (23) covering at least a portion of the electric field relaxation region (3) and a protective oxide film (24) is provided on the epitaxial layer (2). A second protective film composed of a polyimide protective film (12) is provided so as to cover at least a portion of the surface electrode (10) outside, the first protective film, and the epitaxial layer (2) with a silicon nitride film (81) interposed therebetween. The silicon nitride film (81) extends beyond the second protective film at both an inside end portion and an outside end portion of the second protective film.

The present application provides a new technology related to a SiC substrate and a SiC semiconductor having a dislocation conversion layer capable of reducing resistance. The present application is a SiC substrate and a SiC semiconductor device including a dislocation conversion layer (12) having a doping concentration of 1 x 10 15 cm ‑3 above. By including a dislocation conversion layer (12) having such a doping concentration, the propagation of basal plane dislocations to produce a high-resistance laminated defect can be suppressed, and the resistance during the manufacture of a SiC semiconductor device can be reduced.