157 results about "Saturation current" patented technology

The invention discloses a series-parallel system transient stability analysis and fault ride-through control method considering current limiting, and belongs to the field of power fault analysis. In order to reveal an action mechanism of a current amplitude limiting and converter coupling effect on the transient synchronization stability of the hybrid system, the method comprises the following steps: firstly, considering the influence of control mode switching of a constructed network type converter, and establishing a transient analysis model of the hybrid system considering a current amplitude limiting link; then, based on a phase plane method, analyzing an action rule of converter control parameters on system transient stability, determining an optimal active power reference value and a saturation current phase angle of the grid-forming converter during a fault period, and proposing a fault ride-through control strategy according to the optimal active power reference value and the saturation current phase angle; and finally, verifying the correctness of theoretical analysis and the effectiveness of the proposed control strategy through multi-working-condition simulation.

The invention belongs to the technical field of power devices, and provides a silicon carbide power device, a preparation method thereof and a chip, a plurality of P-type floating islands are arranged between an N-type drift region and a top epitaxial region, so that the clamping effect on saturation current can be increased, the short-circuit characteristic is strengthened, and the performance of the device is improved. Meanwhile, the self-depletion effect of the P-type floating island is beneficial to reducing capacitance between the first electrode layer and the grid electrode in the device, the switching characteristic of the device is improved, and the trade-off relationship between breakdown voltage and on-resistance can be effectively balanced under the condition of a relatively shallow P-type well region and a relatively deep doped current expansion region, so that the performance of the device is improved. On-resistance of the device is optimized on the premise that breakdown voltage is not affected, and the requirement of high-power application for device performance is met.

The invention discloses a temperature measurement method, system, medium and equipment integrating a terminal and an electric energy meter, and the method comprises the steps: obtaining a basic temperature value through measuring the voltage difference of a PN junction of a voltage difference triode based on a dynamic matching method; a pre-stored segmentation error compensation model is called to correct the basic temperature value, and a final temperature value is output; through collaborative design of a dynamic matching method and a segmented error compensation model, the problem of full-temperature-range measurement error caused by dynamic change of saturation current IS in operation is solved. Compared with a mode of correcting the saturation current IS initial value only through factory single-point fine adjustment in the prior art, the embodiment of the invention can effectively cope with the dynamic fluctuation of the saturation current IS parameter in the operation process, thereby realizing more stable temperature measurement.

The invention discloses an analytical calculation method suitable for the magnetic saturation current of a high-voltage shunt reactor under a resonance working condition. The method comprises the following steps: establishing an electromagnetic coupling equivalent circuit model under the resonance working condition of the shunt reactor considering the magnetic saturation characteristic of an iron core; dividing the magnetization characteristic of the iron core into an unsaturated section and a saturated section through piecewise linearization processing of the magnetization curves, and setting the slopes of the two sections of magnetization curves and the magnetic field intensity at the knee point of a demarcation point; according to the working state of the reactor, constructing an electromagnetic coupling equation set containing a first-order conducting term coefficient in an unsaturated state, and deducing a time domain analytical expression of winding current; constructing an electromagnetic coupling equation set considering a zero-sequence coupling effect in a saturated state, simplifying resistance parameters, and then deducing a current solution expression in an equivalent inductance matrix form; the current value of the three-phase winding of the shunt reactor is monitored in real time, when the current amplitude of the winding reaches a knee point value, state switching is triggered, the final value of the previous state is used for updating the initial condition of the next state, and the current waveform is solved.

The invention discloses a method for testing trajectory transport parameters of a pulse-excited transistor at an ultralow temperature, and belongs to the field of semiconductor device characterization. According to the method, the self-heating effect intensity of a device is actively controlled by adjusting the pulse time at the environment temperature lower than 10K, and the source-drain saturation current of the transistor in different self-heating states is measured; the true temperature of the channel is inverted by using source-drain saturation current in different self-heating states; and calculating the back scattering probability and the ballistic transport efficiency by researching the dependency relationship between the changes of the threshold voltage and the source-drain saturation current and the channel temperature. According to the method, parameter extraction errors caused by inconsistency of the environment temperature and the channel temperature in a traditional method are solved, the intrinsic ballistic transport efficiency parameters of the device can be accurately obtained, and the method is suitable for high-performance planar transistors with silicon, germanium and III-V group compounds as carrier channels, fin type three-dimensional grids and transistors with ring gate-nanowire structures.

An improved silicon carbide (SiC) planar MOSFET having at least one buried P-shield (BPS) region including one center portion and two side portions for the gate oxide electric field and saturation current reductions is disclosed. Two saturation current pitching (SCP) structures formed in two Junction Field Effect Transistor (JFET) regions sandwiched between the side portions and the center portion of the BPS region limit a saturation current of the device in a forward conduction stage for the short-circuit capability improvement. Moreover, a Junction barrier Schottky diode (JBSD) is integrated with the SiC MOSFET in a location between the two adjacent split gate electrodes for the reverse conduction switching loss reduction.

The purpose of the present disclosure is to provide a technique capable of suppressing a decrease in saturation current while reducing the amount of gate charge. This semiconductor device is provided with: a semiconductor substrate provided with a drift layer, a carrier storage layer, and a base layer; and a two-stage active trench structure provided on the semiconductor substrate. The thickness of the lower-level insulating film in contact with the side portion of the lower-level electrode is thicker than the thickness of the upper-level insulating film in contact with the side portion of the upper-level electrode, and at least one of conditions (a), (b) and (c) is satisfied. The lower end of the upper electrode is positioned above a position at which the integrated value of the impurity concentration of the carrier storage layer in the vertical direction is half.

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

The application provides a method for reducing epitaxial resistance, and provides a semiconductor structure, which at least comprises: a source-drain region and a gate stack of an NMOS region; a source-drain region and a gate stack of a PMOS region; a first protective layer covering the source-drain region and the gate; the first protective layer on the PMOS region is opened by using photoetching and etching to form a first sidewall on the sidewall of the gate stack; a first epitaxial layer containing ion doping and a first cap layer on the first epitaxial layer are formed on the source-drain region of the PMOS region; the source-drain region of the PMOS region is subjected to rapid thermal annealing treatment, so that the doping ions in the first epitaxial layer diffuse to the first epitaxial layer at the bottom of the sidewall; the remaining first protective layer is removed, and then a second protective layer covering the NMOS region and the PMOS region is formed. The application reduces the channel resistance of the PMOS source-drain region to the gate edge, and improves the Idsat (saturation current) and Ioff (off-state current) performance of the device.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

The invention discloses a vertical channel thin film transistor for a 2T0C DRAM (Dynamic Random Access Memory) and a manufacturing method of the vertical channel thin film transistor. Comprising a substrate, a source electrode deposited on the substrate, an interlayer dielectric layer covering the source electrode, a gate dielectric layer deposited on the surface of the interlayer dielectric layer and a drain electrode arranged in the gate dielectric layer, and the drain electrode forms a conical ring shape; a vertical cylindrical channel is formed in the interlayer dielectric layer, and the bottom of the channel is located in the source electrode; and the vertical cylindrical channel is filled with an active layer. According to the invention, the regulation and control capability of the grid electrode is obviously enhanced through distributed grid electrode control, the short-channel effect is effectively inhibited, the saturation current density is greatly improved, the performance of the transistor is obviously improved, and the transistor is suitable for the fields of artificial intelligence accelerators, storage and calculation integrated chips, high-bandwidth memories and the like and has wide application prospects. And the requirements of high-performance calculation and storage application can be met.

This application belongs to the field of power device technology and provides a silicon carbide power device and its fabrication method and chip. By setting multiple P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating islands helps to reduce the capacitance between the first electrode layer and the gate in the device, thereby improving the switching characteristics of the device. Furthermore, in the case of a shallow P-type well region and a deep doped current extension region, the trade-off between breakdown voltage and on-resistance can be effectively balanced, so that the on-resistance is optimized without affecting the breakdown voltage, thus meeting the performance requirements of high-power applications.

Semiconductor device (100), in particular a vertical transistor device, preferably based on gallium nitride, wherein the semiconductor device for current conduction is based on a 2-dimensional electron gas (2DEG).

The application discloses a method for P-type doping of an organic field effect transistor semiconductor layer and an organic field effect transistor prepared by the method. 2,3,5,6-tetrafluoro-7,7',8,8'-tetracyanoquinodimethane (F4-TCNQ) is dissolved in an orthogonal solvent of the organic semiconductor layer as a P-type dopant, and the P-type dopant is spin-coated on an organic semiconductor layer film which has been spin-coated in an air atmosphere, and the doping is activated by rapid thermal annealing, so that the problems caused by hopping transmission and Coulomb traps in charge transport are improved, the threshold voltage is reduced, and the on-off ratio is improved. For a P-type field effect transistor, the P-type doping enhances hole transport, effectively improves the saturation current, and suppresses electron transport, so that the power consumption is reduced when the transistor is turned off. The doping method is based on a solution method and is simple in process and low in preparation cost, can be applied to large-scale production, and has a good application prospect in flexible and portable electronic devices.

According to the trench gate silicon carbide MOSFET device and the preparation method thereof, a source electrode step trench and a P-type shielding layer are introduced to form a follow current nMOS together with a CSL region, a P-type base region and an N-type ohmic contact region, and form a self-bias pMOS together with the CSL region, the P-type base region and a P-type ohmic contact region. During reverse conduction, the source trench freewheeling nMOS is conducted, bipolar conduction of the body diode is inhibited, and the long-term working reliability of the device is improved; in a short-circuit state, the pMOS is started, the P-type shielding layer is grounded, the depletion region is rapidly expanded, pinch-off is formed with the depletion region of the P-type shielding region at the bottom of the trench gate, a current path is limited, saturation current is reduced, and the short-circuit capability of the device is improved; and in a blocking state, the pMOS is opened, and the P-type shielding layer is grounded, so that the electric field intensity of the oxide layer is effectively reduced. According to the invention, the forward conduction capability and low switching loss of the device are ensured, the short circuit and third quadrant capability of the device is improved, and the transient robustness of the device is obviously improved.

The present application discloses a multiphase full-bridge drive system for motor driving, comprising: a multiphase full-bridge circuit comprising at least three identical half-bridge circuits, each half-bridge circuit comprising a first and a second transistor, and the first transistor having a higher short-circuit withstand capability than the second transistor and the short-circuit saturation current of the first transistor being lower than the short-circuit saturation current of the second transistor, each half-bridge circuit further comprising a first and a second transistor drive circuit, each connected to a control terminal of the first transistor and a control terminal of the second transistor in order to control the first and the second transistor;a controller that is connected to the first and second transistor drive circuits of each half-bridge circuit to control the multi-phase full-bridge circuit for generating a multi-phase target drive voltage and thus for motor driving.

An object is to provide a technology that can suppress a decrease in the saturated current while reducing the amount of gate charge. A semiconductor device includes a semiconductor substrate with a drift layer, a carrier storage layer, and a base layer, and a two-stage active trench structure in the semiconductor substrate. A thickness of a lower-stage insulating film in contact with a side portion of a lower stage electrode is greater than a thickness of an upper-stage insulating film in contact with a side portion of an upper stage electrode, at least one of conditions (a), (b), or (c) is satisfied, and a lower end of the upper stage electrode is located above a position at which an integrated value of impurity concentrations of the carrier storage layer in a vertical direction is halved.

The invention provides a large-current inductor. The large-current inductor comprises a shell, a middle column and a coil. The at least two coils are sequentially wound on the middle column and are used for generating an inductive effect through accessed current; a wiring end of the coil penetrates through the shell to form a pin, and the pin is used for being connected with a circuit board; the shell is provided with a containing cavity, and the containing cavity is used for containing the middle column and the coil; the ui value of the shell is 900 to 3500, and the Bm value of the shell is 0.4 T to 0.6 T. By means of the stable saturation current curve characteristic of the ferrite magnetic core material, the large-current inductor can maintain stable current linearity, and the current stability of the inductor is improved. In addition, the ferrite magnetic core has higher surface impedance and small high-frequency eddy current loss and magnetic hysteresis loss, so that the characteristic of low loss can be maintained at higher switching frequency, and the high-frequency application requirement is met.

The application discloses a granulated powder with high saturation performance for inductance and a preparation method, and relates to the technical field of electronic components. The composite powder is composed of 40-60 parts of FeSiCr coarse powder, 25-35 parts of FeSi / amorphous fine powder and 5-15 parts of carbonyl iron powder in terms of mass fraction. The particle size of the FeSiCr coarse powder is 45-75 microns, the particle size of the FeSi / amorphous fine powder is 5-15 microns, and the particle size of the carbonyl iron powder is 1-3 microns. The ternary multi-particle size grading of the FeSiCr coarse powder, the FeSi / amorphous fine powder and the carbonyl iron powder is combined with the inert atmosphere protection mixing process, so that the powder oxidation is effectively inhibited, the effective performance retention rate of the magnetic powder is greater than or equal to 96%, the industrial problem that a single soft magnetic powder cannot simultaneously consider high saturation current and low high-frequency loss is solved from the powder material formula level, the saturation current of the magnetic core is increased by more than 15% than that of a single commercially available FeSiCr powder, the high-frequency loss is reduced by more than 20%, and the fluctuation deviation of the wide-frequency permeability is less than or equal to 5%.

This invention provides a high-reliability trench-gate silicon carbide MOSFET device, comprising: an N+ type substrate, an N- type drift region, a first P region, a P+ contact region, an N+ contact region, an N-type equivalent resistance region located between the first P region and the N+ contact region, a gate dielectric layer, a trench gate, an isolation dielectric layer, a source electrode, and a drain electrode. The SiC MOSFET device proposed in this invention adds an N-type equivalent resistance region, which acts as a series resistor. When a short circuit occurs, this reduces the saturation current of the device and improves its short-circuit capability.

This invention provides a test circuit for a ring oscillator (RO). In existing ring oscillator design rules, the NMOS and PMOS transistors in the same inverter are usually MOS field-effect transistors with the same threshold voltage level. This invention flexibly applies test key design rules and logic operations to design a ring oscillator with mixed NMOS and PMOS threshold voltage types (Mixed Vt). This invention can investigate the impact of the saturation current ratio of NMOS and PMOS transistors on the DC performance of the ring oscillator within a single wafer, solving the problem of measurement errors caused by differences between different wafers; it can obtain more sets of experimental designs, save production resources, reduce R&D costs, and improve testing efficiency.

The invention relates to the field of photovoltaic power generation, and aims to provide a method for calculating open-circuit voltage and short-circuit current of a photovoltaic cell. Comprising the following steps: enabling a photovoltaic cell to work at any two different set steady-state working points by changing the impedance of a power electronic converter, and respectively applying trace disturbance to form new steady-state working points; the port voltage and current values of the photovoltaic cell are sampled for the four steady-state working points, and the reverse saturation current, the open-circuit voltage and the short-circuit current of the photovoltaic cell are obtained through solving based on the photovoltaic effect basic equation and the voltage and current differential relation when the photovoltaic cell is at the steady-state working points. According to the invention, the power electronic converter is prevented from being regulated under the extreme conditions of open-circuit voltage or short-circuit current and the like, interference on the operation stability of the converter is avoided, power generation power loss is avoided, and system safety and power generation benefits are improved; the calculation process can be simplified, hardware equipment does not need to be additionally added or upgraded, and the system cost can be greatly reduced.

The application discloses an AI-based diode model parameter automatic extraction and optimization method, and belongs to the technical field of electronic design.The application solves the problem that the existing diode model parameter extraction method is seriously dependent on manual experience, the process is complicated and time-consuming, and it is difficult to stably obtain high-precision and strong generalization capability model parameters from nonlinear data under the influence of temperature and process deviation.The application constructs an intelligent mapping model from macro electrical characteristics to microscopic model parameters by adaptively denoising and multidimensional feature engineering on measured data, and finally generates a high-fidelity diode electronic design model by combining global optimization of physical constraints, so as to realize high-precision, high-efficiency and full-automatic extraction and optimization of key model parameters such as diode saturation current, ideal factor and series resistance, thereby improving the efficiency, automation level and cross-condition robustness of model extraction.

Light-emitting device configured to emit radiation, comprising: a substrate (50); an epitaxic structure (20) comprising in succession a first DBR stack (21), a light-emitting stack (22), a second DBR stack (23) and several discrete first and second contact regions (241), wherein the light-emitting device emits coherent light having a far-field angle of less than 15 degrees, at a forward current between a laser threshold current and a saturation current therein, and incoherent light at a forward current less than the laser threshold current, wherein the epitaxial structure (20) is arranged on the substrate (50) and further comprises: several first radiation-emitting areas in a first column; and several second radiation-emitting areas in a second column; a conductive layer (60) on the epitaxial structure (20); wherein the contact areas (241) are arranged in a two-dimensional field and are configured to direct a spatially limited current in the light-emitting device to the several first radiation-emitting areas and the several second radiation-emitting areas; and wherein one of the several first contact areas includes a first latitude (w3') and one of the several second contact areas includes a second latitude (w3) that differs from the first latitude (w3').

This invention provides a modeling circuit, method, and model for a MOSFET containing a parasitic BJT. The modeling method includes: obtaining the saturation current, maximum DC current gain, and base-emitter junction non-ideal saturation current of the BJT under different active region areas in the SPICE model of the MOSFET; fitting the saturation current, maximum DC current gain, and base-emitter junction non-ideal saturation current of the BJT to the active region area to obtain the relationship between the saturation current, maximum DC current gain, and base-emitter junction non-ideal saturation current of the BJT under different active region areas; adding the relationship to the SPICE model of the MOSFET to obtain the MOSFET model containing the parasitic BJT. This invention reflects the parasitic BJT characteristics of the MOSFET during simulation.

A reference current generator includes two transistors, a resistor and a mirroring circuit. The first transistor includes a source receiving a supply voltage, a drain connected with a first node, and a gate connected with a second node. The second transistor includes a source receiving the supply voltage, and a drain and a gate connected with a third node. The resistor is connected between the second node and the third node. The mirroring circuit includes an input terminal receiving an input current, a first mirrored terminal connected with the second node and a second mirrored terminal connected with the first node. The first mirrored terminal and the second mirrored terminal generate a first mirroring current and a second mirroring current respectively. The first transistor generates a saturation current. A reference current is equal to the saturation current minus the second mirroring current.

A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.

The application discloses a high short-circuit resistance current carrier storage trench gate IGBT device, which is configured to comprise a plurality of interval trenches (1), and a P+ area (2) for improving short-circuit resistance of the IGBT is formed between adjacent trenches (1). The IGBT device provided by the application forms the P+ area periodically between the trenches, so that the trench sidewall of the P+ area cannot form a conductive channel, thereby reducing the overall channel density, reducing the saturation current of the device, and greatly improving the short-circuit resistance of the device.

The invention provides a method for testing the saturation current of an IO port, and the method comprises the steps: a, measuring a first average current flowing through a source input end corresponding to an MOS tube when the MOS tube in the IO port is in a cut-off state; b, an MOS tube in the IO port is controlled to be switched between a conduction stage and a cut-off stage, and the MOS tube is always in a saturated state in the conduction stage; c, measuring a second average current flowing through the source input end corresponding to the MOS tube in the process of the step b; and d, obtaining the IO port saturation current according to the difference value of the first average current and the second average current and the proportion of the conduction time T1 and the cut-off time T2 of the MOS tube.

The invention belongs to the technical field of power devices, and provides a silicon carbide trench gate power device with a floating P-type ring and a preparation method thereof, and a chip, a P-type shielding region is formed at the bottom of a groove of an N-type drift region, and a gate dielectric layer is formed on the inner wall of the groove on the P-type shielding region. A plurality of P-type floating ring regions with the same width are arranged in regions on two sides of an N-type drift region, and the plurality of P-type floating ring regions on the same side are sequentially arranged towards a silicon carbide substrate along a P-type shielding region, so that a floating PN junction is formed, an electric field extends downwards towards two sides, the distribution range of a high electric field in the drift region can be expanded, the area of a space charge region is increased, and the performance of the device is improved. The saturation current of the device is effectively reduced, the endurance capability of the device under a short-circuit test is improved, and the reliability of the device is improved.