272 results about "Saturation current" patented technology

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention discloses a series-parallel system transient stability analysis and fault ride-through control method considering current limiting, and belongs to the field of power fault analysis. In order to reveal an action mechanism of a current amplitude limiting and converter coupling effect on the transient synchronization stability of the hybrid system, the method comprises the following steps: firstly, considering the influence of control mode switching of a constructed network type converter, and establishing a transient analysis model of the hybrid system considering a current amplitude limiting link; then, based on a phase plane method, analyzing an action rule of converter control parameters on system transient stability, determining an optimal active power reference value and a saturation current phase angle of the grid-forming converter during a fault period, and proposing a fault ride-through control strategy according to the optimal active power reference value and the saturation current phase angle; and finally, verifying the correctness of theoretical analysis and the effectiveness of the proposed control strategy through multi-working-condition simulation.

The invention discloses an NAND flash memory, a memory and electronic equipment. Data of a plurality of pages can be read at the same time under the same face in the NAND, the saturation current of each page can be different, and / or the time for reading the data of each page can be different, so that the data recorded by each page is different, the total current of a reading circuit is different, and the voltage drop speed of a discharge capacitor CSO is different. When the NAND flash memory reads data of a plurality of pages, the voltage comparison unit can be used for detecting the relation between the voltage of the discharge capacitor CSO and the comparison voltage so as to accurately read data recorded in each page, and confusion between the read data and the pages is avoided.

The invention discloses a current saturation algorithm-based converter control mode switching method and system, and the method comprises the steps: building an outer loop voltage control equation of a fault-free network-building converter, and defining that the converter operates in a constant voltage mode; current limitation of a device under the fault is considered, a dq-axis current reference value under the fault is generated based on a current saturation algorithm, and a current converter is defined to operate in a current limiting mode; after a fault occurs in the constant voltage mode, whether the current amplitude of the converter exceeds the saturation current amplitude which can be borne by the device at the fault moment is judged, and the converter enters the current limiting mode from the constant voltage mode to operate; in the current limiting mode, when a difference value between an actual value and a reference value of active power output by the converter is smaller than a given value, exiting the current limiting mode, and entering a constant voltage mode for operation; and finally, on the basis of a switching rule of the converter between the CVC mode and the CLC mode, obtaining a switching model after the network-forming converter suffers from a fault. According to the invention, automatic switching can be realized to avoid the device overcurrent problem, and the logic is simple and effective.

The invention relates to a weak current signal detection system and method based on a fluxgate, and the system comprises an excitation module, a range selection module, a power amplification module, a fluxgate magnetic core coil, a sampling resistor, a differential amplification module and a data processing module which are connected in sequence, the magnetic core current reaches saturation current; the range selection module is used for adjusting the gain of the power amplification module; the power amplification module is used for amplifying the excitation signal; the fluxgate magnetic core coil is used for sensing current to be measured; the sampling resistor is used for sampling saturation current of a magnetic core coil of the fluxgate; the differential amplification module is used for amplifying saturation current of a magnetic core coil of the fluxgate; and the data processing module performs time difference calculation on the amplified saturation current through resampling, and outputs a weak current detection result. Compared with the prior art, the hardware cost can be reduced while the measurement precision is improved.

The present disclosure describes moving one phase of the TLVR topology from a primary side of the topology to a secondary side. By doing so, the secondary side phase is able to drive the TLVR secondary winding current with equal magnitude and opposite direction to the primary winding current for both transient and DC. Therefore, all the TLVR inductors see zero bias of magnetic flux in the cores under any loading conditions. With this feature, TLVR inductor size can be significantly reduced by reducing the saturation current. As another option, the inductor size can remain unchanged and the Zero-Bias TLVR can be optimized for power efficiency by increasing the inductance. With higher inductance, the voltage regulator switching frequency can be reduced accordingly to boost up the power efficiency.

The invention belongs to the technical field of power devices, and provides a silicon carbide power device, a preparation method thereof and a chip, a plurality of P-type floating islands are arranged between an N-type drift region and a top epitaxial region, so that the clamping effect on saturation current can be increased, the short-circuit characteristic is strengthened, and the performance of the device is improved. Meanwhile, the self-depletion effect of the P-type floating island is beneficial to reducing capacitance between the first electrode layer and the grid electrode in the device, the switching characteristic of the device is improved, and the trade-off relationship between breakdown voltage and on-resistance can be effectively balanced under the condition of a relatively shallow P-type well region and a relatively deep doped current expansion region, so that the performance of the device is improved. On-resistance of the device is optimized on the premise that breakdown voltage is not affected, and the requirement of high-power application for device performance is met.

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The manufacturing method comprises the steps that a substrate is provided, a gate structure and side wall structures on the two sides are formed on the substrate, and a lightly doped region and a heavily doped region are formed in the portions, on the two sides of the gate structure, of the substrate; forming a first etching stop layer covering the substrate, the gate structure and the side wall structure on the substrate; forming an opening in the first etching stop layer by etching, wherein the opening exposes a part of the heavily doped region and at least a part of the gate structure; forming a compensation epitaxial layer in the opening, wherein the compensation epitaxial layer covers a part of the heavily doped region; at least metallizing the compensation epitaxial layer to form a metal silicide layer; forming an interlayer dielectric layer on the substrate and the metal silicide layer; etching the interlayer dielectric layer to the metal silicide layer to form a connecting hole; and forming a barrier layer and a conductive structure in the connecting hole. According to the semiconductor device and the manufacturing method thereof, the saturation current can be improved, and the performance and the yield of the semiconductor device can be improved.

The embodiment of the invention provides a VDMOS device. The VDMOS device comprises a substrate, an epitaxial layer located on the substrate and a drain electrode located on the back side of the substrate. The well region of the first doping type is formed downwards from the upper surface of the epitaxial layer; the source region of the second doping type is formed downwards from the upper surface of the well region; the first doping region of the first doping type is downwards formed in the source region from the upper surface of the source region, and the first doping region and the source region form a PN junction which is defined as a secondary PN junction; wherein the parts of the source region, which are positioned on the two sides of the first doped region, are a source region first side part and a source region second side part; the top of the first side portion of the source region is used for being grounded, and when the VDMOS device is switched on, the potential change of the second side portion of the source region is positive, and reverse bias of the second-level PN junction is achieved. The VDMOS device solves the technical problem that a traditional VDMOS device is insufficient in short circuit capacity along with increase of saturation current.

The invention discloses a computing power inductance device and a preparation method thereof. The computing power inductance device comprises a magnetic core, a conductor and a terminal electrode, the conductor is arranged in the magnetic core and led out of the magnetic core to form the terminal electrode, a soft magnetic composite material of the magnetic core comprises flat particles, and the flat particles are arranged in the soft magnetic composite material of the magnetic core. The ratio of the maximum width of the bottom / top surface of the flat particles to the thickness of the flat particles is 2.5-15. The computing force inductance device is higher in inductance value, higher in saturation current, higher in temperature rise current, lower in direct current resistance and more excellent in comprehensive electrical performance.

A semiconductor device includes: a semiconductor layer; the gate structure is positioned on the upper surface of the semiconductor layer; the drift region of the second doping type extends into the semiconductor layer from the upper surface of the semiconductor layer, the source region and the drain region of the second doping type are located in the semiconductor layer, and the drain region and the drift region are located on the same side of the gate structure. And the first dielectric layer at least covers a part of the upper surface of the drift region adjacent to the gate structure, wherein the first dielectric layer has a high dielectric constant. According to the invention, the first dielectric layer is made of a material with a high dielectric constant, so that the capacitance between the grid electrode and the drift region is larger, the coupling effect is stronger, the JFET effect of the semiconductor device is relieved, and the saturation current density of the device is increased.

The invention discloses a temperature measurement method, system, medium and equipment integrating a terminal and an electric energy meter, and the method comprises the steps: obtaining a basic temperature value through measuring the voltage difference of a PN junction of a voltage difference triode based on a dynamic matching method; a pre-stored segmentation error compensation model is called to correct the basic temperature value, and a final temperature value is output; through collaborative design of a dynamic matching method and a segmented error compensation model, the problem of full-temperature-range measurement error caused by dynamic change of saturation current IS in operation is solved. Compared with a mode of correcting the saturation current IS initial value only through factory single-point fine adjustment in the prior art, the embodiment of the invention can effectively cope with the dynamic fluctuation of the saturation current IS parameter in the operation process, thereby realizing more stable temperature measurement.

The invention provides a voltage environment self-adaptive adjusting method and system of a plug-in adapter, and is applied to the field of electric data processing. Under-voltage compensation and over-voltage compensation can be automatically performed according to actual voltage conditions through a dynamic voltage compensation mechanism, so that the adapter can still maintain stable output in an extremely low or extremely high voltage environment, and adapter damage caused by abnormal voltage is avoided; meanwhile, key element parameters such as the turn ratio, the magnetic flux density and the saturation current of the transformer are tested, it is ensured that the elements work within the design range, in combination with activation of the active clamping circuit, the problems of voltage spikes and overcurrent can be effectively solved, the service life of the key elements is prolonged, and damage is avoided.

The invention discloses an analytical calculation method suitable for the magnetic saturation current of a high-voltage shunt reactor under a resonance working condition. The method comprises the following steps: establishing an electromagnetic coupling equivalent circuit model under the resonance working condition of the shunt reactor considering the magnetic saturation characteristic of an iron core; dividing the magnetization characteristic of the iron core into an unsaturated section and a saturated section through piecewise linearization processing of the magnetization curves, and setting the slopes of the two sections of magnetization curves and the magnetic field intensity at the knee point of a demarcation point; according to the working state of the reactor, constructing an electromagnetic coupling equation set containing a first-order conducting term coefficient in an unsaturated state, and deducing a time domain analytical expression of winding current; constructing an electromagnetic coupling equation set considering a zero-sequence coupling effect in a saturated state, simplifying resistance parameters, and then deducing a current solution expression in an equivalent inductance matrix form; the current value of the three-phase winding of the shunt reactor is monitored in real time, when the current amplitude of the winding reaches a knee point value, state switching is triggered, the final value of the previous state is used for updating the initial condition of the next state, and the current waveform is solved.

The invention discloses a method for testing trajectory transport parameters of a pulse-excited transistor at an ultralow temperature, and belongs to the field of semiconductor device characterization. According to the method, the self-heating effect intensity of a device is actively controlled by adjusting the pulse time at the environment temperature lower than 10K, and the source-drain saturation current of the transistor in different self-heating states is measured; the true temperature of the channel is inverted by using source-drain saturation current in different self-heating states; and calculating the back scattering probability and the ballistic transport efficiency by researching the dependency relationship between the changes of the threshold voltage and the source-drain saturation current and the channel temperature. According to the method, parameter extraction errors caused by inconsistency of the environment temperature and the channel temperature in a traditional method are solved, the intrinsic ballistic transport efficiency parameters of the device can be accurately obtained, and the method is suitable for high-performance planar transistors with silicon, germanium and III-V group compounds as carrier channels, fin type three-dimensional grids and transistors with ring gate-nanowire structures.

An improved silicon carbide (SiC) planar MOSFET having at least one buried P-shield (BPS) region including one center portion and two side portions for the gate oxide electric field and saturation current reductions is disclosed. Two saturation current pitching (SCP) structures formed in two Junction Field Effect Transistor (JFET) regions sandwiched between the side portions and the center portion of the BPS region limit a saturation current of the device in a forward conduction stage for the short-circuit capability improvement. Moreover, a Junction barrier Schottky diode (JBSD) is integrated with the SiC MOSFET in a location between the two adjacent split gate electrodes for the reverse conduction switching loss reduction.

The purpose of the present disclosure is to provide a technique capable of suppressing a decrease in saturation current while reducing the amount of gate charge. This semiconductor device is provided with: a semiconductor substrate provided with a drift layer, a carrier storage layer, and a base layer; and a two-stage active trench structure provided on the semiconductor substrate. The thickness of the lower-level insulating film in contact with the side portion of the lower-level electrode is thicker than the thickness of the upper-level insulating film in contact with the side portion of the upper-level electrode, and at least one of conditions (a), (b) and (c) is satisfied. The lower end of the upper electrode is positioned above a position at which the integrated value of the impurity concentration of the carrier storage layer in the vertical direction is half.

The present invention discloses a method for manufacturing a MOSFET structure and a MOSFET structure, the method comprising: performing ion implantation on a wafer to form a p-type shielding region, and etching a groove on the wafer, the wafer comprising a first current transmission layer and a second current transmission layer, the grooves being distributed on both sides of the second current transmission layer; forming a doped region on both sides of the second current transmission layer; growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer through photoresist and depositing polysilicon to form two gate regions; forming an oxidized dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxidized dielectric layer and the second current transmission layer, and depositing a drain region at the bottom of the wafer to perform ohmic contact and Schottky contact. The present invention protects the gate oxide and the Schottky contact region through the p-type shielding region and the doped region, controls the width of the conductive current path, reduces the saturation current, and improves the short-circuit capability and reliability.

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

The application provides a method for reducing epitaxial resistance, and provides a semiconductor structure, which at least comprises: a source-drain region and a gate stack of an NMOS region; a source-drain region and a gate stack of a PMOS region; a first protective layer covering the source-drain region and the gate; the first protective layer on the PMOS region is opened by using photoetching and etching to form a first sidewall on the sidewall of the gate stack; a first epitaxial layer containing ion doping and a first cap layer on the first epitaxial layer are formed on the source-drain region of the PMOS region; the source-drain region of the PMOS region is subjected to rapid thermal annealing treatment, so that the doping ions in the first epitaxial layer diffuse to the first epitaxial layer at the bottom of the sidewall; the remaining first protective layer is removed, and then a second protective layer covering the NMOS region and the PMOS region is formed. The application reduces the channel resistance of the PMOS source-drain region to the gate edge, and improves the Idsat (saturation current) and Ioff (off-state current) performance of the device.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

The present invention discloses a converter control mode switching method and system based on a current saturation algorithm. The method establishes an outer loop voltage control equation for a grid-type converter under fault-free conditions and defines the converter as operating in a constant voltage mode. Considering the current limit of devices under fault conditions, a dq axis current reference value under fault conditions is generated based on the current saturation algorithm and the converter is defined as operating in a current-limited mode. After a fault occurs in the constant voltage mode, the method determines whether the converter's current amplitude at the moment of the fault exceeds the saturated current amplitude that the device can withstand, and the converter switches from the constant voltage mode to the current-limited mode. In the current-limited mode, when the difference between the actual value of the converter's output active power and the reference value is less than a given value, the converter exits the current-limited mode and enters the constant voltage mode. Finally, based on the converter's switching rules between CVC and CLC modes, a switching model for the grid-type converter after a fault occurs is derived. The present invention can achieve automatic switching to avoid device overcurrent problems, with simple and effective logic.

The invention relates to a flux-weakening speed regulation control method and a flux-weakening speed regulation control device during high-speed operation of an IPMSM. The method comprises the following steps: establishing a mathematical model of an IPMSM in a d-axis and q-axis rotating coordinate system; based on the mathematical model of the IPMSM in the d-axis and q-axis rotating coordinate system, performing field weakening control by using a gradient descent algorithm, determining a field weakening operation region where the driving motor is located, and correcting d-axis and q-axis stator current set values of the corresponding field weakening control region; and based on the mathematical model of the IPMSM in the d-axis and q-axis rotating coordinate system, the weak magnetic operation region where the driving motor is located and the corrected d-axis and q-axis stator current set values, performing integral saturation current closed-loop control on the driving motor. The defects in the prior art can be overcome, and the dynamic and static response performance of the motor driving system is improved.

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate; forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer comprises at least two sub-isolation layers which are sequentially stacked on the semiconductor substrate; in the direction perpendicular to the semiconductor substrate, under a specific etching condition, the etching rate of the sub-isolation layer farthest from the semiconductor substrate is smaller than that of other sub-isolation layers; sequentially depositing a gate layer and a second isolation layer on the first isolation layer; a groove penetrating through the second isolation layer, the gate layer and the first isolation layer is formed, and in the portion, penetrating through the first isolation layer, of the groove, the size of the groove located at the end face portion, away from the semiconductor substrate, of the first isolation layer is the smallest. According to the invention, the inverted trapezoidal structure at the bottom of the trench can be optimized after etching, the resistance is reduced, and the control capability of the gate to the trench is improved, so that the saturation current of the transistor is increased, and the performance of the transistor is improved.

The invention discloses a vertical channel thin film transistor for a 2T0C DRAM (Dynamic Random Access Memory) and a manufacturing method of the vertical channel thin film transistor. Comprising a substrate, a source electrode deposited on the substrate, an interlayer dielectric layer covering the source electrode, a gate dielectric layer deposited on the surface of the interlayer dielectric layer and a drain electrode arranged in the gate dielectric layer, and the drain electrode forms a conical ring shape; a vertical cylindrical channel is formed in the interlayer dielectric layer, and the bottom of the channel is located in the source electrode; and the vertical cylindrical channel is filled with an active layer. According to the invention, the regulation and control capability of the grid electrode is obviously enhanced through distributed grid electrode control, the short-channel effect is effectively inhibited, the saturation current density is greatly improved, the performance of the transistor is obviously improved, and the transistor is suitable for the fields of artificial intelligence accelerators, storage and calculation integrated chips, high-bandwidth memories and the like and has wide application prospects. And the requirements of high-performance calculation and storage application can be met.

This application belongs to the field of power device technology and provides a silicon carbide power device and its fabrication method and chip. By setting multiple P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating islands helps to reduce the capacitance between the first electrode layer and the gate in the device, thereby improving the switching characteristics of the device. Furthermore, in the case of a shallow P-type well region and a deep doped current extension region, the trade-off between breakdown voltage and on-resistance can be effectively balanced, so that the on-resistance is optimized without affecting the breakdown voltage, thus meeting the performance requirements of high-power applications.

The invention relates to an SOI-LIGBT (Silicon On Insulator-Lateral Insulated Gate Bipolar Translator) device introducing a deep groove and a self-biased PMOS (P-channel Metal Oxide Semiconductor), and belongs to The device comprises a cathode P + region, a cathode P-well region, a cathode N + region, a drift region, a P-buffer region, an anode N-buffer region, an anode P + region, a main gate oxide layer, a polycrystalline silicon main gate, a deep trench oxide layer, a deep trench oxide layer, a polycrystalline silicon auxiliary gate, a silicon dioxide buried oxide layer and a substrate. According to the device, a self-biased PMOS (P-channel Metal Oxide Semiconductor) is integrated at a cathode, an extraction channel of excess carriers is provided during turn-off, the working frequency of the device in the application process is improved, saturation current is reduced during forward conduction of the device, the short-circuit safe working time of the device is prolonged, and the reliability and the safety of the device are improved; and the PMOS integrated with the cathode does not need to be controlled by an additional circuit, so that the feasibility of the device in the actual application process is improved, and the design difficulty of the driving circuit is reduced.

The invention provides a semiconductor structure, a manufacturing method, a chip and a circuit, and relates to the field of semiconductors. The semiconductor structure includes: a substrate; the well region is formed in the substrate; wherein the well region comprises a plurality of sub-well regions formed by ion implantation from outside to inside in sequence, and the relative atomic mass of the ions implanted in the sub-well region on the innermost side is larger than the relative atomic mass of the ions implanted in the other sub-well regions; the grid electrode is formed on the upper surface of the sub-well region on the innermost side of the well region in a step shape; and the side walls are formed on the two sides of the grid electrode. According to the invention, the oxidation enhancement diffusion effect and the transient enhancement effect can be reduced, so that the impurity concentration of the surface of the channel below the grid electrode does not rise too fast, the stability of the threshold voltage and saturation current of the device structure is ensured, and the performance of the finally formed semiconductor structure is improved.

The present invention relates to an IGBT device with a thyristor structure using self-biased MOS clamping, which can also be regarded as an integrated ETO device. The body region of the IGBT device is composed of multiple layers of P-type doped layers and N-type doped layers arranged alternately, and adjacent doped regions of the same conductive type are completely isolated by another conductive type doped region. The device of the present invention uses a self-biased MOS (Q2) to clamp the electric field shielding layer, so that the external control MOS (Q1, Q2) of the traditional ETO can be monolithically integrated into the device. At the same time, compared with the IGBT with a carrier storage layer, the self-biased MOS (Q2) clamps the drain potential of the MOS (Q1) in the structure of the present invention at a lower level, thereby greatly improving the doping concentration threshold of the carrier storage layer and reducing the on-state voltage drop of the device; and the clamped MOS drain potential can reduce the saturation current of the new structure, thereby increasing the short-circuit safe working area of ​​the new device.

The invention relates to the technical field of semiconductors, in particular to a groove type IGBT device and a manufacturing method thereof, and the method comprises a substrate, and a P-base region, a gate region and an emitter region which are located on the substrate; the P-base region is located between the gate regions, and the P-base region is in contact with the gate regions; the emitter region comprises an N + active region, a short circuit region, a latch region and an emitter metal region; the N + active region is located on the P-base region, located between the gate regions and located between the gate regions and the short circuit region; the short circuit regions are distributed on the P-base region at intervals, are positioned on the latch region and are in contact with the latch region; the latch region is located in the P-base region and is correspondingly located below the interval region between the short circuit regions; the spacer region is filled with the emitter metal region, and the emitter metal region covers the N + active region, the short circuit region and the gate region. According to the device structure, the saturation current of the IGBT device is effectively reduced, the anti-short-circuit capability of the IGBT is greatly improved, and the anti-latch-up capability of the IGBT device is improved at the same time.