102 results about "Saturation current" patented technology

The invention discloses a series-parallel system transient stability analysis and fault ride-through control method considering current limiting, and belongs to the field of power fault analysis. In order to reveal an action mechanism of a current amplitude limiting and converter coupling effect on the transient synchronization stability of the hybrid system, the method comprises the following steps: firstly, considering the influence of control mode switching of a constructed network type converter, and establishing a transient analysis model of the hybrid system considering a current amplitude limiting link; then, based on a phase plane method, analyzing an action rule of converter control parameters on system transient stability, determining an optimal active power reference value and a saturation current phase angle of the grid-forming converter during a fault period, and proposing a fault ride-through control strategy according to the optimal active power reference value and the saturation current phase angle; and finally, verifying the correctness of theoretical analysis and the effectiveness of the proposed control strategy through multi-working-condition simulation.

The invention discloses a method for testing trajectory transport parameters of a pulse-excited transistor at an ultralow temperature, and belongs to the field of semiconductor device characterization. According to the method, the self-heating effect intensity of a device is actively controlled by adjusting the pulse time at the environment temperature lower than 10K, and the source-drain saturation current of the transistor in different self-heating states is measured; the true temperature of the channel is inverted by using source-drain saturation current in different self-heating states; and calculating the back scattering probability and the ballistic transport efficiency by researching the dependency relationship between the changes of the threshold voltage and the source-drain saturation current and the channel temperature. According to the method, parameter extraction errors caused by inconsistency of the environment temperature and the channel temperature in a traditional method are solved, the intrinsic ballistic transport efficiency parameters of the device can be accurately obtained, and the method is suitable for high-performance planar transistors with silicon, germanium and III-V group compounds as carrier channels, fin type three-dimensional grids and transistors with ring gate-nanowire structures.

The purpose of the present disclosure is to provide a technique capable of suppressing a decrease in saturation current while reducing the amount of gate charge. This semiconductor device is provided with: a semiconductor substrate provided with a drift layer, a carrier storage layer, and a base layer; and a two-stage active trench structure provided on the semiconductor substrate. The thickness of the lower-level insulating film in contact with the side portion of the lower-level electrode is thicker than the thickness of the upper-level insulating film in contact with the side portion of the upper-level electrode, and at least one of conditions (a), (b) and (c) is satisfied. The lower end of the upper electrode is positioned above a position at which the integrated value of the impurity concentration of the carrier storage layer in the vertical direction is half.

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

Semiconductor device (100), in particular a vertical transistor device, preferably based on gallium nitride, wherein the semiconductor device for current conduction is based on a 2-dimensional electron gas (2DEG).

The application discloses a method for P-type doping of an organic field effect transistor semiconductor layer and an organic field effect transistor prepared by the method. 2,3,5,6-tetrafluoro-7,7',8,8'-tetracyanoquinodimethane (F4-TCNQ) is dissolved in an orthogonal solvent of the organic semiconductor layer as a P-type dopant, and the P-type dopant is spin-coated on an organic semiconductor layer film which has been spin-coated in an air atmosphere, and the doping is activated by rapid thermal annealing, so that the problems caused by hopping transmission and Coulomb traps in charge transport are improved, the threshold voltage is reduced, and the on-off ratio is improved. For a P-type field effect transistor, the P-type doping enhances hole transport, effectively improves the saturation current, and suppresses electron transport, so that the power consumption is reduced when the transistor is turned off. The doping method is based on a solution method and is simple in process and low in preparation cost, can be applied to large-scale production, and has a good application prospect in flexible and portable electronic devices.

According to the trench gate silicon carbide MOSFET device and the preparation method thereof, a source electrode step trench and a P-type shielding layer are introduced to form a follow current nMOS together with a CSL region, a P-type base region and an N-type ohmic contact region, and form a self-bias pMOS together with the CSL region, the P-type base region and a P-type ohmic contact region. During reverse conduction, the source trench freewheeling nMOS is conducted, bipolar conduction of the body diode is inhibited, and the long-term working reliability of the device is improved; in a short-circuit state, the pMOS is started, the P-type shielding layer is grounded, the depletion region is rapidly expanded, pinch-off is formed with the depletion region of the P-type shielding region at the bottom of the trench gate, a current path is limited, saturation current is reduced, and the short-circuit capability of the device is improved; and in a blocking state, the pMOS is opened, and the P-type shielding layer is grounded, so that the electric field intensity of the oxide layer is effectively reduced. According to the invention, the forward conduction capability and low switching loss of the device are ensured, the short circuit and third quadrant capability of the device is improved, and the transient robustness of the device is obviously improved.

The present application discloses a multiphase full-bridge drive system for motor driving, comprising: a multiphase full-bridge circuit comprising at least three identical half-bridge circuits, each half-bridge circuit comprising a first and a second transistor, and the first transistor having a higher short-circuit withstand capability than the second transistor and the short-circuit saturation current of the first transistor being lower than the short-circuit saturation current of the second transistor, each half-bridge circuit further comprising a first and a second transistor drive circuit, each connected to a control terminal of the first transistor and a control terminal of the second transistor in order to control the first and the second transistor;a controller that is connected to the first and second transistor drive circuits of each half-bridge circuit to control the multi-phase full-bridge circuit for generating a multi-phase target drive voltage and thus for motor driving.

An object is to provide a technology that can suppress a decrease in the saturated current while reducing the amount of gate charge. A semiconductor device includes a semiconductor substrate with a drift layer, a carrier storage layer, and a base layer, and a two-stage active trench structure in the semiconductor substrate. A thickness of a lower-stage insulating film in contact with a side portion of a lower stage electrode is greater than a thickness of an upper-stage insulating film in contact with a side portion of an upper stage electrode, at least one of conditions (a), (b), or (c) is satisfied, and a lower end of the upper stage electrode is located above a position at which an integrated value of impurity concentrations of the carrier storage layer in a vertical direction is halved.

The invention provides a large-current inductor. The large-current inductor comprises a shell, a middle column and a coil. The at least two coils are sequentially wound on the middle column and are used for generating an inductive effect through accessed current; a wiring end of the coil penetrates through the shell to form a pin, and the pin is used for being connected with a circuit board; the shell is provided with a containing cavity, and the containing cavity is used for containing the middle column and the coil; the ui value of the shell is 900 to 3500, and the Bm value of the shell is 0.4 T to 0.6 T. By means of the stable saturation current curve characteristic of the ferrite magnetic core material, the large-current inductor can maintain stable current linearity, and the current stability of the inductor is improved. In addition, the ferrite magnetic core has higher surface impedance and small high-frequency eddy current loss and magnetic hysteresis loss, so that the characteristic of low loss can be maintained at higher switching frequency, and the high-frequency application requirement is met.

The application discloses a granulated powder with high saturation performance for inductance and a preparation method, and relates to the technical field of electronic components. The composite powder is composed of 40-60 parts of FeSiCr coarse powder, 25-35 parts of FeSi / amorphous fine powder and 5-15 parts of carbonyl iron powder in terms of mass fraction. The particle size of the FeSiCr coarse powder is 45-75 microns, the particle size of the FeSi / amorphous fine powder is 5-15 microns, and the particle size of the carbonyl iron powder is 1-3 microns. The ternary multi-particle size grading of the FeSiCr coarse powder, the FeSi / amorphous fine powder and the carbonyl iron powder is combined with the inert atmosphere protection mixing process, so that the powder oxidation is effectively inhibited, the effective performance retention rate of the magnetic powder is greater than or equal to 96%, the industrial problem that a single soft magnetic powder cannot simultaneously consider high saturation current and low high-frequency loss is solved from the powder material formula level, the saturation current of the magnetic core is increased by more than 15% than that of a single commercially available FeSiCr powder, the high-frequency loss is reduced by more than 20%, and the fluctuation deviation of the wide-frequency permeability is less than or equal to 5%.

This invention provides a high-reliability trench-gate silicon carbide MOSFET device, comprising: an N+ type substrate, an N- type drift region, a first P region, a P+ contact region, an N+ contact region, an N-type equivalent resistance region located between the first P region and the N+ contact region, a gate dielectric layer, a trench gate, an isolation dielectric layer, a source electrode, and a drain electrode. The SiC MOSFET device proposed in this invention adds an N-type equivalent resistance region, which acts as a series resistor. When a short circuit occurs, this reduces the saturation current of the device and improves its short-circuit capability.

The application discloses an AI-based diode model parameter automatic extraction and optimization method, and belongs to the technical field of electronic design.The application solves the problem that the existing diode model parameter extraction method is seriously dependent on manual experience, the process is complicated and time-consuming, and it is difficult to stably obtain high-precision and strong generalization capability model parameters from nonlinear data under the influence of temperature and process deviation.The application constructs an intelligent mapping model from macro electrical characteristics to microscopic model parameters by adaptively denoising and multidimensional feature engineering on measured data, and finally generates a high-fidelity diode electronic design model by combining global optimization of physical constraints, so as to realize high-precision, high-efficiency and full-automatic extraction and optimization of key model parameters such as diode saturation current, ideal factor and series resistance, thereby improving the efficiency, automation level and cross-condition robustness of model extraction.

Light-emitting device configured to emit radiation, comprising: a substrate (50); an epitaxic structure (20) comprising in succession a first DBR stack (21), a light-emitting stack (22), a second DBR stack (23) and several discrete first and second contact regions (241), wherein the light-emitting device emits coherent light having a far-field angle of less than 15 degrees, at a forward current between a laser threshold current and a saturation current therein, and incoherent light at a forward current less than the laser threshold current, wherein the epitaxial structure (20) is arranged on the substrate (50) and further comprises: several first radiation-emitting areas in a first column; and several second radiation-emitting areas in a second column; a conductive layer (60) on the epitaxial structure (20); wherein the contact areas (241) are arranged in a two-dimensional field and are configured to direct a spatially limited current in the light-emitting device to the several first radiation-emitting areas and the several second radiation-emitting areas; and wherein one of the several first contact areas includes a first latitude (w3') and one of the several second contact areas includes a second latitude (w3) that differs from the first latitude (w3').

This invention provides a modeling circuit, method, and model for a MOSFET containing a parasitic BJT. The modeling method includes: obtaining the saturation current, maximum DC current gain, and base-emitter junction non-ideal saturation current of the BJT under different active region areas in the SPICE model of the MOSFET; fitting the saturation current, maximum DC current gain, and base-emitter junction non-ideal saturation current of the BJT to the active region area to obtain the relationship between the saturation current, maximum DC current gain, and base-emitter junction non-ideal saturation current of the BJT under different active region areas; adding the relationship to the SPICE model of the MOSFET to obtain the MOSFET model containing the parasitic BJT. This invention reflects the parasitic BJT characteristics of the MOSFET during simulation.

A reference current generator includes two transistors, a resistor and a mirroring circuit. The first transistor includes a source receiving a supply voltage, a drain connected with a first node, and a gate connected with a second node. The second transistor includes a source receiving the supply voltage, and a drain and a gate connected with a third node. The resistor is connected between the second node and the third node. The mirroring circuit includes an input terminal receiving an input current, a first mirrored terminal connected with the second node and a second mirrored terminal connected with the first node. The first mirrored terminal and the second mirrored terminal generate a first mirroring current and a second mirroring current respectively. The first transistor generates a saturation current. A reference current is equal to the saturation current minus the second mirroring current.

A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.

The invention provides a method for testing the saturation current of an IO port, and the method comprises the steps: a, measuring a first average current flowing through a source input end corresponding to an MOS tube when the MOS tube in the IO port is in a cut-off state; b, an MOS tube in the IO port is controlled to be switched between a conduction stage and a cut-off stage, and the MOS tube is always in a saturated state in the conduction stage; c, measuring a second average current flowing through the source input end corresponding to the MOS tube in the process of the step b; and d, obtaining the IO port saturation current according to the difference value of the first average current and the second average current and the proportion of the conduction time T1 and the cut-off time T2 of the MOS tube.

The invention belongs to the technical field of power devices, and provides a silicon carbide trench gate power device with a floating P-type ring and a preparation method thereof, and a chip, a P-type shielding region is formed at the bottom of a groove of an N-type drift region, and a gate dielectric layer is formed on the inner wall of the groove on the P-type shielding region. A plurality of P-type floating ring regions with the same width are arranged in regions on two sides of an N-type drift region, and the plurality of P-type floating ring regions on the same side are sequentially arranged towards a silicon carbide substrate along a P-type shielding region, so that a floating PN junction is formed, an electric field extends downwards towards two sides, the distribution range of a high electric field in the drift region can be expanded, the area of a space charge region is increased, and the performance of the device is improved. The saturation current of the device is effectively reduced, the endurance capability of the device under a short-circuit test is improved, and the reliability of the device is improved.

To provide a 4H SiC electronic device having improved short-circuit characteristics, and to provide a method of manufacturing the same.SOLUTION: An electronic device (100) includes a semiconductor body (102) of silicon carbide, a body region (105) in a first surface of the semiconductor body, a source region (108) in the body region (105), a drain region (104) in a second surface of the semiconductor body (102), and a doped region (120) including one or more first sub-regions (121) extending seamlessly across a first surface (102a) of the semiconductor body (102) and having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration. Thus, the electronic device has a plurality of zones having different conduction threshold voltages and different saturation currents and alternating with each other.SELECTED DRAWING: Figure 2

This application relates to the field of semiconductor manufacturing technology, specifically to a device and method for determining outliers in the current ratio of a MOS transistor, comprising: standardizing the acquired linear current value and saturation current value; calculating the apparent current ratio, which is the ratio of the standardized linear current value to the standardized saturation current value; calculating the median of the current ratio; calculating the absolute deviation of the median based on the current ratio and the median; calculating the upper limit management limit value and the lower limit management limit value based on the median of the current ratio and the absolute deviation of the median; and determining the current ratio as an outlier if it is greater than the upper limit management limit value or less than the lower limit management limit value, thereby improving the reliability of the measurement data.

The invention discloses a back contact battery preparation method and a back contact battery, and belongs to the field of batteries. A layer of intrinsic amorphous silicon is introduced into a substrate to serve as a buffer layer, then an intermediate layer and a second layer of intrinsic amorphous silicon are deposited in sequence to form a sandwich structure, lattice structures of the intrinsic amorphous silicon layers are repaired through high-temperature annealing to obtain an intrinsic polycrystalline silicon layer, a double-layer passivation structure is formed, and then atom doping and patterning are performed to obtain the intrinsic polycrystalline silicon layer and the double-layer passivation structure. The P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer can share the same buffer layer and the same intermediate layer, the double-layer passivation structure can effectively slow down doping diffusion, improve the doping concentration regulation interval and reduce the composite saturation current density, and the passivation effect is improved on the whole.

The application relates to the technical field of network-constructing inverters and is a kind of fault ride-through system and method based on a double-synchronous unified virtual oscillation controller, which comprises a double-sequence current reference generator for obtaining power reference values when a fault is detected, and combining the power reference values to determine positive and negative sequence current reference values; a double-sequence vector limiter connected with the double-sequence current reference generator, which realizes overcurrent limitation under symmetrical and asymmetrical faults and outputs limited positive and negative sequence saturation current reference values; a positive sequence space vector oscillator and a negative sequence space vector oscillator, both of which are connected with the double-sequence vector limiter and realize double-sequence synchronous operation. The application can inhibit overcurrent under symmetrical or asymmetrical fault conditions, and combines enhanced synchronization capability with fast overcurrent limitation to provide voltage support and unbalanced relief fault ride-through without switching to a backup controller or a current source type control.

The application belongs to the technical field of power semiconductor, and relates to a silicon carbide MOSFET structure, which comprises a metallized drain, a high-doped first-conductivity-type semiconductor substrate, a first-conductivity-type semiconductor epitaxial layer, a second-conductivity-type semiconductor well, a high-doped second-conductivity-type semiconductor ohmic contact region, a high-doped first-conductivity-type semiconductor source contact region, a high-doped first-conductivity-type semiconductor current guide layer, a first-conductivity-type semiconductor JFET region, a metallized source, a gate oxide layer, a Schottky metal region, a polysilicon gate electrode, an oxide layer and an N+ polysilicon short circuit layer. The application adopts a split gate structure, integrates a Schottky contact in the middle of the gate, and sets a current guide layer in the JFET region. With the increase of the drain voltage, the Schottky contact makes the JFET region quickly deplete and clamp off in advance, thereby reducing the saturation current of the device. The current guide layer provides a current path, which can improve the short circuit current resistance of the device and reduce the on-resistance of the device.

A NAND flash memory, a memory and an electronic device. The NAND flash memory reads data of multiple pages at the same time on the same surface, and makes the saturation current of each page different and / or the time of reading data of each page different, so that the data recorded by each page is different, the total current of the reading circuit is different, and the speed of voltage drop of the discharge capacitor C SO is different. When the NAND flash memory reads data of multiple pages, the relationship between the voltage of the discharge capacitor C SO and the comparison voltage is detected by using a voltage comparison unit, so that the data recorded by each page is accurately read, and confusion between the read data and the pages is avoided.

The application belongs to the technical field of photoelectric functional film manufacturing, and particularly relates to a hierarchical pore host framework gas phase permeation-in-situ formation assembly method and an online acceptance method. The assembly method takes a two-dimensional covalent organic framework film with a first pore structure and a second pore structure as a host framework; a guest precursor is introduced by pulse gas phase permeation for in-situ crystallization in a low-temperature confined space; then, an interface passivation molecule is introduced by gas phase permeation to form a discontinuous passivation layer, and flash solidification is used to induce grain boundary fusion and form a continuous guest phase; subsequently, an upper contact structure for electrical measurement is formed, a bias-dependent external quantum efficiency and a dark state current-voltage curve are obtained, an effective carrier collection characteristic length and a reverse saturation current density are fitted, and process acceptance and correction instructions are generated accordingly. The application is suitable for closed-loop intelligent manufacturing of complex and hybrid films, and greatly improves the yield of mass production.

The application discloses a kind of transient stability analysis method and related device considering current limit, establish the mathematical model of hydropower system and photovoltaic power generation system;In view of the current-limiting control of photovoltaic inverter and flexible rectifier during fault, the equation of active power sent by hydro-generator before fault removal is derived according to Thevenin theorem;The analytical expression of critical removal angle of sending-out system is derived by using equal-area rule;With critical removal angle as the key index of transient stability limit of sending-out system, the influence of photovoltaic and flexible current transformer saturation current angle parameter value and water-light generation ratio on the transient stability of sending-out system is evaluated.The water-light generation ratio setting method involved in the application can effectively improve the transient stability of the system, and the research results are expected to provide certain theoretical guidance for the stable operation of future new energy power system.

A silicon carbide power device cell with double gate trenches is characterized in that a first gate channel region of a silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed along at least one side wall of a first type of gate trench and is connected with a first source region, and a second gate channel region of a silicon carbide super barrier rectifier (serving as an MOS (Metal Oxide Semiconductor) channel diode) is formed along the side wall of a second type of gate trench and is connected with a second source region; therefore, the loss of the turn-off switch is reduced. The first P shielding region surrounds the bottom region of the second-type gate trench and is connected to the source electrode metal through the side wall P-type region; and the second P shielding region is adjacent to the lower surface of the first body region, and forms a saturation current pinch-off region with the adjacent second P shielding region for improving the short-circuit capability and reducing the electric field of the gate oxide layer.

This method for producing a diamond thin film involves synthesizing a diamond thin film on a base material through a plasma CVD method, wherein a raw material gas containing C, H, and O is supplied to a vacuum vessel in which the base material is disposed, high-frequency current is applied to an antenna that is disposed inside or outside the vacuum vessel and that has a conductor element and a capacitive element which are electrically connected to each other in series to generate inductively coupled plasma inside the vacuum vessel, and the generated inductively coupled plasma is used for the plasma CVD method. When the diamond thin film is being synthesized, the plasma has the following characteristics: the electron temperature is 1.0 eV or more and 2.0 eV or less; the electron density is 1.0 × 1011cm-3 or more and 1.0 × 1012cm-3 or less; and the ion saturation current is 1.0 × 10-4 A or more and 1.0 × 10-2 A or less.