19results about How to "Lower threshold voltage" patented technology

The invention discloses an echo wall mode microcavity laser and a preparation method thereof, and the laser sequentially comprises a GaN substrate, a field oxygen isolation layer, a hole transport layer, an insulating layer and a transparent conductive layer from bottom to top, and the upper surface of the GaN substrate is provided with an echo wall mode microcavity. The upper surface of the transparent conductive layer and the upper surface of the GaN substrate are respectively provided with a first electrode and a second electrode. The MIS structure of the first electrode and the transparent conducting layer-insulating layer-GaN substrate is adopted, the preparation process and the structure are simple, the hole transport layer can improve the minority carrier hole injection amount when the device works, and therefore the turn-on voltage of the device is remarkably reduced; and the laser device can also realize a lasing function.

The invention provides a junction field effect transistor device and a method of manufacturing the same. The device includes a substrate having a first conductivity type; a well buried in the substrate and having a second conductivity type, the second conductivity type being different from the first conductivity type; a first top layer embedded in the well and having a first conductivity type; a plurality of sources or drains disposed on the top surface of the well; the first isolation structure is adjacent to the source electrode or the drain electrode; the grid electrode is arranged on the top surface of the first top layer; and a plurality of first wells disposed under the gate, wherein the second conductivity type dopant concentration of the first wells is lower than the second conductivity type dopant concentration of the wells.

The invention discloses high-dielectric-constant polyurethane with a side chain containing zwitter-ion pairs as well as preparation and application of the high-dielectric-constant polyurethane, and belongs to the technical field of photoelectric materials. Zwitterionic pairs are introduced into a polyurethane chain segment through a chain extension means, positive and negative ions are ammonium positive ions / phosphate anions and / or phosphonium positive ions / sulfonate anions respectively, and the zwitterionic pairs are located on side chains. By introducing zwitterionic pairs, the dielectric constant of polyurethane can be remarkably improved, and by increasing the dielectric constant, the capacitance of the dielectric layer is increased under the conditions that the thickness of the dielectric layer is not reduced and the film performance of the dielectric layer is prevented from being damaged due to the fact that pinholes penetrate through the dielectric layer. The zwitter-ion pair is introduced to the side chain of the polyurethane, so that the dielectric property of the polyurethane is improved, and the dielectric constant is prevented from being reduced under a high-frequency alternating electric field; and when the polyurethane dielectric medium is applied to the organic field effect transistor as an insulating layer, the threshold voltage can be obviously reduced, and the original charge transfer performance can be maintained at the same time.

This application provides a pixel circuit, a display panel, and a display device. The pixel circuit includes: a driving module; a bias compensation module, wherein the control terminal of the bias compensation module is electrically connected to a first control signal line, the first terminal of the bias compensation module is electrically connected to a target signal line, and the second terminal of the bias compensation module is electrically connected to either the first terminal or the second terminal of the driving module; the target signal line is electrically connected to a first periodic signal. This application can adjust the bias state of the threshold voltage of the driving module and can flexibly meet the adjustment requirements of the threshold voltage of the driving module under different conditions.

The invention discloses a memory element and a memory. The memory element comprises a first electrode layer and a second electrode layer which are stacked along a first direction, the storage layer is located between the first electrode layer and the second electrode layer, the storage layer has a bidirectional threshold switching characteristic, and the material of the storage layer comprises first ions with negative charges and second ions with positive charges; wherein the storage layer comprises a first storage layer, a second storage layer and a third storage layer which are sequentially arranged in a stacked mode in the first direction, and the concentration of the first ions in the first storage layer is larger than the concentration of the first ions in the second storage layer. A concentration of the second ions in the third storage layer is greater than a concentration in the second storage layer. According to the invention, the threshold voltage of the Set state is reduced, and the read window of the SOM device is improved.

The invention discloses a writing method of a ferroelectric field effect transistor array, and belongs to the technical field of micro-nano electronics. According to the method, a self-compensation write-in method is provided for a multi-stage storage ferroelectric field effect transistor array of a 1T structure, a pulse sequence of a self-compensation waveform is adopted for write-in and corresponds to different storage states in multi-stage storage, positive pulse write-in is adopted when the pulse sequence is higher than an intermediate storage state, and negative pulse write-in is adopted when the pulse sequence is lower than the intermediate storage state. The method comprises the following steps of: writing a FeFET memory cell, performing read verification on a written state of the FeFET memory cell, starting an error correction program for correction when a write error is found so as to reach a target state, and starting a durability recovery program to recover the performance of the FeFET memory device if the error correction program fails; the method simultaneously solves the reliability problems of large fluctuation between devices and between cycles, limited durability and serious write-in crosstalk, has the advantages of simple process, low hardware overhead and the like, is compatible with the current advanced node CMOS technology, and is easy to implement.

This invention proposes a low-cost, high-efficiency co-sputtering technique for magnesium-hydrogen co-doped indium zinc oxide (IZO) thin-film transistors and their fabrication methods. The device is fabricated using heavily doped N-type silicon and silicon dioxide as the gate and insulating layer, respectively. A magnesium-doped IZO semiconductor channel layer is deposited using a dual-target co-sputtering method followed by hydrogen plasma treatment. Aluminum is then deposited as the electrode using DC sputtering. All deposition processes are patterned using a mask, ultimately resulting in a high-performance magnesium-hydrogen co-doped IZO thin-film transistor. This invention improves IZO defects and controls oxygen vacancy concentration by doping magnesium with an appropriate atomic concentration using dual-target co-sputtering. Hydrogen plasma treatment is used to modulate the interface defect states and carrier transport characteristics. This fabrication process not only offers advantages such as high efficiency and low cost, but also produces devices with high carrier mobility and good stability, providing a technical reference for optimizing low-cost and high-efficiency new co-doping processes.

The diode is composed of a dual-gate PSJ-GaN FET. The FET has a GaN layer 11, an Al x Ga 1‑x N layer 12, undoped GaN layer 13 and p-type GaN layer 14. x Ga 1‑x A source electrode 19 and a drain electrode 20 are provided on the N layer 12, a first gate electrode 15 is provided on the p-type GaN layer 14, and a second gate electrode 18 is provided on the gate insulating film 17 provided inside the groove 16 provided at the Al2O3 layer between the source electrode 19 and the undoped GaN layer 13. x Ga 1‑x In the N layer 12 , the source electrode 19 , the first gate electrode 15 , and the second gate electrode 18 are connected to each other, or the source electrode 19 and the second gate electrode 18 are connected to each other and a positive voltage relative to the source electrode 19 and the second gate electrode 18 is applied to the first gate electrode 15 .

The application discloses a network-constructing energy storage coordinated control method for supporting grid voltage stability, and steps are as follows: real-time acquisition of state information and network-constructing energy storage output current; when the network-constructing energy storage output current does not reach an overcurrent limiting threshold, the network-constructing energy storage is controlled to adopt a constant voltage amplitude operation mode, the voltage amplitude of a node connected with the network-constructing energy storage is maintained to be equal to a reference value, so that a P-V characteristic curve of a load side is reshaped, the maximum transferable power of the load side is improved, and a static voltage stability margin is increased; when overcurrent occurs in the network-constructing energy storage, the network-constructing energy storage is switched to an overcurrent operation mode, in which mode, the network-constructing energy storage output active power and reactive power are distributed according to the ratio of line resistance to reactance between a grid node and a node connected with the network-constructing energy storage; and when the network-constructing energy storage output current falls below a preset recovery threshold, the constant voltage amplitude operation mode is restored. The application can improve the static voltage stability limit of a load node and the continuous voltage support capability of energy storage to the load under an overcurrent condition.

The present invention relates to a polymerizable liquid crystal composition and a display device thereof, and belongs to the field of liquid crystal materials. The polymerizable liquid crystal composition comprises at least one compound having a structure shown in general formula I: at least one compound shown in general formula P: at least one compound shown in general formula II: at least one compound shown in general formula III: and at least one compound shown in general formula M, wherein compound M is selected from compounds represented by general formula M-I and / or M-II: The liquid crystal composition of the present invention has very low rotational viscosity, good phase performance and good low-temperature performance, and can form a lower pretilt angle after UV irradiation, has less RM residue, lower threshold voltage and faster response time, and the formed pretilt angle has long-term stability under high and low temperature conditions, and can meet the requirements of liquid crystal display devices for low power consumption and good display effect.

The present invention provides a non-volatile ferroelectric semiconductor memory and a preparation method thereof, wherein the memory comprises a substrate, a control gate and a storage gate sequentially arranged above the substrate; wherein a source and a drain are arranged on the substrate, and a substrate region between the source and the drain forms a channel isolating the source and the drain; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the control gate is used to control the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate, the source, the control gate and the drain. The above invention can improve storage density, reduce power consumption and enhance reliability.

The invention discloses a phase change memory and an operation method, the phase change memory comprises a word line, a bit line and a memory module, the memory module is connected with the word line and the bit line to which a reverse voltage difference is applied in a setting operation, the threshold voltage of the memory module can be reduced, and the performance of the memory module is improved. Therefore, under the condition that the threshold voltage of the memory module after the reset operation is kept unchanged, the difference between the threshold voltage of the memory module after the reset operation and the threshold voltage of the memory module after the setting operation is increased, and the read window margin is further improved.

The invention provides a liquid crystal composition and a liquid crystal display device. The liquid crystal composition comprises at least one compound as shown in a general formula I, at least one compound as shown in a general formula II and at least one compound as shown in a general formula III. According to the liquid crystal composition disclosed by the invention, through mutual compounding of specific structures and contents of the compounds, the liquid crystal composition has proper vertical dielectric, proper dielectric anisotropy, relatively large optical anisotropy, relatively small rotary viscosity, shorter gray scale response time, relatively good low-temperature storage stability and relatively good Flicker value; the liquid crystal compound also has wider phase width to meet the display requirement at lower temperature, so that a liquid crystal display device comprising the liquid crystal compound has lower threshold voltage, higher response speed, higher contrast ratio and wider temperature use range. # imgabs0 #

The invention discloses a memristor manufacturing method for generating oxygen vacancies by X-ray irradiation. The memristor manufacturing method comprises the following steps: taking a resistive layer; respectively depositing a top surface insulating layer and a bottom surface insulating layer on the top surface and the bottom surface of the resistive layer; etching the top surface insulating layer to form a top surface square hole array, etching the bottom surface insulating layer to form a bottom surface square hole array, respectively forming top electrodes in top surface square holes, and respectively forming bottom electrodes in bottom surface square holes; x-rays are adopted to irradiate the resistive layer, and the needed oxygen vacancy concentration gradient is generated in the preset area of the resistive layer. According to the method, the oxygen vacancy concentration distribution is effectively controlled through X-ray irradiation, and compared with a traditional gas ion implantation method, the method has the advantages of being simple in process, precise in vacancy generation control and low in energy consumption, and is particularly suitable for being applied to a high-radiation environment and a nonvolatile memory requiring high performance.

The invention relates to a data management method of a solid state disk, which relates to the field of data storage management, and comprises the following steps: in response to a data storage request of a user side, obtaining a serial number of a solid state disk requested to be stored and to-be-stored data; extracting the state of the storage unit to obtain an idle digit constraint interval list of the storage unit; obtaining a to-be-stored bit number and an idle bit number constraint interval list distributed in a storage unit, and obtaining a plurality of data storage schemes; performing threshold voltage balance optimization analysis to obtain a target data storage scheme; and performing data management on the to-be-stored data according to the target data storage scheme. The technical problems that the number of threshold voltages of a storage unit is too large and the read-write efficiency is low due to the fact that the influence of the number of the threshold voltages on the read-write efficiency is not considered in an existing solid state disk storage technology are solved, the number of the threshold voltages is balanced by optimizing a data storage scheme, and the read-write efficiency is improved. The technical effects of reducing the threshold voltage quantity of the storage unit and improving the read-write efficiency of the solid state disk are achieved.

The present invention provides a liquid crystal composition containing a dibenzo derivative and a liquid crystal display device thereof. The liquid crystal composition of the present invention has a higher clearing point, a higher optical anisotropy, a higher absolute value of dielectric anisotropy, a larger average elastic constant, a lower threshold voltage, a shorter response time, a higher contrast, a longer low-temperature storage time and a higher voltage holding rate (VHR (initial) and VHR (UV)), so that the liquid crystal display device containing the liquid crystal composition has a wider temperature use range, a higher contrast, lower power consumption, a lower threshold voltage, a faster response speed, better low-temperature stability and higher reliability, thereby having a wider range of applications.

The present invention discloses an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and a preparation method thereof. The thin film transistor device comprises: a substrate layer, a bottom gate electrode layer, a top gate electrode layer, a bottom gate insulating layer, a top gate insulating layer, an InAlSnO active layer, an InGaZnO active layer, a source electrode layer, a drain electrode layer and a passivation layer. The present invention effectively suppresses the carrier capture effect and enhances the electrical reliability of the TFT device by forming a composite channel structure with a larger InAlSnO / InGaZnO heterojunction energy band step.

The present invention provides a thin film transistor, a manufacturing method thereof and a display panel. The manufacturing method of the thin film transistor includes: a substrate; a gate layer and a gate insulating layer sequentially located on the substrate; a hydrogen-containing layer located on the gate insulating layer; a semiconductor layer located on the hydrogen-containing layer, the semiconductor layer including a source doping region and a drain doping region, the source doping region and the drain doping region are respectively arranged at two ends of the semiconductor layer at intervals; a source electrode layer and a drain electrode layer are respectively located on the source doping region and the drain doping region. By forming a hydrogen-containing layer between the gate insulating layer and the semiconductor layer, the atomic structure in the gate insulating layer is optimized, the structural defects are reduced, the threshold voltage is reduced, and the on-state current is increased, so as to improve the device performance, thereby improving the yield and reliability of the panel.

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a semiconductor material layer; forming a first mask layer, wherein the first mask layer forms a first opening exposing the first region of the semiconductor material layer and at least shields the second region of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region of the first conductive type; forming a second mask layer which forms a second opening exposing the second area and at least shields the first area; performing a second ion implantation process on the second region based on the second mask layer to form a first well region of the first conductive type; the second injection concentration of the second ion injection process is greater than the first injection concentration of the first ion injection process; forming a second drift region of a second conductive type; a first source region and a first drain region are respectively formed in the first well region and the second drift region. Therefore, the influence on the threshold voltage is reduced while the hot carrier effect is improved.