5results about How to "Lower threshold voltage" patented technology

This application provides a pixel circuit, a display panel, and a display device. The pixel circuit includes: a driving module; a bias compensation module, wherein the control terminal of the bias compensation module is electrically connected to a first control signal line, the first terminal of the bias compensation module is electrically connected to a target signal line, and the second terminal of the bias compensation module is electrically connected to either the first terminal or the second terminal of the driving module; the target signal line is electrically connected to a first periodic signal. This application can adjust the bias state of the threshold voltage of the driving module and can flexibly meet the adjustment requirements of the threshold voltage of the driving module under different conditions.

The invention discloses a memory element and a memory. The memory element comprises a first electrode layer and a second electrode layer which are stacked along a first direction, the storage layer is located between the first electrode layer and the second electrode layer, the storage layer has a bidirectional threshold switching characteristic, and the material of the storage layer comprises first ions with negative charges and second ions with positive charges; wherein the storage layer comprises a first storage layer, a second storage layer and a third storage layer which are sequentially arranged in a stacked mode in the first direction, and the concentration of the first ions in the first storage layer is larger than the concentration of the first ions in the second storage layer. A concentration of the second ions in the third storage layer is greater than a concentration in the second storage layer. According to the invention, the threshold voltage of the Set state is reduced, and the read window of the SOM device is improved.

This invention proposes a low-cost, high-efficiency co-sputtering technique for magnesium-hydrogen co-doped indium zinc oxide (IZO) thin-film transistors and their fabrication methods. The device is fabricated using heavily doped N-type silicon and silicon dioxide as the gate and insulating layer, respectively. A magnesium-doped IZO semiconductor channel layer is deposited using a dual-target co-sputtering method followed by hydrogen plasma treatment. Aluminum is then deposited as the electrode using DC sputtering. All deposition processes are patterned using a mask, ultimately resulting in a high-performance magnesium-hydrogen co-doped IZO thin-film transistor. This invention improves IZO defects and controls oxygen vacancy concentration by doping magnesium with an appropriate atomic concentration using dual-target co-sputtering. Hydrogen plasma treatment is used to modulate the interface defect states and carrier transport characteristics. This fabrication process not only offers advantages such as high efficiency and low cost, but also produces devices with high carrier mobility and good stability, providing a technical reference for optimizing low-cost and high-efficiency new co-doping processes.

The application discloses a network-constructing energy storage coordinated control method for supporting grid voltage stability, and steps are as follows: real-time acquisition of state information and network-constructing energy storage output current; when the network-constructing energy storage output current does not reach an overcurrent limiting threshold, the network-constructing energy storage is controlled to adopt a constant voltage amplitude operation mode, the voltage amplitude of a node connected with the network-constructing energy storage is maintained to be equal to a reference value, so that a P-V characteristic curve of a load side is reshaped, the maximum transferable power of the load side is improved, and a static voltage stability margin is increased; when overcurrent occurs in the network-constructing energy storage, the network-constructing energy storage is switched to an overcurrent operation mode, in which mode, the network-constructing energy storage output active power and reactive power are distributed according to the ratio of line resistance to reactance between a grid node and a node connected with the network-constructing energy storage; and when the network-constructing energy storage output current falls below a preset recovery threshold, the constant voltage amplitude operation mode is restored. The application can improve the static voltage stability limit of a load node and the continuous voltage support capability of energy storage to the load under an overcurrent condition.

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a semiconductor material layer; forming a first mask layer, wherein the first mask layer forms a first opening exposing the first region of the semiconductor material layer and at least shields the second region of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region of the first conductive type; forming a second mask layer which forms a second opening exposing the second area and at least shields the first area; performing a second ion implantation process on the second region based on the second mask layer to form a first well region of the first conductive type; the second injection concentration of the second ion injection process is greater than the first injection concentration of the first ion injection process; forming a second drift region of a second conductive type; a first source region and a first drain region are respectively formed in the first well region and the second drift region. Therefore, the influence on the threshold voltage is reduced while the hot carrier effect is improved.