51results about How to "Reduce Overlap Capacitance" patented technology

A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.

A display substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (TFT) and a pixel electrode. The gate line is extended in a first direction on the base substrate. The gate insulation layer is formed on the base substrate to cover the gate line. The data line is extended in a second direction and intersects the gate line at an intersecting portion. At the intersecting portion, the data line is separated from the gate line by an air gap. In another embodiment, the data line also includes at least one etching hole extending to the air gap. The TFT is electrically connected to the data and the gate lines. The pixel electrode is electrically connected to the TFT.

The invention provides a self-aligning metal oxide thin film transistor and a manufacturing method thereof. The method includes depositing a metal oxide semiconductor layer, a gate dielectric layer and a conducting thin film on a substrate and photoetching for imaging, spin-coating a dopant layer on the surface of a device, performing heat treatment to enable doping atoms in the spin-coated dopant layer to be diffused into a lower-layer material. The graphical gate electrode and the graphic gate dielectric exist, so that the doping atoms can only be diffused into metal oxide semiconductor areas on two sides of a channel area, doping of the metal oxide semiconductor on two sides of a channel is realized, resistivity of the metal oxide semiconductor is greatly lowered, and a self-aligned source-drain area is formed. The spin-coated dopant layer can also serve as a passivating layer of the device and is combined with subsequent processes like photoetching of contact holes and leading-out of electrodes and a wiring layer to manufacture a complete TFT (thin film transistor) device. The metal oxide thin film transistor prepared by the method has a self-aligning structure and is simple in process and compatible with large-area substrate process.

An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode.

Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed .on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region; a gate oxide layer on the silicon substrate; and a notched gate electrode on the substrate, the notched gate electrode including a notch along an outer side surface of a lower portion such that a top portion of the notched gate electrode is wider than the lower portion, the gate oxide layer extending between the interface of the notched gate electrode and the substrate, and a gate poly oxide layer provided along an outer side surface of the notched gate electrode and along an inner wall of the notch, a portion of the lightly doped region being under the notch.

This invention discloses one MOS field effect tube and its process method, which has side wall bottom concaved toward inside. The field effect tube method comprises the following steps: a, injecting well ions for annealing to sacrifice oxidation layer peeling off; b, growing or depositing one layer of thick oxidation layer; c, processing total etching in middle area oxidation; d, growing grating oxidation; e, depositing multiple transistor grating; f, processing light etch on thick oxidation area; g, regular steps after etching.

This invention discloses one MOS field effect tube and its process method, which has the following steps: a, injecting well ion and annealing and sacrifice oxidation layer for peeling off; b, growing or depositing one layer of grating oxidation layer; c, totally etching middle area grating oxidation; d, growing film grating oxidation; e, the current process method steps are applicable for this invention.

The invention discloses a manufacturing method of a semiconductor device. The method comprises the following steps of: removing a pseudo-gate stack in the process of preparing a complementary metal-oxide-semiconductor (CMOS) transistor by using a replacement gate or gate last process; forming an L-shaped sidewall and a second sidewall on the L-shaped sidewall in a first opening which is formed after the pseudo-gate stack is removed; redefining the size of a replacement gate to play a role in adjusting the overlapped capacitance of a replacement gate stack and a source/drain region and a source/drain extension region; and forming a replacement sidewall by a sidewall of a gate electrode in the replacement gate stack, so that the overlapped capacitance of the sidewall and the source/drain region and the source/drain extension region is further reduced, and the whole overlapped capacitance of the device is further reduced. Furthermore, a device with a smaller size is obtained by a processmethod which is easier to implement.

The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

The invention is a semiconductor component, comprising a substrate, a gate dielectric layer, a gate, a source/drain region, and a stress layer, where the gate dielectric layer is arranged on the substrate, the gate is arranged on the gate dielectric layer and the area of the top of the gate is more than that of the bottom; in addition, the source/drain region is arranged in the substrate on two sides of the gate, and the stress layer is arranged on the substrate and covers the gate and the source/drain region.

Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4×10¹⁸ cm⁻³±40%.

P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises an underlying substrate, and data lines and thin-film transistors which are arranged on the underlying substrate. The source electrode of each thin-film transistor comprises a first child source electrode and a second child source electrode. The first child source electrode and the second child source electrode are respectively connected with the data lines. The drain electrode of each thin-film transistor comprises a first child drain electrode which is arranged between the first child source electrode and the second child source electrode. Effective channel regions are respectively formed by the first child source electrode and the second child source electrode and the first child drain electrode respectively. The first child source electrode and the second child source electrode are mutually parallel and are respectively connected with the data lines, i.e. the first child source electrode and the second child source electrode are not intersected so that overlapping area of the source electrode and the gate electrode can be reduced, overlapping capacitance can be reduced and thus load can be reduced; besides, influence of capacitance on chargeability is far greater than influence of resistance so that linewidth can be properly reduced, aperture ratio can be enhanced and chargeability can be ensured by using the array substrate.