36results about How to "Suppress signal delay" patented technology

The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor chips to each other, and a plurality of chip-connection pads connected to the chip-to-chip interconnection; and a wiring board that has a plurality of lands of which pitch is larger than a pitch of the chip-connection pads, wherein a major surface of each of the plurality of semiconductor chips is connected to the chip-connection pads via a first connector so that the plurality of semiconductor chips are mounted on the semiconductor substrate, and an external-connection pad is formed on the major surface other than a region facing the semiconductor substrate, and is connected to the land on the wiring board via a second connector.

An object is to provide a solid-state imaging device or a semiconductor display device with which a high-quality image can be taken. By performing operation using a global shutter method, a potential for controlling charge accumulation operation can be shared by all pixels. In addition, a first photosensor group includes a plurality of photosensors connected to a wiring supplied with an output signal, and a second photosensor group includes a plurality of photosensors connected to another wiring supplied with the output signal. A wiring for supplying a potential or a signal for controlling charge accumulation operation to the first photosensor group is connected to a wiring for supplying the potential or signal to the second photosensor group.

An active matrix substrate or TFT substrate is provided with a lower layer wiring with a groove wiring structure covering surroundings of a copper layer with a barrier metal film is formed by forming a groove at an insulating substrate and depositing the barrier metal film and the copper layer in this groove. This groove wiring structure is used for a TFT substrate of a liquid crystal display (LCD) device. It is possible to manufacture an LCD device with large size, high density, a large aperture ratio and in which the disclination defects originating from a different in level of the lower layer wiring and an occurrence of disconnection failures in an upper layer wiring are suppressed.

A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4 F² at a minimum.

The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

According to an aspect of the present disclosure, a gate driver includes a plurality of stages which is dependently connected to each other and each of the plurality of pixels includes: a first output unit which outputs a sensing signal by voltages of a Q node and a QB node; a second output unit which outputs a reference signal by the voltages of the Q node and the QB node; a third output unit which outputs a scan signal by the voltages of the Q node and the QB node; a first controller which controls the Q node; and a second controller which controls the QB node, and at least two of the first to third output units share at least one clock signal among a plurality of clock signals, thereby reducing an area of the gate driver.

An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

The transistor array substrate of the present invention reduces the voltage drop of wiring. The transistor array substrate includes: a substrate; a plurality of driving transistors arranged in a matrix on the substrate, and a gate insulating film is sandwiched between the gate, the source, and the drain; a plurality of signal lines connected to the The gates of a plurality of drive transistors are laid out together and arranged to extend in a predetermined direction on the substrate; a plurality of supply lines are laid out together with the sources and drains of the drive transistors, and are arranged across the gates. The electrode insulating film is arranged crosswise with the plurality of signal lines, and conducts with one of the source and drain of the driving transistor; a plurality of power supply wirings are respectively stacked on the plurality of supply lines along the plurality of supply lines .

An electromagnetic transceiver apparatus for a NMR apparatus has an intermediate frequency generator for preparing an intermediate wave, a transmission frequency converter for preparing, on the basis of an intermediate frequency of the intermediate wave, an electromagnetic wave to be radiated from a transmitter coil, a reception frequency converter for processing a signal received by the NMR probe, an analog-digital converter for converting an output of the reception frequency converter into a digital signal, an IQ detector for performing detection on the basis of an output of the analog-digital converter, a phase locked loop and a switch inserted between the analog-digital converter and the reception frequency converter to select either an input from the intermediate frequency generator or an input from the reception frequency converter.

A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

A gate drive circuit (60) divided into a plurality of stages (ST) is provided. In each of the stages (ST), TFT elements (T1-T4) are provided, and branch lines (78) which connect clock lines (72, 74) and the TFT elements are provided. When attention is paid to one branch line (78A), divergent lines (79A, 79B) which electrically connect TFT elements (T2, T4) provided in a stage (ST(j)) different from a stage (ST(j-1)) in which TFT elements (T1, T3) connected to the branch line (78A) are provided and the branch line (78A) are provided to extend from the branch line (78A).

The present invention provides a printed wiring board, where insulation layers and conductive circuits are laminated alternately, the cross-section of each conductive circuit is rectangular, and when the upper conductive circuit space between adjacent conductive circuits of the PWB is referred to as (W1) and the lower conductive circuit space as (W2), the difference between those spaces with reference to the conductive circuit thickness (T) satisfies the formula 0.10T <=||W1 - W2| |<=0.73T. The above-described structure can suppress crosstalk and delayed signal transmission and prevent malfunctions of ICs even when high-speed driven ICs are mounted.

In a gateway apparatus for interconnecting different types of communication networks that are a line network and a packet network, a method and an apparatus for eliminating sound interruptions that would otherwise occur due to delay or loss of sound encoded data, minimizing the degradation of sound quality, and maintaining a short delay for telephone communication. A sound data processing circuit (550) of the gateway apparatus compares an expected value of the number of sound encoded data as expected outputs to be developed from a multiplexed-data separating circuit (200) in a unit period with the actual number of sound encoded data. If the actual number of sound encoded data is below the expected value, then the sound data processing circuit (550) generates encoded data for causing a destination terminal to execute an error encapsulation, and packetizes and transmits the generated encoded data together with the sound encoded data to the packet network from a transmission circuit (801). If acquiring no sound data from a reception circuit of the packet network in a given period, the sound data processing circuit (550) generates a signal indicative of no acquisition, selects either generation or disposal of the encoded data, and sends the signal to the line network from a data multiplexing circuit (900) and a line network terminating circuit (100).

A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor or a process technique for a standard power supply voltage of the IC or LSI. In order to increase an operating voltage of a field effect transistor, measures are taken in which a gate is divided into division gates, and electric potentials which are closer to a drain electric potential and which change according to increase or decrease in the drain electric potential are supplied to the division gates nearer a drain, respectively.

A touch panel includes a substrate including a touch area and a non-touch area adjacent to the touch area, a conductive polymer layer disposed on the substrate, and a touch sensor unit disposed between the conductive polymer layer and the touch area of the substrate. The conductive polymer layer includes a polymer wiring pattern disposed in the non-touch area of the substrate and includes a conductive polymer connected to the touch sensor unit.

A plasma CVD apparatus including a reaction chamber including an inlet for supplying a compound including a borazine skeleton, a feeding electrode, arranged within the reaction chamber, for supporting a substrate and being applied with a negative charge, and a plasma generating mechanism, arranged opposite to the feeding electrode via the substrate, for generating a plasma within the reaction chamber. A method forms a thin film wherein a thin film is formed by using a compound including a borazine skeleton as a raw material, and a semiconductor device includes a thin film formed by such a method as an insulating film. The apparatus and method enable to produce a thin film wherein low dielectric constant and high mechanical strength are stably maintained for a long time and insulating characteristics are secured.

A circuit for transmitting/receiving a logic signal through a capacitor is provided, which prevents signal delay and malfunction on the receiving circuit side. The power supply voltage of the buffer that transmits the logic signal in the transmitting circuit is enhanced to be larger than the power supply voltage of the buffer that inputs the logic signal in the receiving circuit. As a result, the amplitude of the logic signal at the input point is expanded from the clipping level according to the protection diodes, so that the signal delay, as well as the malfunction are prevented.