Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Printed wiring board

A technology of printed circuit boards and conductor circuits, which is applied in the manufacture of printed circuit components and multilayer circuits, and can solve problems such as IC malfunctions

Active Publication Date: 2007-11-28
IBIDEN CO LTD
View PDF4 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in the process of simultaneous development of high-speed driving of ICs and finer wiring of printed circuit boards on which such ICs are mounted, there may be cases where there are finer wiring patterns with minimum conductor width L / minimum spacing S=15 / 15 μm or less. IC malfunction due to crosstalk or signal delay in the printed circuit board

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Printed wiring board
  • Printed wiring board
  • Printed wiring board

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] (A) Preparation of kneaded product containing scaly particles

[0043] To a mixed solvent of 20 g of methyl ethyl ketone (hereinafter referred to as "MEK") and 80 g of xylene was added 15 g of scaly particles (manufactured by Hojun Co., Ltd., trade name "Esben C"), and the aspect ratio at the time of dispersion : ~500, crystal size: ~0.5μm), and kneaded with three rollers to make a kneaded product containing scaly particles.

[0044] (B) Preparation of solution containing epoxy resin

[0045] Add and mix 85 g of solid epoxy resin (manufactured by Japan EPOXY RESIN, trade name "Epicoat 1007") to a mixed solvent of 6.8 g of MEK and 27.2 g of xylene to make epoxy resin resin solution.

[0046] (C) Preparation of resin film for interlayer insulating layer

[0047] The kneaded product containing the scaly particles produced in the above (A), the solution containing the epoxy resin produced in the above (B), and dicyandiamide (bii·tei· Ai Japan (BTA JAPAN) Co., Ltd., trad...

Embodiment 2

[0162] Change the mask for pattern formation of the plating resist layer, and change the electrolytic copper plating conditions and the thickness of the conductive circuit after film thickness adjustment so that the L / S of the signal line is 7.5 μm / 7.5 μm, and the thickness T of the conductive circuit is 7.5 μm, except Other than that, a multilayer printed wiring board was produced in the same manner as in Example 1.

[0163] In this embodiment, the value of |W1-W2| is 0.675 μm to 2.775 μm, which basically satisfies the relationship of (0.10×thickness T of the conductive circuit) to (0.35×thickness T of the conductive circuit). Also, the standard deviation σ of |W1-W2| was 1.33 μm.

Embodiment 3

[0165] Change the mask for pattern formation of the plating resist layer, and change the electrolytic copper plating conditions and the thickness of the conductive circuit after film thickness adjustment so that the L / S of the signal line is 10.0 μm / 10.0 μm, and the thickness T of the conductive circuit is 10.0 μm, except Other than that, a multilayer printed wiring board was produced in the same manner as in Example 1.

[0166] In this embodiment, the value of |W1-W2| is 0.9 μm to 3.6 μm, which basically satisfies the relationship of (0.10×thickness T of the conductive circuit) to (0.35×thickness T of the conductive circuit). Also, the standard deviation σ of |W1-W2| was 1.27 μm.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Roughnessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The present invention provides a printed wiring board, where insulation layers and conductive circuits are laminated alternately, the cross-section of each conductive circuit is rectangular, and when the upper conductive circuit space between adjacent conductive circuits of the PWB is referred to as (W1) and the lower conductive circuit space as (W2), the difference between those spaces with reference to the conductive circuit thickness (T) satisfies the formula 0.10T <=||W1 - W2| |<=0.73T. The above-described structure can suppress crosstalk and delayed signal transmission and prevent malfunctions of ICs even when high-speed driven ICs are mounted.

Description

technical field [0001] The present invention relates to a printed circuit board having a fine wiring structure that does not cause malfunction due to crosstalk, signal transmission delay, etc. even if a high-speed drive IC is mounted thereon. Background technique [0002] A laminated printed wiring board is an example of a printed wiring board formed by filling insulating material between conductive circuits. In such a printed wiring board, for example, conductive circuits and interlayer resin insulating layers are alternately laminated on a core substrate, and the conductive circuits on the lower layer and the conductive circuits on the upper layer are electrically connected through so-called via holes. The via hole is formed by opening an interlayer resin insulating layer and providing a plated film on the opening (see Japanese Laid-Open Patent Publication No. 11-176985 or Japanese Laid-Open Patent Publication No. 11-243279). [0003] In such a printed circuit board, inte...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H05K1/02H05K3/46
Inventor 中井通玉木昌德
Owner IBIDEN CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com