7 results about "Bistable circuits" patented technology

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

An electronic circuit has: a cell array having a plurality of memory cells, each memory cell having a bistable circuit having a first inverter circuit and a second inverter circuit capable of switching between a first mode having a transfer characteristic substantially free of hysteresis and a second mode having a transfer characteristic with hysteresis, an output node and an input node of the first inverter circuit being connected to an input node and an output node, respectively, of the second inverter circuit; and a control circuit that, after powering off one or more first memory cells of the plurality of memory cells in which data can not be retained, sets the bistable circuits within one or more second memory cells of the plurality of memory cells remaining powered on to the second mode, provides a second supply voltage to the bistable circuits within the one or more second memory cells in a state maintaining the second mode, the second supply voltage being lower than a first supply voltage provided to the bistable circuits when reading and / or writing data, the second mode bistable circuits being capable of retaining data at the second supply voltage.

An electronic circuit is provided with: a cell array having a plurality of memory cells, each memory cell having a bistable circuit and a non-volatile element, the bistable circuit storing data in a volatile manner, the non-volatile element storing data stored in the bistable circuit in a non-volatile manner, the non-volatile element storing data stored in the bistable circuit in a non-volatile manner; and recovering the data stored in a non-volatile manner into the bistable circuit. And a control circuit that, when the cell array is powered off, extracts one or more first memory cells, among the plurality of memory cells, that volatile store data that may not be stored non-nonvolatile regardless of whether or not the memory cells are volatile rewritten, and powers off the one or more first memory cells, after the one or more first memory cells are powered off, a storage action of storing data stored in the bistable circuit to the non-volatile element is performed in the remaining one or more second memory cells among the plurality of memory cells, after which the one or more second memory cells are powered off.

An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and / or written, to the bistable circuit in the second memory cell while maintaining the second mode.

The invention discloses a four-gate field effect transistor, a preparation method thereof and a bistable circuit. The four-gate field effect transistor comprises a semiconductor substrate; a buried oxide layer located on the semiconductor substrate; the junction gate layer and the active layer are located on the buried oxide layer; the junction gate layer comprises a first junction gate and a second junction gate; the active layer comprises a source region and a drain region; the channel region is located between the source region and the drain region, and the channel region is located between the first junction gate and the second junction gate; the top gate is positioned on the channel region; an isolation region; the channel region comprises a first channel located between the first junction gate and the isolation region; the second channel is positioned between the second junction gate and the isolation region; the top gate comprises a first gate and a second gate; the source region comprises a first source electrode and a second source electrode; the drain region comprises a first drain electrode and a second drain electrode; the first grid electrode is electrically connected with the second drain electrode and the second junction gate, and a first input voltage is accessed; the second grid electrode is electrically connected with the first drain electrode and the first junction gate, and a second input voltage is accessed; the isolation region is grounded; the first source electrode and the second source electrode are connected with power supply voltage.

The invention discloses a bistable PUF (Physical Unclonable Function) circuit based on dynamic division multiplexing of a cross coupling structure, which comprises W PUF unit arrays, each PUF unit array comprises m PUF units, each PUF unit comprises a PMOS (P-channel Metal Oxide Semiconductor) unit consisting of four PMOS tubes and an NMOS (N-channel Metal Oxide Semiconductor) unit consisting of four NMOS tubes, the PMOS units and the NMOS units form a central symmetry structure, the PUF unit arrays have an NMOS mode and a PMOS mode, and each PUF unit array has an N-channel Metal Oxide Semiconductor (NMOS) mode and an N-channel Metal Oxide Semiconductor (PMOS) mode. An NMOS (N-channel Metal Oxide Semiconductor) mode or a PMOS (P-channel Metal Oxide Semiconductor) mode is selected for a PUF (Physical Unclonable Function) unit array, so that an NMOS unit or a PMOS unit of each PUF unit is used as a PUF entropy source to generate PUF response, one PUF unit selected in each PUF unit array can originate from different PUF responses generated by random process deviation of different transistors (four NMOS tubes or four PMOS tubes) in the PUF unit array, and the entropy sources are mutually independent; the method has the advantages of low hardware resource overhead and high entropy source utilization rate under the condition of relatively high attack resistance.

This inverter circuit comprises: a first FET of a channel of a first conductivity type in which the source is connected to an intermediate node, the drain is connected to a first power supply line, and the gate is connected to an output node; a second FET of a channel of a second conductivity type different from the first conductivity type in which the source is connected to the intermediate node, the drain is connected to the output node, and the gate is connected to an input node; and a third FET of a channel of the first conductivity type in which the source is connected to a second power supply line and the drain is connected to the output node.