3 results about "Bistable circuits" patented technology

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

The invention discloses a four-gate field effect transistor, a preparation method thereof and a bistable circuit. The four-gate field effect transistor comprises a semiconductor substrate; a buried oxide layer located on the semiconductor substrate; the junction gate layer and the active layer are located on the buried oxide layer; the junction gate layer comprises a first junction gate and a second junction gate; the active layer comprises a source region and a drain region; the channel region is located between the source region and the drain region, and the channel region is located between the first junction gate and the second junction gate; the top gate is positioned on the channel region; an isolation region; the channel region comprises a first channel located between the first junction gate and the isolation region; the second channel is positioned between the second junction gate and the isolation region; the top gate comprises a first gate and a second gate; the source region comprises a first source electrode and a second source electrode; the drain region comprises a first drain electrode and a second drain electrode; the first grid electrode is electrically connected with the second drain electrode and the second junction gate, and a first input voltage is accessed; the second grid electrode is electrically connected with the first drain electrode and the first junction gate, and a second input voltage is accessed; the isolation region is grounded; the first source electrode and the second source electrode are connected with power supply voltage.

This inverter circuit comprises: a first FET of a channel of a first conductivity type in which the source is connected to an intermediate node, the drain is connected to a first power supply line, and the gate is connected to an output node; a second FET of a channel of a second conductivity type different from the first conductivity type in which the source is connected to the intermediate node, the drain is connected to the output node, and the gate is connected to an input node; and a third FET of a channel of the first conductivity type in which the source is connected to a second power supply line and the drain is connected to the output node.