171 results about "Bistable circuits" patented technology

The present invention is a memory circuit that includes a bistable circuit that stores data, and a ferromagnetic tunnel junction device that nonvolatilely stores the data in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored in the bistable circuit. According to the present invention, writing data to and reading data from the bistable circuit can be performed at high speed. In addition, even though a power source is shut down, it is possible to restore data nonvolatilely stored in the ferromagnetic tunnel junction devices to the bistable circuit.

A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.

The purpose of this invention is to increase reliability of a switching element while reducing consumption power. In the vertical blanking period, an end pulse signal (ED) changes from the low level to the high level. The potential of first nodes (N1) in the first stage to (m−1)th stage of cascade-connected m-stage bistable circuits included in a shift register of the scanning signal drive circuit is reliably maintained at the low level, and the potential of second nodes (N2) in the first stage to the (m−1)th stage changes from the high level to the low level. In a bistable circuit in the m-th stage, the potential of the first node (N1) in the m-th stage changes from the high level to the low level, and the potential of the second node (N2) in the m-th stage is maintained at the low level. The supply to a bistable circuit of clock signals (CKA, CKB) is stopped. Until a write period in the subsequent vertical scanning period, the potential of the first node (N1) and the potential of the second node (N2) in each stage are maintained at the low level.

There is realized a scanning signal line drive circuit (in a display device) capable of, even in a case where a circuit in a shift register is formed using a thin-film transistor which is relatively large in off leakage, suppressing unnecessary power consumption due to a leakage current in the thin-film transistor. In at least one embodiment, bistable circuit that forms the shift register includes a thin-film transistor for raising a potential of an output terminal based on a first dock, a region netA connected to a gate terminal of the thin-film transistor, another thin-film transistor for lowering a potential of the region netA, and a region netB connected to a gate terminal of the other thin-film transistor. With this configuration, the potential of the region netB is raised based on a third clock which is advanced in phase by 90 degrees with respect to the first clock and is lowered based on a fourth clock which is delayed in phase by 90 degrees with respect to the first clock.

Stability of a circuit operation in a monolithic gate driver is improved. A bistable circuit is provided with a charge replenishment circuit (71) including: a capacitor (CAP2); a thin-film transistor (MA) having a first electrode supplied with a first clock for charge replenishment (CKA), a second electrode connected to a third-node (N3) connected to one end of the capacitor (CAP2), and a third electrode connected to a second-node (N2) to be maintained at the high level during a normal operation period; and a thin-film transistor (MB) having a first electrode supplied with a second clock for charge replenishment (CKB), a second electrode supplied with a high-level DC power supply potential (VDD), and a third electrode connected to the third-node (N3). The first clock for charge replenishment (CKA) and the second clock for charge replenishment (CKB) are alternately driven to the high level so as to eliminate a period in which “the first clock for charge replenishment (CKA) is at the high level and the second clock for charge replenishment (CKB) is at the high level”.

Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device.

In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged. In the second discharge step, the clear signal (H_CLR) is set at the high level, and electric charges on floating nodes in each of the bistable circuits are discharged.

In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.

A mechanism is provided for a circuit for generation of a random output. A bistable circuit has two stable states as an output and a clock signal as an input. The bistable circuit includes a first logic circuit and a second logic circuit cross-coupled connected together, which transition into a metastable state before resolving to the two stable states. The second logic circuit resolves to a stable state at a resolution time. A digitization circuit is configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal. The resolution time randomly varies according to noise. An actual value of the stable state is eliminated as factor in generating the random bits.

A circuit for generating a random output value is disclosed that comprises: a bistable circuit having two stable states in which a 0 or a 1 is output and having a balanced metastable state in which a floating value between 0 and 1 is output, said bistable circuit resolving from said metastable state to one of said stable states on being switched on, said state depending on a voltage level at a port on said bistable circuit; a voltage level control circuit for controlling a voltage level at said port on said bistable circuit; a time measuring circuit for measuring a switching time taken for said bistable circuit to switch from said metastable state to one of said stable states following switch on; and control logic for controlling said time measuring circuit, said voltage level control circuit and a switching off and on of said bistable circuit, said control logic being adapted to perform a following sequence: control said voltage level control circuit to set a predetermined voltage level at said port on said bistable circuit, switch said bistable circuit on, detect a measured switching time, and turn said bistable circuit off and if said measured switching time is longer than a predetermined value, output said resolved stable state of said bistable circuit as said random output value.

A bistable circuit includes an input terminal (41) for a set signal, an input terminal (42) for a reset signal, an output terminal (48) for a state signal, a thin-film transistor (M2) for increasing a potential of the output terminal (48) based on a first clock, a thin-film transistor (M1) for increasing a potential of a first-node connected to a gate terminal of the thin-film transistor (M2) based on the set signal, a thin-film transistor (M5) for decreasing the potential of the first-node, a thin-film transistor (M7) for increasing a potential of a second-node connected to a gate terminal of the thin-film transistor (M5) based on the reset signal, a thin-film transistor (M6) for decreasing the potential of the output terminal (48) based on the potential of the second-node, a thin-film transistor (M3) for increasing the potential of the second-node based on the set signal, and a capacitor (CAP2) having one end connected to the second-node and the other end connected to the input terminal (41).

A gate driver is implemented that includes an easily testable shift register to improve panel yields. In a monolithic gate driver including a shift register that operates based on 4-phase clock signals, each stage of the shift register is provided with an inter-stage connecting wiring line for receiving a clock signal other than clock signals received from a clock signal trunk wiring line, from a different stage than the stage; and a contact that connects a wiring line formed on the stage to the inter-stage connecting wiring line. The shift register is grouped every four consecutive stages. Markings formed of different numbers of planar-view circular-shaped structures are formed on bistable circuits of four stages included in each group such that the same type of marking appears every four stages.

The present invention is directed to suppress dullness of a scanning signal in a scanning signal line drive circuit. A bistable circuit is provided with an input terminal (43) for receiving a first clock signal (CK), an input terminal (48) for receiving a control signal (CT), an input terminal (49) for receiving a level down signal (LD), an output terminal (51), a thin film transistor (T2), and a thin film transistor (TA). The thin film transistor (T2) has a gate terminal connected to a first node (N1), a drain terminal connected to the input terminal (43), and a source terminal connected to the output terminal (51). The thin film transistor (TA) has a gate terminal connected to the input terminal (48), a drain terminal connected to the first node (N1), and a source terminal connected to the input terminal (49). The potential of the control signal (CT) becomes the high level in a control period as a period except for the first one horizontal scanning period in a vertical blanking period. The level down signal (LD) is a potential lower than DC power supply potential (Vss).

A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

The invention discloses a measuring circuit of single-particle pulse width. The measuring circuit comprises a single-particle pulse signal generating circuit and at least one stage of a measuring circuit. The single-particle pulse signal generating circuit generates a single-particle pulse signal to be measured. A bistable circuit directly driven by the single-particle pulse signal to be measured forms a first stage of the measuring circuit. From a second stage of the measuring circuit on, each stage of circuit is composed of a pulse attenuator circuit and a bistable circuit. The input ends of the pulse attenuator circuits are connected with the signal input ends of the bistable circuits of former stages, and output ends of the pulse attenuator circuits are connected with the signal input ends of the bistable circuits of identical stage circuit. The output ends of a stage of preset bistable circuit or multiple stages of preset bistable circuits form the output result of the measuring circuit together, and the output result corresponds to the single-particle pulse width. The measuring circuit of the single-particle pulse width can improve the measuring accuracy of the single-particle pulse width, and reduce equipment cost.

The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17).

The present invention provides a Single-Event-Upset (SEU) and Single-Event-Gate-Rupture (SEGR) protection against incident radiation for any bi-stable circuit either in one state, having a 2 transistor, 1 capacitor integrated circuit coupled to a bi-stable circuit's outputs, or in both states, having a 4 transistor, 2 capacitor integrated circuit coupled to the bi-stable circuit's outputs. The protection against SEU and SEGR is achieved by the 2T1C or the 4T2C circuits, by providing the opposite drive to the SEU or SEGR event through capacitive coupling, and shunting electron-hole pair current, created by an ion tracking through the bi-stable circuit, into the power supplies. The 2T1C integrated circuit architecture, which only protects bi-stable circuits in one state, is to allow the bi-stable circuit to be a Single-Event-Upset (SEU) detector by capturing the effect of an incident ion and store that state. The 2T1C architecture, while protecting the bi-stable circuit after it has been affected by incident radiation, can alert the system the bi-stable integrated circuit is embedded in, to compensate or at be aware that an Single-Event-Upset has occurred. The purpose of the 4T2C integrated circuit architecture, which protects bi-stable circuits in both stable states, is to allow for critical data/state retention in any radiation environment, while not effecting speed of operation.

A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

The invention provide a three-limit time-base circuit composed of analogue integrated circuit operational amplifier A (or voltage comparator B), few separate electronic elements by using new principleand ingenious connection mode. The three-limit time-base circuit has top and bottom limit main control functions completely compatible to all functions of classic 555 time-base circuit can be used asultra-top and bottom limit control circuit and astable, monostable and bistable circuit. The invention increases exceed bottom limit protection and control function, when inputted sensing circuit hasfault, fault display and protection control can be executed in time to prevent the main control circuit from being out of control. The invention, used in control circuits for temperature, pressure, water level etc., may improve security, and prevent severe accidents (such as fire hazard). So, the invention has wide use in electronic application field such as household electrical appliances, simple controllers, and high cost performance of products are provided.

The invention discloses a measuring circuit for single-event transient pulse width. The measuring circuit for single-event transient pulse width comprises a single-event pulse signal generating circuit (103) and at least one measuring circuit. Primary stage of the measuring circuit consists of a bistable circuit. From the second stage, each stage of the measuring circuit comprises a delay circuit, a logic gate circuit and a bistable circuit. In the second stage, input signal of the delay circuit is signal to be measured, input signal of the logic gate circuit serves as output signal of the delay circuit and output signal of the first-stage bistable circuit, and output signal of the logic gate circuit serves as input signal of the bistable circuit in the second stage. From the third stage, the input signal of the delay circuit in each stage serves as the output signal of the logic gate circuit in the previous stage, the input signal of the logic gate circuit serves as the output signal of the current-stage delay circuit and the output signal of the previous bistable circuit, and the output signal of the current-stage logic gate circuit serves as the input signal of the current-stage bistable circuit. The measuring circuit is capable of measuring within a wide pulse width range and is high in measuring precision.

A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

A DC-AC frequency converter type nose cleaner includes an electromagnetic pump, a container storing a cleaning solution, a nose-washing tool and a frequency converter circuit driving the electromagnetic pump. The frequency converter circuit at least includes an oscillator circuit, a bistable circuit and a push-pull circuit. The electromagnetic pump is supplied with AC obtained from the oscillation of DC in the frequency converter circuit. The swing speed, the swing frequency and the swing amplitude of the swing arms vary with the change of the oscillation frequency of the oscillator circuit. Thereby, the discharge pressure and the discharge flow of the electromagnetic pump could further be changed to obtain the most appropriate discharge pressure and discharge flow of the nose cleaner. In other words, the DC-AC frequency converter type nose cleaner can change the pressure and the flow generated by the electromagnetic pump so as to satisfy the requirement of the discharge pressure and flow of the nose cleaner so as to overcome the defect of the discharge pressure of the conventional nose cleaner that is too big to hurt the user.