Scanning signal line driving circuit, display device provided therewith, and scanning signal line driving method
A technology for scanning signal lines and driving circuits, which is applied to electrical components, information storage, static indicators, etc., and can solve problems such as reduced reliability of transistors and large threshold fluctuations
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no. 1 Embodiment approach >
[0137]
[0138] figure 1 It is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention. Such as figure 1 As shown, the liquid crystal display device includes: a power supply 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line drive circuit) 300, a gate driver (scanning signal line drive circuit) 400, a common electrode The driving circuit 500 and the display unit 600 . In addition, the gate driver 400 is formed on the display panel including the display portion 600 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, or an oxide semiconductor (such as IGZO). That is, in this embodiment, the gate driver 400 and the display unit 600 are formed on the same substrate (the array substrate which is one of the two substrates constituting the liquid crystal panel). Accordingly, the frame area of the liquid cry...
no. 2 Embodiment approach >
[0209]
[0210] Figure 22 It is a signal waveform diagram for explaining the detailed operation of the gate driver 400 according to the second embodiment of the present invention. In addition, the overall configuration and operation of the liquid crystal display device, the configuration and operation of the gate driver 400, the configuration and operation of the bistable circuit, and the configuration and operation of the clock control circuit 420 are the same as those of the above-mentioned first embodiment. These descriptions are therefore omitted.
[0211] In the above-mentioned first embodiment, a vertical retrace period (about 8.3 msec) of about 1 / 2 the length of one vertical scan period is provided, and the drive frequency in the writing period is doubled the general drive frequency (60 Hz). That is 120Hz (about 8.3msec). In contrast, in this embodiment, if Figure 22 As shown, set a vertical retrace period (approximately 11.1msec) of approximately 2 / 3 the length ...
no. 3 Embodiment approach >
[0215]
[0216] Figure 23 It is a signal waveform diagram for explaining the detailed operation of the gate driver 400 according to the third embodiment of the present invention. In addition, the overall configuration and operation of the liquid crystal display device, the configuration and operation of the gate driver 400, the configuration and operation of the bistable circuit, and the configuration and operation of the clock control circuit 420 are the same as those of the above-mentioned first embodiment. These descriptions are therefore omitted.
[0217] In the above-mentioned first embodiment, a vertical retrace period (about 8.3 msec) of about 1 / 2 the length of one vertical scan period is provided, and the drive frequency in the writing period is doubled the general drive frequency (60 Hz). That is 120Hz (about 8.3msec). In addition, in the above-mentioned second embodiment, the vertical retrace period (about 11.1 msec) having a length of approximately 2 / 3 of one v...
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