9 results about "Return-to-zero" patented technology

A server rack with a plurality of compute nodes is positioned in a facility that includes a spine and the server rack includes a middle of rack (MOR) switch located near the middle of the server rack, vertically speaking. The MOR switch includes a plurality of ports that are connected via passive cables to the compute nodes provided in the server rack. In an embodiment the passive cables are configured to function at 56 Gbps using non-return to zero (NRZ) encoding and each cable may be about or less than 1.5 meters long. An electrical to optical panel (EOP) can be positioned adjacent a top of the server rack and the EOP includes connections to the MOR switch and to the spine, thus the EOP helps connect the MOR switch to the spine. Connections between adjacent server racks can provide for additional compute bandwidth when needed.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

The utility model relates to the technical field of radio controlled clocks, and discloses a pointer type radio controlled clock movement capable of quickly calling memory time, which comprises a shell, a pointer shaft is arranged in the center of the shell, a gear is connected to the bottom of the pointer shaft, and a PCB (printed circuit board) is arranged in the shell. According to the pointer type radio controlled clock movement capable of quickly calling the memory time, the microcontroller, the main battery, the memory battery, the voltage stabilizing module, the power supply switching module, the battery low-voltage detection module, the signal receiving and timing module and the movement driving chip are arranged on the PCB, so that the whole machine has a time memory function; the pointers can call and memorize within sixty seconds after returning to zero, quickly display current standard time, save time and electric energy, optimize user experience, and solve the problems that when a battery of an existing radio controlled clock is replaced, signals are difficult to receive, electric energy and time are wasted in vain, energy conservation and environmental protection are not facilitated, and the service life of the existing radio controlled clock is prolonged due to the fact that radio signals in the daytime are complex and large in interference. And the user experience is poor.

The invention discloses an order preserving method and device, electronic equipment and a storage medium, and belongs to the technical field of computers. The method comprises the steps that transaction layer packets are received, corresponding authorization indication signals are generated, the authorization indication signals are used for representing the receiving time sequence of the corresponding transaction layer packets, the transaction layer packets are divided into first-class packets and second-class packets, the first-class packets are used for achieving one-way data issuing, and the second-class packets are used for achieving two-way data interaction; based on the authorization indication signal of each transaction layer packet, recording the number of preposed first-class packets associated with each second-class packet, the authorization indication signal of the preposed first-class packet being generated before the second-class packet; and for the processed second type of packets, when the number of the preposed first type of packets associated with the second type of packets is zero, sending the second type of packets. According to the scheme, the number of the front packets is counted by adopting the authorization indication signal, and the order preservation is realized according to the judgment on whether the number of the front packets returns to zero or not, so that additional parameters do not need to be processed along with a pipeline, and the hardware resource overhead is reduced.

A translation device includes a first input / output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a non-return to zero (NRZ) method through a plurality of first pins; a second input / output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a pulse amplitude modulation-3 (PAM-3) method through a plurality of second pins; and a translation circuit configured to translate the first signal to the second signal, or translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first signal speed.

The invention discloses a steam turbine control system and a communication fault protection method and module thereof, and the communication fault protection method comprises the steps: monitoring a communication signal between a processor and a previous processor, and judging whether a communication fault exists between the processor and the previous processor or not according to the communication signal, the steam turbine control system comprises a plurality of processors in chain communication connection. When a communication fault exists, a TAB control signal output by the processor is switched to a safety value, and the safety value is larger than zero; and when the communication fault does not exist, outputting the TAB control signal output by the former processor to the latter processor. According to the technical scheme, the tripping hidden danger that the TAB control signal returns to zero due to off-network of the processor can be thoroughly eliminated, the operation safety of a unit is improved, and only the process is stopped and the original system control logic is not damaged if a communication fault occurs in the rush-to-turn stage.

An interface chip includes a first interface circuit connected to a test device, the first interface circuit providing an interface for a first non-return to zero (NRZ) signal and a sideband signal for the test device; a second interface circuit connected to a device under test (DUT), the second interface circuit providing an interface for a second NRZ signal and a pulse amplitude modulation (PAM) signal for the DUT; and a conversion circuit connected to the first interface circuit and the second interface circuit, the conversion circuit providing conversion between the first NRZ signal and the second NRZ signal and between the first NRZ signal and the PAM signal based on the sideband signal.

The invention discloses a high-frequency pulse direct-current power supply output stability control device, and belongs to the technical field of power supply control. The device provides a state return-to-zero-knowledge injection control normal form aiming at the contradiction that a traditional controller is slow in response after opening through punching and resetting due to integral memory in a pulse mode. At the starting moment of each pulse period, generating a pulse starting instruction and delaying to generate a reset signal, forcibly discharging the integrating capacitor to enable the output of the integrating capacitor to return to zero, and eliminating the overshoot hidden danger; determining a feed-forward control value according to a load current steady-state value collected during the turn-off period of the last pulse and a current target duty ratio; and in the same control period when the integral value returns to zero, adding the feed-forward value and the integral output value to generate a driving control signal, and finally modulating and driving the power switch to output pulse current. Through cooperation of physical state forced zero clearing and system knowledge cross-period prediction injection, rapid non-overshoot establishment of the pulse current is realized, and the dynamic performance bottleneck of the high-frequency pulse power supply is effectively solved.

This invention belongs to the field of new energy grid connection technology and relates to an improved adaptive virtual current pre-synchronization method considering secondary frequency regulation. The method includes the following steps: determining the virtual current; coordinate transformation; superposition; secondary reconstruction; determining the adaptive proportional gain and adaptive integral gain; inputting an adaptive PI controller; and grid connection. This invention completely eliminates the phase-locked loop (PLL) by constructing a virtual current, fundamentally eliminating the system instability risk caused by PLLs in weak grids. By performing secondary reconstruction on the q-axis component of the virtual current, it completely solves the problem of control quantity returning to zero when the phase difference is close to 180° in traditional PLL-free strategies, achieving smooth synchronization and shortest path convergence across the entire phase angle range. By establishing a small-signal model of the frequency difference to determine the maximum allowable angular frequency compensation and designing an adaptive PI control law with error feedback, it maximizes the synchronization speed while ensuring that the frequency does not exceed the limit, achieving an adaptive balance between pre-synchronization efficiency and frequency safety.