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207 results about "Non-return-to-zero" patented technology

In telecommunication, a non-return-to-zero (NRZ) line code is a binary code in which ones are represented by one significant condition, usually a positive voltage, while zeros are represented by some other significant condition, usually a negative voltage, with no other neutral or rest condition. The pulses in NRZ have more energy than a return-to-zero (RZ) code, which also has an additional rest state beside the conditions for ones and zeros. NRZ is not inherently a self-clocking signal, so some additional synchronization technique must be used for avoiding bit slips; examples of such techniques are a run-length-limited constraint and a parallel synchronization signal.

Method and apparatus for transmitting a signal using simultaneous FM and AM modulation

InactiveUS20060029397A1Wider flat top regionElectromagnetic transmittersFall timeCarrier signal
There is provided method for transmitting binary data contained in respective successive time cells, the data being in the form of an optical signal obtained by amplitude modulation and frequency modulation of an optical carrier wave, with a 0 bit data value having a 0 bit mean amplitude having a 0 bit amplitude time duration and a 0 bit frequency having a 0 bit frequency duration, and a 1 bit data value having a 1 bit mean amplitude having a 1 bit amplitude time duration and a 1 bit frequency having a 1 bit frequency duration; the improvement wherein: independently adjusting the 0 bit mean amplitude relative to the 1 bit mean amplitude; independently adjusting the 0 bit frequency relative to the 1 bit frequency; and independently adjusting time duration of the frequency profile of the 1 bit relative to the time duration of the amplitude profile of the 1 bit, whereby to extend the error-free propagation of the optical signal though a dispersive optical fiber beyond the dispersion limit. There is provided a method for transmitting Non-Return-To-Zero (NRZ) binary data contained in respective successive time cells, the data being in the form of an optical signal obtained by amplitude modulation and frequency modulation of an optical carrier wave, with a 0 bit data value having a 0 bit mean amplitude having a 0 bit amplitude time duration and a 0 bit frequency having a 0 bit frequency duration, and a 1 bit data value having a 1 bit mean amplitude having a 1 bit amplitude time duration and a 1 bit frequency having a 1 bit frequency duration; the improvement wherein: the phase across each 1 bit data value is substantially constant, and the phase of the carrier changes across each and every 0 bit by an amount equal to the product of the frequency difference between the 1 bit and the 0 bit and the duration of the 0 bit; whereby to extend the error-free propagation of the optical signal though a dispersive optical fiber beyond the dispersion limit. In accordance with one form of the present invention, there is provided a method for transmitting binary data contained in respective successive time cells, the data being in the form of an optical signal obtained by amplitude modulation and frequency modulation of an optical carrier wave, with a 0 bit data value having a 0 bit mean amplitude having a 0 bit amplitude time duration and a 0 bit frequency having a 0 bit frequency duration, and a 1 bit data value having a 1 bit mean amplitude having a 1 bit amplitude time duration and a 1 bit frequency having a 1 bit frequency duration; the improvement wherein: the amplitude profile of the 1 bit is substantially bell-shaped, and the frequency profile of the 1 bit is substantially square-shaped, with steeper rise and fall time and a wider flat top region; whereby to extend the error-free propagation of the optical signal though a dispersive optical fiber beyond the dispersion limit.
Owner:AZNA +1

Excess delay compensation in a delta sigma modulator analog-to-digital converter

A high-performance delta sigma analog-to-digital converter. The high-performance delta sigma analog-to-digital converter includes a first mechanism for converting an input analog signal to a digital output signal. The first mechanism is characterized by a transfer function that is altered relative to an ideal transfer function. A second mechanism compensates for the alteration in the transfer function via a single additional digital-to-analog converter. In a specific embodiment, the alteration includes an additional pole and an additional zero induced by feedback delays in the first mechanism. The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism includes an additional latch that compensates for the signal dependent jitter delay. The first mechanism includes a resonator and a quantizer. The second mechanism includes a feedback path from an output of the quantizer to the resonator. The feedback path includes a first latch positioned between an output of the quantizer and the additional digital-to-analog converter. The additional latch is positioned at an output of the first latch and eliminates signal dependent jitter delay in the analog-to-digital converter. The additional feedback digital-to-analog converter is a non-return-to-zero digital-to-analog converter, an output of which is connected to the resonator.
Owner:RAYTHEON CO

High-speed parallel interface circuit

InactiveCN102510328AAccurate Sample RecoverySynchronising arrangementOriginal dataOversampling
The invention is suitable for the digital communication field, and provides a high-speed parallel interface circuit. The high-speed parallel interface circuit comprises a low voltage differential signaling (LVDS) receiving module, a data sampling module, a data restoring module and a word synchronization module, wherein the LVDS receiving module receives and shapes data; the data sampling module is connected with the LVDS receiving module and samples the data output by the LVDS receiving module under a plurality of phase clocks; the data restoring module is connected with the data sampling module, selects optimal sampling data from oversampling data output from the data sampling module and restores original data by non return to zero inverse (NRZI) decoding; and the word synchronization module is connected with the data restoring module and carries out shift adjustment to the data output by the data restoring module. In the high-speed parallel interface circuit, oversampling and word synchronization are combined to carry out accurate sampling restoration and synchronization to source-synchronous parallel data; and data in the center of an effective window can be dynamically and accurately sampled and restored in real time by dynamically synchronizing, filtering, discriminating phase, selecting the oversampling data and the like.
Owner:成都三零嘉微电子有限公司

Method And System For Encoding And Decoding Information With Modulation Constraints And Error Control

A method and system for encoding a segment of user data words into a segment of code words so that both modulation constraints and a predetermined parity-check constraint are satisfied. Each segment of the user data is partitioned into several data words, and encoded separately by first and second types of component code, which are referred to as the normal constrained code and the parity-related constrained code, respectively. The parity-check constraint over the combined code word is achieved by concatenating the sequence of normal constrained code words with a specific parity-related constrained code word chosen from a candidate code word set. Both the component codes are finite-state constrained codes, which are designed to have rates close to the Shannon capacity. Furthermore, they are based on the same finite state machine (FSM), which enables them to be connected seamlessly, without violating the modulation constraints. Two preferred embodiments are provided to design a code in the non-return-to-zero inverted (NRZI) format and the non-return-to-zero (NRZ) format, respectively. Designing the codes in NRZ format may reduce the number of parity-check bits required for error detection and simplify error correction or post-processing. The parity-check constraint is defined by the parity-check polynomial or parity-check matrix of a systematic linear block code, which could detect any type of dominant error event as well as error event combinations of a given optical recording system. As a result, the information density of the system is improved.
Owner:AGENCY FOR SCI TECH & RES

All-optical code conversion method with wavelength conversion function

InactiveCN102608832AOvercome the drawbacks of inflexible wavelength settingsLow waveguide efficiencyNon-linear opticsErbium dopingBand-pass filter
The invention discloses an all-optical code conversion method with a wavelength conversion function, which is characterized in that an RF (radio frequency) signal source sends out a radio-frequency signal with 10GHz recurrence frequency to be injected into a mode-locked semiconductor laser for active mode locking, the mode-locked semiconductor laser sends out an ultra-short pulse sequence with 10GHz recurrence frequency as pump light, an erbium-doped optical fiber amplifier is used for power amplification of the pump light prior to that spontaneous radiation noise is filtered by a filter 1, the pump light passes through a PC (polarization controller) 2 to realize optical coupling with an NRZ (non-return-to-zero) signal to be converted, and a PC1 on an NRZ signal light branch is used for adjusting the polarization state of a light beam. After coupling of the pump light and the NRZ signal, the pump light and the NRZ signal are injected into an overhigh-power erbium-doped optical fiber amplifier for power amplification prior to entering a 50-meter photonic crystal fiber and generating four-wave frequency mixing effect in the photonic crystal fiber, and two narrow-band optical filters are used for respectively filtering sidebands, so that a code conversion signal is obtained while wavelength conversion is completed, and a wavelength multicast function is realized.
Owner:XIAN UNIV OF POSTS & TELECOMM
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