High-speed parallel interface circuit

Abstract

The invention is suitable for the digital communication field, and provides a high-speed parallel interface circuit. The high-speed parallel interface circuit comprises a low voltage differential signaling (LVDS) receiving module, a data sampling module, a data restoring module and a word synchronization module, wherein the LVDS receiving module receives and shapes data; the data sampling module is connected with the LVDS receiving module and samples the data output by the LVDS receiving module under a plurality of phase clocks; the data restoring module is connected with the data sampling module, selects optimal sampling data from oversampling data output from the data sampling module and restores original data by non return to zero inverse (NRZI) decoding; and the word synchronization module is connected with the data restoring module and carries out shift adjustment to the data output by the data restoring module. In the high-speed parallel interface circuit, oversampling and word synchronization are combined to carry out accurate sampling restoration and synchronization to source-synchronous parallel data; and data in the center of an effective window can be dynamically and accurately sampled and restored in real time by dynamically synchronizing, filtering, discriminating phase, selecting the oversampling data and the like.

Description

technical field [0001] The invention belongs to the field of digital communication, in particular to a high-speed parallel interface circuit. Background technique [0002] With the vigorous development of digital communication services, the communication system poses unprecedented challenges to the transmission bandwidth of communication interfaces. Among them, high-speed parallel interface and high-speed serial interface solutions are widely used in optical fiber communication, data exchange and other fields. For high-speed parallel transmission, the effective recovery of data and channel synchronization are transmission bottlenecks. There are two main problems: one is that when the single-line transmission rate becomes faster and faster, the time window occupied by each bit of data becomes smaller and smaller. As a result, it is difficult for the clock to sample accurately in the effective window of the data; secondly, due to the different delays of the data paths in paral...

AI Technical Summary

Problems solved by technology

For high-speed parallel transmission, the effective recovery of data and channel synchronization are transmission bottlenecks. There are two main problems: one is that when the single-line transmission rate becomes faster and faster, the time window occupied by each bit of data becomes smaller and smaller. As a result, it is difficult for the clock to sample accurately in the effective window of the data; secondly, due to the different delays of the data paths transmitted in parallel, it is difficult for the receiving end to effectively receive data synchronously

However, the design of the analog clock data recovery circuit is relatively complicated. The sudden data signal cannot meet the fast synchronization requirements. The large phase jitter will easily cause the PLL to lose lock. The PLL locks for a long time and only provides serial clock data. recovery and sampling without providing a parallel data transfer solution

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