The invention relates to the cross technical field of integrated circuits and neural
engineering, discloses an in-memory adaptive
clock synchronization method and
chip for a multi-mode brain-computer interface
signal, and aims to solve the problems of large
phase jitter, high
power consumption and slow dynamic response caused by large sampling
rate difference and dependence on an external non-adaptive phase-locked loop in the prior art. According to the method,
instantaneous energy features of high-frequency electroencephalogram signals are extracted in real time in a storage and calculation integrated
feature extraction array,
phase adjustment control signals are generated through an energy-to-phase module, and a local
ring oscillator is dynamically adjusted to generate a self-adaptive low-frequency sampling
clock which is used for triggering sampling of low-frequency near-
infrared spectrum signals and binding a high-precision
timestamp. The
system comprises a near
infrared spectrum
signal acquisition module, a storage and calculation integrated
feature extraction array, an energy-to-phase module, a
digital control ring oscillator, a
timestamp generation module and a state synchronization control module. According to the invention, through a storage and calculation integrated closed-loop feedback mechanism, sub-
picosecond-level synchronization precision, ultra-low
power consumption and high-sensitivity response to key neural events are realized.