53 results about "Circuit extraction" patented technology

The invention provides a voltage stability control method for a multi-output switching power supply, which comprises the following steps of: sampling a main output channel in real time to obtain a voltage signal; the voltage signal is processed through a wide bandwidth error amplifier, a main channel adjusting signal is generated, and the main channel adjusting signal is used for driving a main power switch device; receiving an input voltage fluctuation frequency band of an auxiliary channel, a load current transient change gradient and a frequency spectrum coupling characteristic of a main channel adjusting signal through a dynamic prediction model, and generating an auxiliary channel adjusting signal with a phase lead compensation characteristic; a cross coupling active offset mechanism is constructed, time domain-frequency domain characteristics of coupling interference are extracted through a high-precision differential detection circuit, amplitude-frequency adjustable reverse correction signals are generated in real time through an adaptive compensation algorithm and injected into control nodes of an auxiliary output channel, and dynamic decoupling and ripple suppression are carried out. According to the method, high-stability control of multi-channel voltage under all working conditions is realized, and the dynamic response speed and the anti-interference capability are improved.

A state monitor system and a state monitor method capable of detecting an AE wave with high accuracy are provided. Accordingly, from a sensing signal SS output detected at an acoustic emission sensor 23, an AE-wave extracting circuit 55 extracts an AE wave AEW taking a structure that is a manufacturing target of three-dimensional printing process as a generation source. An AE-wave analyzing circuit 56 analyzes the AE wave AEW extracted by the AE-wave extracting circuit 55. In this case, the AE-wave extracting circuit 55 includes a noise cutting circuit cutting a first disturbance noise generated in a frequency band of the AE wave AEW while using a band-stop filter.

The invention belongs to the technical field of plasma impedance matching, and particularly relates to a plasma impedance matching optimization method based on backward reasoning, which comprises the following steps: constructing an impedance matching circuit comprising a plasma load, a radio frequency power supply and an impedance matching network; determining a control parameter set P formed by parameters of a plurality of elements in the impedance matching network and initializing a value; acquiring preset values of other discharge parameters except the P, operating an impedance matching circuit in combination with the current value of the P, and extracting impedance Zp of the load; calculating a preset performance index of the impedance matching circuit based on the current value of the P and the current Zp; and fixing the Zp value as the current value, searching the value of the P and operating the circuit again by taking the preset performance index minimization as the target through backward reasoning until the index reaches the threshold value, obtaining the optimal value of the P and the corresponding Zp value, and completing plasma impedance matching optimization. The matching method provided by the invention has the characteristics of rapidness, accuracy and strong robustness.

The invention relates to a matrix decomposition device and method based on a memristor cross array, which are suitable for efficient hardware implementation of singular value decomposition (SVD), the memristor cross array receives a conductance value mapped by a Grubrum matrix constructed by a to-be-decomposed matrix and a bit line input voltage converted by a bit line column vector, and outputs a corresponding current; converting the corresponding current into a voltage vector; performing normalization processing on the voltage vector to obtain a normalized vector; judging whether convergence occurs or not; performing normalization processing on the steady-state voltage vector to obtain a final output vector; and according to the final output vector, main characteristic values are extracted based on a first normalization circuit, and main singular values and corresponding singular matrixes are calculated. Compared with the prior art, the high parallel computing characteristic of the memristor cross array is utilized, efficient operation and hardware acceleration of matrix decomposition are achieved, the method has the advantages of being low in power consumption, high in speed and good in expansibility, and the method is suitable for application scenes such as artificial intelligence, signal processing and large-scale matrix operation.

The invention discloses an instruction tamper-proofing device for a traffic information board system, relates to the field of traffic information security, and solves the three technical problems of key clone risk, high computing power dependence and poor environmental adaptability of a traditional encryption scheme. A tamper-proof system is constructed through a triple cooperation mechanism: a unique unclonable physical feature is extracted based on a physical unclonable circuit, efficient integrity verification is realized through a segmented cascade parity check circuit, and a timestamp is accurately compared in combination with a temperature compensation clock; and multi-dimensional features are fused, spliced and integrated, tampering recognition is performed through feature comparison, and ultimate protection is formed if irreversible hardware is triggered to fail if tampering recognition is performed. The device achieves pure hardware millisecond-level response, thoroughly eliminates software dependence, maintains zero misjudgment rate in an extreme environment, ensures full-life-cycle safety of instructions through physical-level protection, and provides unduplicated safety guarantee for an information board system.

The application belongs to the field of electric power, and discloses a Kelvin emitter-based power IGBT junction temperature detection system and method, which comprises: a main circuit unit connected to a measured power IGBT module; a driving unit providing a gate driving signal for the measured IGBT module; a sampling unit extracting a collector current, an emitter, a Kelvin emitter and a gate signal from the main circuit and sending the signals to a junction temperature detection unit after edge detection; a temperature control unit regulating the ambient temperature of the main circuit unit; and the junction temperature detection unit receiving temperature control data and double-edge signals, fitting a correlation model of the interval time of the double-edge signals and the junction temperature, and calculating the working junction temperature according to the model. The application realizes online detection of the junction temperature of the IGBT module performance through accurate signal control, signal acquisition and intelligent junction temperature calculation, and has high precision and high efficiency.

This invention relates to a single-event latch-up evaluation method for advanced process technologies, comprising: constructing a high-energy particle incident model using the Geant4 Monte Carlo simulation tool; constructing and calibrating a three-dimensional basic device model using the TCAD simulation tool; constructing a standard cell circuit containing parasitic effects, extracting the parasitic thyristor structure of the standard cell circuit, and identifying sensitive regions of the parasitic thyristor structure; performing transient effect simulation on the identified sensitive regions based on the high-energy particle incident model to confirm whether latch-up is triggered; introducing anti-latch-up hardening measures for the sensitive regions, and performing simulation verification on the hardened standard cell circuit under the high-energy particle incident model; if the hardened standard cell circuit does not trigger latch-up, the anti-latch-up hardening measures are deemed effective. This method provides a systematic and automated solution that can fundamentally characterize the complex parasitic effects of advanced devices.

The invention discloses an electric power system quantum electromagnetic transient simulation method with a high quantum state utilization rate. The electric power system quantum electromagnetic transient simulation method comprises the following steps: S1, solving an electric quantity of an electric power system through quantum calculation; s2, transmission of action information of a control switch in a single simulation step length and quantum state transmission of a step length are realized through quantum stealth transmission; s3, through a multi-path parallel step length simulation quantum state providing method, parallel calculation is carried out to sequentially provide simulation quantum states with the difference of one step length; s4, constructing a quantum analysis circuit to extract electrical quantity characteristic information of the key node according to a stride length simulation quantum state in the time window; and S5, realizing long-time-consumption quantum computing task error suppression based on quantum teleportation by adopting a segmented quantum computing relay architecture. According to the method, the problem of low quantum electromagnetic transient simulation calculation efficiency caused by low quantum state utilization rate is solved aiming at the phenomenon of reading out a multi-step quantum state after quantum-classical information interaction and simulation in calculation.

Systems and methods for controlling valve actuators are provided. The system includes an interface circuit in electrical communication with a wiring connection from a pool / spa control system, and a processor in communication with the interface circuit. The interface circuit extracts a plurality of encoded bits transmitted to the interface circuit from the pool / spa control system over the wiring connection. The plurality of encoded bits could include Manchester-encoded bits that are encoded by the pool / spa control system by altering signals transmitted to the interface circuit over the wiring connection. The processor receives the plurality of encoded bits from the interface circuit and processes the plurality of encoded bits into a control command for controlling operation of the valve actuator. When a valid control command has been generated, the processor executes the control command to operate the valve actuator in accordance with the control command.

The present application relates to the technical field of electric parameter monitoring, and discloses a spark phenomenon identification processing system based on pulse feature fusion, comprising: a signal acquisition unit for acquiring controlled loop voltage and current signals; a feature preprocessing unit for extracting voltage and current change rates by using a hardware differential circuit; an arbitration processing unit for obtaining a change rate product by using a hardware multiplier to generate a correlation signal, and separating a high-frequency burr signal by using a high-pass filter circuit, and outputting a spark identification signal when the correlation signal crosses a negative determination threshold and the high-frequency burr signal pulse count exceeds a randomness threshold; and an output processing unit for executing loop locking according to the spark identification signal, wherein the present application utilizes the physical difference between random jump and smooth characteristics of a controlled switch in the discharge process, constructs time domain and topological dimension criteria, eliminates high-frequency power electronic commutation interference, reduces identification time delay, and guarantees the operation safety of the controlled loop.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The present invention provides a capacitance-based ground-hugging explosion fuse detection and control method, which includes the following steps: arranging capacitance detection electrodes at the head of the fuse, and using an oscillation circuit to establish a quasi-electrostatic field in the space around the projectile body by the electrodes. When a target appears near the projectile body, the quasi-electrostatic field is disturbed, causing a corresponding regular change in the equivalent capacitance between the fuse electrodes. The detector extracts this change information through a detection circuit, and after filtering, amplification, and A / D sampling, the processor performs signal processing and gives a detonation signal to achieve ground-hugging explosion control; according to the characteristic that the capacitance change amount of the capacitance detection is inversely proportional to the cube of the distance, as the distance between the projectile and the target approaches, the target signal should first change slowly and then change extremely rapidly. By combining the two characteristics, the fast-changing interference target signal is eliminated to achieve the purpose of anti-interference. The present invention realizes reliable recognition and detonation control of different types of targets, especially soft targets, and can improve the reliability of the fuse.

This invention relates to high-frequency amplifiers. A high-frequency amplifier (1) includes: an input terminal P IN Output terminal P OUT ; transistor (5), which is configured to amplify the input terminal P IN The RF signal; a matching circuit (9) and a reflection circuit (7), the matching circuit (9) for the fundamental frequency of the RF signal, and the reflection circuit (7) for the harmonics relative to the fundamental frequency, the matching circuit (9) and the reflection circuit (7) are connected in series between the transistor (5) and the output terminal P. OUT Between; extraction circuit (13), which is configured to extract the output terminal P OUT The harmonics at the point; processing circuits (15, 17) configured to adjust the phase and intensity of the harmonics extracted by the extraction circuit (13); and multiplexing circuit (19) configured to multiplex the harmonics processed by the processing circuits (15, 17) to the harmonics reflected by the reflection circuit (7) and provide the multiplexed harmonics to the transistor (5).

The invention provides a hardware Trojan horse detection method and system based on LLM and RTL semantic compression. The method comprises the steps that a to-be-detected modular RTL design circuit containing coarse-grained hardware Trojan horses is prepared; an AST is generated by using PyVerilog and is stored; establishing a tree topology structure according to the instance circuit, and recording depth information; extracting port name and bit width information for each instance circuit; extracting an assignment logic occurrence frequency for each instance circuit; extracting a judgment condition occurrence frequency for each instance circuit; establishing feature similarity between instance circuits by using a cosine similarity algorithm; constructing a modular design current feature set, and preparing an LLM input prediction; proper cue words are designed, and cue word fine adjustment is carried out on the mainstream large model; and obtaining an output result, and carrying out statistical calculation according to the to-be-tested index. The technical problems that static analysis is restricted by code complexity and abstraction levels, and dynamic analysis is easily influenced by insufficient verification scenes are solved.

The invention discloses an impedance extraction device and method under magnetic core saturation excitation, and relates to the technical field of electromagnetic compatibility. The device comprises an injection device and an extraction device. The injection device comprises a power amplification circuit, an AC-DC power supply, a signal generator, an MCU control circuit and a current detection circuit, and the extraction device comprises a high-frequency filter circuit, a feed-through capacitor, a first radio frequency current probe, a second radio frequency current probe, a magnetic core clamp, a first high-pass filter, a second radio frequency current probe and a vector network analyzer output end. According to the method, controllable current is applied to the magnetic core through the injection device to enable the magnetic core to be saturated, and meanwhile, the impedance of the magnetic core in a saturated state is extracted on line by utilizing a vector network analyzer and a double-probe method in the extraction device in combination with SOL calibration and a specific impedance calculation formula. According to the method, the impedance of the magnetic core under different saturation degrees can be obtained, the test process is simple, and the sensitivity and operability are high.

The present invention discloses a high-precision bandgap reference circuit, comprising: a bandgap circuit, which adopts a cascode current mirror structure to generate a positive temperature coefficient current and a negative temperature coefficient voltage; a negative temperature coefficient current extraction circuit, which extracts the negative temperature coefficient voltage generated by the bandgap circuit and generates a negative temperature coefficient current; a current compensation circuit, which receives the current I0 output by the negative temperature coefficient current extraction circuit and the positive temperature coefficient current I generated by the bandgap circuit. IN , and output current with positive temperature coefficient I IN Second-order related compensation current I out The present invention not only retains the advantages of the traditional Bandgap voltage reference such as simple structure and strong process compatibility, but also achieves the goals of low output voltage temperature coefficient and low power consumption.

The present invention discloses an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier, comprising a class F oscillator, a third harmonic extraction frequency multiplier, a negative peak detection circuit, a low-pass filter, a sample-and-hold circuit, a comparator, and a logic circuit. The class F oscillator obtains a periodic pseudo-square wave AC differential signal; the third harmonic extraction frequency multiplier obtains a third harmonic differential signal after fundamental frequency suppression; the negative peak detection circuit extracts the amplitude signal of the third harmonic differential signal; the low-pass filter filters the amplitude signal to a DC level; the comparator compares the amplitude signals of different frequency bands and outputs the comparison result; and the logic circuit controls the switched capacitor array in the third harmonic extraction frequency multiplier to adaptively switch the frequency band to the desired frequency band. The present invention can achieve automatic tracking of the third harmonic, solving the problems that the third harmonic frequency multiplier can only achieve excellent phase noise within a narrow frequency band and requires manual adjustment of the frequency band, which takes too much time.

The invention discloses an MOS (Metal Oxide Semiconductor) transistor grid charge balancing method and system for parasitic capacitance charge counteracting logic, and relates to the field of power electronic device driving. According to the method, a gate voltage second derivative characteristic signal is extracted through a cascade analog differentiating circuit to identify parasitic capacitance transient disturbance, and asynchronous quantization is triggered to generate a digital quantized value when an amplitude exceeds a threshold value; a clockless asynchronous combinatorial logic retrieval circuit retrieves a charge compensation control index from a charge compensation lookup table; after the programmable current mirror array is decoded, the current mirror branch is selectively conducted, and quantitative compensation charges are applied to a grid node; the waveform deviation integral circuit obtains compensated waveforms, detects characteristic moments to achieve time domain synchronization, calculates a waveform deviation integral value and dynamically modifies a lookup table mapping relation to form closed-loop feedback. According to the scheme, transient disturbance and normal switching are distinguished through second derivative characteristics, synchronous sampling delay is eliminated through a clock-free architecture, and online self-adaptive optimization of compensation parameters is achieved through closed-loop negative feedback.

The application discloses a kind of downhole fluxgate sensor signal processing methods, the method extracts the magnetic field voltage signal mainly with second harmonic component using signal detection circuit, further eliminates other harmonic components after digital phase-sensitive rectification and smoothing filter algorithm, realizes the effective extraction of magnetic field signal.The extraction effect of phase-sensitive rectification algorithm on second harmonic is verified by time sequence simulation result, and the open-loop fluxgate sensor designed based on second harmonic method is experimented.Compared with other types of fluxgate signal detection methods, second harmonic method effectively improves the resolution, linearity and other key performances of the sensor, and the fluxgate sensor designed based on second harmonic method can realize the detection and effective modulation of the measured magnetic field signal, and shows higher magnetic measuring level.

The application discloses a MOS transistor gate charge balancing method and system of parasitic capacitance charge offsetting logic, and relates to the field of power electronic device driving. The method identifies parasitic capacitance transient disturbance by extracting a second derivative characteristic signal of a gate voltage through a cascade analog differential circuit, triggers asynchronous quantization to generate a digital quantization value when the amplitude exceeds a threshold value, searches a charge compensation control index from a charge compensation lookup table through a clockless asynchronous combination logic retrieval circuit, selectively turns on a current mirror branch of a programmable current mirror array after decoding to apply quantization compensation charge to a gate node, and obtains a compensated waveform through a waveform deviation integration circuit, realizes time domain synchronization when detecting a characteristic moment, calculates a waveform deviation integral value, dynamically modifies a lookup table mapping relationship, and forms a closed loop feedback. The scheme distinguishes transient disturbance from normal switching through a second derivative characteristic, eliminates synchronous sampling delay through a clockless architecture, and realizes online adaptive optimization of compensation parameters through closed loop negative feedback.

An apparatus comprises fetch circuitry configured to fetch instructions for processing by processing circuitry, and prediction circuitry configured to identify instructions to be fetched by the fetch circuitry. The prediction circuitry is configured to perform a lookup in a prediction table based on an address of a first instruction, and in response to the lookup identifying that the prediction table includes a skip-fetch-instruction entry corresponding to the address of the first instruction, the skip-fetch-instruction entry specifying information identifying an operation represented by at least one execute-without-fetch instruction subsequent in program order to the first instruction, the prediction circuitry is configured to control the fetch circuitry to skip fetching of the at least one execute-without-fetch instruction, and control the processing circuitry to perform the operation represented by the at least one execute-without-fetch instruction despite fetching of the at least one execute-without-fetch instruction being skipped.

The application discloses a kind of monolithic three-dimensional integrated differential amplification circuit ion sensing system and preparation method thereof, belong to MEMS technical field, including differential amplification circuit and ion-sensitive field effect transistor, by setting molybdenum disulfide layer in differential amplification circuit, and ion-sensitive field effect transistor is set on molybdenum disulfide layer, through the two ion-sensitive membranes set on two gates synchronous work under differential amplification circuit, one ion-sensitive membrane senses ion signal in the liquid to be measured, another ion-sensitive membrane senses environmental noise, through ion-sensitive field effect transistor and differential amplification circuit, the difference of two end output signals is extracted and amplified, while retaining target ion response signal, environmental noise is inhibited, high-precision, high-sensitivity detection to target ion concentration is realized;And the whole ion sensing system only occupies the area of two FETs, reduces chip plane area, realizes the chip-level miniaturization and high integration of ion sensing system.

A semiconductor device for operating an inductive load, including: a switching element having a control terminal, a low potential terminal and a high potential terminal; a drive circuit configured to apply a control voltage to the control terminal of the switching element to switching-drive the switching element, and operate the inductive load connected to the switching element; an extracting circuit configured to extract control terminal charges from the control terminal of the switching element when the switching element makes a transition from an on state to an off state; and a voltage control circuit connected to a connection point between the low potential terminal of the switching element and the inductive load, the voltage control circuit being configured to clamp a drop in a voltage at the connection point to a predetermined voltage while the extracting circuit is extracting the control terminal charges.

The utility model discloses a novel bit error rate test circuit which comprises an MCU controller, a clock source circuit and a signal shaping circuit. And the MCU controller is connected with the two to realize a control function. The clock source circuit extracts a clock signal and provides a time reference for the signal shaping circuit. The signal shaping circuit is composed of a chip U603, a crystal oscillator Y2, a plurality of capacitors, resistors and the like and can filter input signals in a balanced mode and compensate transmission distortion. In a data transmission and processing system, a stable clock is crucial, so that a chip U603 can accurately sample and process an input signal, and error codes and data loss are avoided. Meanwhile, a resistor (such as R630) and a capacitor (such as C616, C617 and the like) in the circuit form a power supply filtering decoupling network, the power supply voltage is smoothed, the influence of fluctuation on the chip U603 is reduced, and the overall reliability of the circuit is improved.

The invention discloses an ion sensing system of a monolithic three-dimensional integrated differential amplification circuit and a preparation method of the ion sensing system, and belongs to the technical field of MEMS, the ion sensing system comprises a differential amplification circuit and an ion sensitive field effect transistor, a molybdenum disulfide layer is arranged in the differential amplification circuit, and the ion sensitive field effect transistor is arranged on the molybdenum disulfide layer. Two ion sensitive films arranged on two grid electrodes synchronously work under a differential amplification circuit, one ion sensitive film senses ion signals in liquid to be detected, the other ion sensitive film senses environmental noise, and the difference value of output signals at the two ends is extracted and amplified through an ion sensitive field effect transistor and the differential amplification circuit. Environmental noise is suppressed while target ion response signals are reserved, and high-precision and high-sensitivity detection of target ion concentration is realized; and the whole ion sensing system only occupies the area of two FETs, so that the plane area of a chip is reduced, and chip-level miniaturization and high integration of the ion sensing system are realized.

The present invention discloses a 22KHz signal anti-interference tuning and amplifying circuit for a high-frequency head, which includes a tuning and amplifying circuit, a peak detection circuit and a data limiter circuit; the peak detection circuit is connected to the tuning and amplifying circuit, and the peak detection circuit is connected to the data limiter circuit; the signal is input from the tuning and amplifying circuit and output from the data limiter circuit; the tuning and amplifying circuit is used for tuning and amplifying analog signals; the peak detection circuit extracts and holds the peak value of the tuned and amplified signal; the data limiter circuit is used for converting the amplitude-modulated wave envelope signal extracted by the peak detection circuit into a digital signal; this anti-interference tuning and amplifying circuit has the characteristics of using fewer components, improving the anti-noise ability and reducing the error rate in signal conversion.

The invention relates to the technical field of electrical parameter monitoring, and discloses a sparking phenomenon identification processing system based on pulse feature fusion, and the system comprises a signal collection unit which is used for obtaining the voltage and current signals of a controlled loop; the feature preprocessing unit is used for extracting voltage and current change rates by using a hardware differential circuit; the arbitration processing unit is used for acquiring a change rate product through a hardware multiplier so as to generate a correlation signal, separating a high-frequency burr signal by using a high-pass filter circuit, and outputting a sparking identification signal when the correlation signal crosses a negative judgment threshold and the pulse count of the high-frequency burr signal exceeds a random degree threshold; according to the invention, by using the physical difference between the random jump in the discharge process and the smooth characteristic of the controlled switch, the time domain and topology dimension criteria are constructed, the high-frequency power electronic commutation interference is eliminated, the identification time delay is reduced, and the operation safety of the controlled loop is ensured.

The invention relates to a protocol identification circuit, method and device, equipment and a storage medium. The circuit comprises an upstream circuit used for sending a first starting signal to a process control state machine after initialization; the flow control state machine is used for reading the configuration information in the configuration table and sending the configuration information and a second starting signal to the link protocol identification state machine; the link protocol identification state machine is used for configuring the physical layer matching function circuit according to the configuration information, acquiring the feature information extracted by the feature extraction circuit, and sending the feature information to the process control state machine; and the process control state machine is also used for reading the expected characteristics in the detection table under the condition that the characteristic information is received, matching the characteristic information with the expected characteristics, and taking the protocol type corresponding to the expected characteristics as a protocol identification result and sending the protocol identification result to the upstream circuit under the condition that the matching is passed. The protocol identification efficiency can be improved.

The invention discloses a non-contact antenna sensor for monitoring a power electronic switching device. The non-contact antenna sensor comprises an annular antenna, an oscillating circuit and a detection circuit, the change of the current i of the tested power electronic switching device in the switching transient process causes the change of the surrounding magnetic field B, thereby causing the change of the planar magnetic flux phi of the loop antenna, and enabling the two ends of the loop antenna to generate induced electromotive force e. The oscillating circuit outputs oscillating voltage Vosc under the action of the induced electromotive force e; the detection circuit extracts the initial peak value Vp of the oscillation voltage Vosc and maintains the output voltage Vo of the oscillation voltage Vosc at the initial peak value Vp state for a preset time; under the conditions that a commutation loop is not inserted and no contact is generated with a tested system, information of the current change rate of the power electronic switching device at the switching moment is captured, so that state evaluation is carried out on the power electronic switching device, and the device has the advantages of low cost, light size, high integration level, convenience in use and the like.

This invention relates to a single-event latch-up evaluation method for advanced process technologies, comprising: constructing a high-energy particle incident model using the Geant4 Monte Carlo simulation tool; constructing and calibrating a three-dimensional basic device model using the TCAD simulation tool; constructing a standard cell circuit containing parasitic effects, extracting the parasitic thyristor structure of the standard cell circuit, and identifying sensitive regions of the parasitic thyristor structure; performing transient effect simulation on the identified sensitive regions based on the high-energy particle incident model to confirm whether latch-up is triggered; introducing anti-latch-up hardening measures for the sensitive regions, and performing simulation verification on the hardened standard cell circuit under the high-energy particle incident model; if the hardened standard cell circuit does not trigger latch-up, the anti-latch-up hardening measures are deemed effective. This method provides a systematic and automated solution that can fundamentally characterize the complex parasitic effects of advanced devices.