25 results about "Circuit extraction" patented technology

The invention discloses an instruction tamper-proofing device for a traffic information board system, relates to the field of traffic information security, and solves the three technical problems of key clone risk, high computing power dependence and poor environmental adaptability of a traditional encryption scheme. A tamper-proof system is constructed through a triple cooperation mechanism: a unique unclonable physical feature is extracted based on a physical unclonable circuit, efficient integrity verification is realized through a segmented cascade parity check circuit, and a timestamp is accurately compared in combination with a temperature compensation clock; and multi-dimensional features are fused, spliced and integrated, tampering recognition is performed through feature comparison, and ultimate protection is formed if irreversible hardware is triggered to fail if tampering recognition is performed. The device achieves pure hardware millisecond-level response, thoroughly eliminates software dependence, maintains zero misjudgment rate in an extreme environment, ensures full-life-cycle safety of instructions through physical-level protection, and provides unduplicated safety guarantee for an information board system.

This invention relates to a single-event latch-up evaluation method for advanced process technologies, comprising: constructing a high-energy particle incident model using the Geant4 Monte Carlo simulation tool; constructing and calibrating a three-dimensional basic device model using the TCAD simulation tool; constructing a standard cell circuit containing parasitic effects, extracting the parasitic thyristor structure of the standard cell circuit, and identifying sensitive regions of the parasitic thyristor structure; performing transient effect simulation on the identified sensitive regions based on the high-energy particle incident model to confirm whether latch-up is triggered; introducing anti-latch-up hardening measures for the sensitive regions, and performing simulation verification on the hardened standard cell circuit under the high-energy particle incident model; if the hardened standard cell circuit does not trigger latch-up, the anti-latch-up hardening measures are deemed effective. This method provides a systematic and automated solution that can fundamentally characterize the complex parasitic effects of advanced devices.

Systems and methods for controlling valve actuators are provided. The system includes an interface circuit in electrical communication with a wiring connection from a pool / spa control system, and a processor in communication with the interface circuit. The interface circuit extracts a plurality of encoded bits transmitted to the interface circuit from the pool / spa control system over the wiring connection. The plurality of encoded bits could include Manchester-encoded bits that are encoded by the pool / spa control system by altering signals transmitted to the interface circuit over the wiring connection. The processor receives the plurality of encoded bits from the interface circuit and processes the plurality of encoded bits into a control command for controlling operation of the valve actuator. When a valid control command has been generated, the processor executes the control command to operate the valve actuator in accordance with the control command.

The present application relates to the technical field of electric parameter monitoring, and discloses a spark phenomenon identification processing system based on pulse feature fusion, comprising: a signal acquisition unit for acquiring controlled loop voltage and current signals; a feature preprocessing unit for extracting voltage and current change rates by using a hardware differential circuit; an arbitration processing unit for obtaining a change rate product by using a hardware multiplier to generate a correlation signal, and separating a high-frequency burr signal by using a high-pass filter circuit, and outputting a spark identification signal when the correlation signal crosses a negative determination threshold and the high-frequency burr signal pulse count exceeds a randomness threshold; and an output processing unit for executing loop locking according to the spark identification signal, wherein the present application utilizes the physical difference between random jump and smooth characteristics of a controlled switch in the discharge process, constructs time domain and topological dimension criteria, eliminates high-frequency power electronic commutation interference, reduces identification time delay, and guarantees the operation safety of the controlled loop.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

This invention relates to high-frequency amplifiers. A high-frequency amplifier (1) includes: an input terminal P IN Output terminal P OUT ; transistor (5), which is configured to amplify the input terminal P IN The RF signal; a matching circuit (9) and a reflection circuit (7), the matching circuit (9) for the fundamental frequency of the RF signal, and the reflection circuit (7) for the harmonics relative to the fundamental frequency, the matching circuit (9) and the reflection circuit (7) are connected in series between the transistor (5) and the output terminal P. OUT Between; extraction circuit (13), which is configured to extract the output terminal P OUT The harmonics at the point; processing circuits (15, 17) configured to adjust the phase and intensity of the harmonics extracted by the extraction circuit (13); and multiplexing circuit (19) configured to multiplex the harmonics processed by the processing circuits (15, 17) to the harmonics reflected by the reflection circuit (7) and provide the multiplexed harmonics to the transistor (5).

The invention discloses an impedance extraction device and method under magnetic core saturation excitation, and relates to the technical field of electromagnetic compatibility. The device comprises an injection device and an extraction device. The injection device comprises a power amplification circuit, an AC-DC power supply, a signal generator, an MCU control circuit and a current detection circuit, and the extraction device comprises a high-frequency filter circuit, a feed-through capacitor, a first radio frequency current probe, a second radio frequency current probe, a magnetic core clamp, a first high-pass filter, a second radio frequency current probe and a vector network analyzer output end. According to the method, controllable current is applied to the magnetic core through the injection device to enable the magnetic core to be saturated, and meanwhile, the impedance of the magnetic core in a saturated state is extracted on line by utilizing a vector network analyzer and a double-probe method in the extraction device in combination with SOL calibration and a specific impedance calculation formula. According to the method, the impedance of the magnetic core under different saturation degrees can be obtained, the test process is simple, and the sensitivity and operability are high.

The invention discloses an MOS (Metal Oxide Semiconductor) transistor grid charge balancing method and system for parasitic capacitance charge counteracting logic, and relates to the field of power electronic device driving. According to the method, a gate voltage second derivative characteristic signal is extracted through a cascade analog differentiating circuit to identify parasitic capacitance transient disturbance, and asynchronous quantization is triggered to generate a digital quantized value when an amplitude exceeds a threshold value; a clockless asynchronous combinatorial logic retrieval circuit retrieves a charge compensation control index from a charge compensation lookup table; after the programmable current mirror array is decoded, the current mirror branch is selectively conducted, and quantitative compensation charges are applied to a grid node; the waveform deviation integral circuit obtains compensated waveforms, detects characteristic moments to achieve time domain synchronization, calculates a waveform deviation integral value and dynamically modifies a lookup table mapping relation to form closed-loop feedback. According to the scheme, transient disturbance and normal switching are distinguished through second derivative characteristics, synchronous sampling delay is eliminated through a clock-free architecture, and online self-adaptive optimization of compensation parameters is achieved through closed-loop negative feedback.

The application discloses a MOS transistor gate charge balancing method and system of parasitic capacitance charge offsetting logic, and relates to the field of power electronic device driving. The method identifies parasitic capacitance transient disturbance by extracting a second derivative characteristic signal of a gate voltage through a cascade analog differential circuit, triggers asynchronous quantization to generate a digital quantization value when the amplitude exceeds a threshold value, searches a charge compensation control index from a charge compensation lookup table through a clockless asynchronous combination logic retrieval circuit, selectively turns on a current mirror branch of a programmable current mirror array after decoding to apply quantization compensation charge to a gate node, and obtains a compensated waveform through a waveform deviation integration circuit, realizes time domain synchronization when detecting a characteristic moment, calculates a waveform deviation integral value, dynamically modifies a lookup table mapping relationship, and forms a closed loop feedback. The scheme distinguishes transient disturbance from normal switching through a second derivative characteristic, eliminates synchronous sampling delay through a clockless architecture, and realizes online adaptive optimization of compensation parameters through closed loop negative feedback.

The application discloses a kind of monolithic three-dimensional integrated differential amplification circuit ion sensing system and preparation method thereof, belong to MEMS technical field, including differential amplification circuit and ion-sensitive field effect transistor, by setting molybdenum disulfide layer in differential amplification circuit, and ion-sensitive field effect transistor is set on molybdenum disulfide layer, through the two ion-sensitive membranes set on two gates synchronous work under differential amplification circuit, one ion-sensitive membrane senses ion signal in the liquid to be measured, another ion-sensitive membrane senses environmental noise, through ion-sensitive field effect transistor and differential amplification circuit, the difference of two end output signals is extracted and amplified, while retaining target ion response signal, environmental noise is inhibited, high-precision, high-sensitivity detection to target ion concentration is realized;And the whole ion sensing system only occupies the area of two FETs, reduces chip plane area, realizes the chip-level miniaturization and high integration of ion sensing system.

A semiconductor device for operating an inductive load, including: a switching element having a control terminal, a low potential terminal and a high potential terminal; a drive circuit configured to apply a control voltage to the control terminal of the switching element to switching-drive the switching element, and operate the inductive load connected to the switching element; an extracting circuit configured to extract control terminal charges from the control terminal of the switching element when the switching element makes a transition from an on state to an off state; and a voltage control circuit connected to a connection point between the low potential terminal of the switching element and the inductive load, the voltage control circuit being configured to clamp a drop in a voltage at the connection point to a predetermined voltage while the extracting circuit is extracting the control terminal charges.

The utility model discloses a novel bit error rate test circuit which comprises an MCU controller, a clock source circuit and a signal shaping circuit. And the MCU controller is connected with the two to realize a control function. The clock source circuit extracts a clock signal and provides a time reference for the signal shaping circuit. The signal shaping circuit is composed of a chip U603, a crystal oscillator Y2, a plurality of capacitors, resistors and the like and can filter input signals in a balanced mode and compensate transmission distortion. In a data transmission and processing system, a stable clock is crucial, so that a chip U603 can accurately sample and process an input signal, and error codes and data loss are avoided. Meanwhile, a resistor (such as R630) and a capacitor (such as C616, C617 and the like) in the circuit form a power supply filtering decoupling network, the power supply voltage is smoothed, the influence of fluctuation on the chip U603 is reduced, and the overall reliability of the circuit is improved.

The invention discloses an ion sensing system of a monolithic three-dimensional integrated differential amplification circuit and a preparation method of the ion sensing system, and belongs to the technical field of MEMS, the ion sensing system comprises a differential amplification circuit and an ion sensitive field effect transistor, a molybdenum disulfide layer is arranged in the differential amplification circuit, and the ion sensitive field effect transistor is arranged on the molybdenum disulfide layer. Two ion sensitive films arranged on two grid electrodes synchronously work under a differential amplification circuit, one ion sensitive film senses ion signals in liquid to be detected, the other ion sensitive film senses environmental noise, and the difference value of output signals at the two ends is extracted and amplified through an ion sensitive field effect transistor and the differential amplification circuit. Environmental noise is suppressed while target ion response signals are reserved, and high-precision and high-sensitivity detection of target ion concentration is realized; and the whole ion sensing system only occupies the area of two FETs, so that the plane area of a chip is reduced, and chip-level miniaturization and high integration of the ion sensing system are realized.

The invention relates to the technical field of electrical parameter monitoring, and discloses a sparking phenomenon identification processing system based on pulse feature fusion, and the system comprises a signal collection unit which is used for obtaining the voltage and current signals of a controlled loop; the feature preprocessing unit is used for extracting voltage and current change rates by using a hardware differential circuit; the arbitration processing unit is used for acquiring a change rate product through a hardware multiplier so as to generate a correlation signal, separating a high-frequency burr signal by using a high-pass filter circuit, and outputting a sparking identification signal when the correlation signal crosses a negative judgment threshold and the pulse count of the high-frequency burr signal exceeds a random degree threshold; according to the invention, by using the physical difference between the random jump in the discharge process and the smooth characteristic of the controlled switch, the time domain and topology dimension criteria are constructed, the high-frequency power electronic commutation interference is eliminated, the identification time delay is reduced, and the operation safety of the controlled loop is ensured.

The invention relates to a protocol identification circuit, method and device, equipment and a storage medium. The circuit comprises an upstream circuit used for sending a first starting signal to a process control state machine after initialization; the flow control state machine is used for reading the configuration information in the configuration table and sending the configuration information and a second starting signal to the link protocol identification state machine; the link protocol identification state machine is used for configuring the physical layer matching function circuit according to the configuration information, acquiring the feature information extracted by the feature extraction circuit, and sending the feature information to the process control state machine; and the process control state machine is also used for reading the expected characteristics in the detection table under the condition that the characteristic information is received, matching the characteristic information with the expected characteristics, and taking the protocol type corresponding to the expected characteristics as a protocol identification result and sending the protocol identification result to the upstream circuit under the condition that the matching is passed. The protocol identification efficiency can be improved.

The invention discloses a non-contact antenna sensor for monitoring a power electronic switching device. The non-contact antenna sensor comprises an annular antenna, an oscillating circuit and a detection circuit, the change of the current i of the tested power electronic switching device in the switching transient process causes the change of the surrounding magnetic field B, thereby causing the change of the planar magnetic flux phi of the loop antenna, and enabling the two ends of the loop antenna to generate induced electromotive force e. The oscillating circuit outputs oscillating voltage Vosc under the action of the induced electromotive force e; the detection circuit extracts the initial peak value Vp of the oscillation voltage Vosc and maintains the output voltage Vo of the oscillation voltage Vosc at the initial peak value Vp state for a preset time; under the conditions that a commutation loop is not inserted and no contact is generated with a tested system, information of the current change rate of the power electronic switching device at the switching moment is captured, so that state evaluation is carried out on the power electronic switching device, and the device has the advantages of low cost, light size, high integration level, convenience in use and the like.

This invention relates to a single-event latch-up evaluation method for advanced process technologies, comprising: constructing a high-energy particle incident model using the Geant4 Monte Carlo simulation tool; constructing and calibrating a three-dimensional basic device model using the TCAD simulation tool; constructing a standard cell circuit containing parasitic effects, extracting the parasitic thyristor structure of the standard cell circuit, and identifying sensitive regions of the parasitic thyristor structure; performing transient effect simulation on the identified sensitive regions based on the high-energy particle incident model to confirm whether latch-up is triggered; introducing anti-latch-up hardening measures for the sensitive regions, and performing simulation verification on the hardened standard cell circuit under the high-energy particle incident model; if the hardened standard cell circuit does not trigger latch-up, the anti-latch-up hardening measures are deemed effective. This method provides a systematic and automated solution that can fundamentally characterize the complex parasitic effects of advanced devices.

The invention relates to the technical field of gas detection and thermophysical property analysis, in particular to a gas thermophysical property parameter identification method and system based on an MEMS sensor. Comprising the following steps: applying a multi-frequency alternating-current excitation current to a heating element to enable the heating element to generate joule thermal fluctuation with double reference frequency and cause resistance same-frequency fluctuation; extracting a triple frequency output voltage signal through a locking amplification circuit, decomposing the triple frequency output voltage signal into an in-phase component and an orthogonal component through phase-sensitive detection, calculating a plurality of temperature rises, and constructing a plurality of thermal impedance models; calculating a heat conductivity coefficient based on a slope of a real part signal of a complex thermal impedance model along with frequency change, and extracting thermal diffusivity from an imaginary part and phase delay; and finally decoupling and outputting the volumetric specific heat capacity in combination with the correlation model. According to the method, high-precision decoupling of multi-dimensional thermal parameters is realized through triple frequency domain impedance analysis, drift interference is effectively filtered out, and the problem that complex component gas is difficult to accurately identify under a microscale is solved.

This invention discloses a design method for a dual-layer wiring bandpass filter based on SISL. The main steps of this method include: determining the bandpass filter specifications and coupling topology, calculating SISL model parameters, designing the core circuit, extracting key parameter relationships, optimizing structural parameters, fabricating the circuit, and verifying performance. The core of this invention employs a Substrate Integrated Suspended Line (SISL) structure. By integrating air cavities and metallized via arrays within a multilayer dielectric substrate, electromagnetic field energy can be confined to a low-loss cavity region, achieving low transmission loss while providing the advantages of high integration and self-packaging. Furthermore, the core circuit is wired in two layers on the upper and lower metal layers of the same dielectric substrate. Through interlayer vertical cross-coupling and tapped feeding, the frequency selectivity of the filter is effectively improved, achieving both circuit miniaturization and enhanced frequency selectivity. Compared with other types of filters, the dual-layer wiring bandpass filter of this invention offers advantages such as miniaturization, self-packaging, low loss, and high stopband suppression. This design method meets the high integration requirements of modern wireless communication systems, providing a high-performance filter solution for fields such as satellite communication.

The present application relates to the technical field of gas detection and thermal physical analysis, in particular to a gas thermal physical parameter identification method and system based on a MEMS sensor. The method comprises: applying a multi-frequency alternating excitation current to a heating element to make it generate a two-fold reference frequency Joule heat fluctuation and cause a resistance same-frequency fluctuation; extracting a three-fold frequency output voltage signal through a lock-in amplifier circuit, decomposing it into in-phase and quadrature components by using phase-sensitive detection, then calculating a complex temperature rise and constructing a complex thermal impedance model; calculating the thermal conductivity based on the slope of the real part signal of the complex thermal impedance model changing with frequency, extracting the thermal diffusivity from the imaginary part and phase delay; and finally decoupling and outputting the volume specific heat capacity in combination with a correlation model. The present application realizes high-precision decoupling of multi-dimensional thermal parameters through three-fold frequency domain impedance analysis, effectively filters out drift interference, and solves the problem of difficult accurate identification of complex component gases at micro scale.

A boost circuit is arranged to reduce rise and fall times of pulsed power used for pulsed control operation of electric machines. Magnetic energy present in the electric machine at the end of a pulse is extracted by the boost circuit to reduce the pulse fall time. The energy is stored by the boost circuit and then applied at the beginning of a subsequent pulse to reduce the rise time. By reducing rise and fall times compared to not using such a boost circuit, machine efficiency is improved.

The application discloses an instruction tamper-proofing device for a traffic information board system, relates to the field of traffic information security, and solves the three technical problems of key clonable risk, high algorithm dependence and poor environmental adaptability existing in traditional encryption schemes. A tamper-proofing system is constructed through a triple synergy mechanism: unique unclonable physical characteristics are extracted based on a physically unclonable circuit, efficient integrity verification is realized through a segmented cascading parity check circuit, and time stamps are accurately compared in combination with a temperature compensation clock; and multi-dimensional features are fused and integrated, tamper identification is performed through feature comparison, irreversible hardware failure is formed to trigger tamper identification, and ultimate protection is formed. The device achieves a pure hardware millisecond-level response, completely eliminates software dependence, maintains a zero false rejection rate in extreme environments, ensures the safety of the whole life cycle of the instruction through physical-level protection, and provides uncopyable security protection for the information board system.

An example method includes: receiving a target frame and one or more reference frames; extracting a first feature map from a first predicted target frame predicted from a first reference frame, and a second feature map from a second predicted frame predicted from a second target frame, wherein the first predicted target frame is a backward predicted target frame and the second predicted target frame is a forward predicted target frame; generating a refined residual feature based at least on the first feature map, the second feature map, and a third feature map extracted from a feature decoder net module or circuit; generating a frame residual based at least on the refined residual feature; and generating an output reconstructed frame based at least on the frame residual and an average frame, wherein the average frame represents an average of the first predicted target frame and the second predicted target frame.

A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.

This invention discloses an adaptive frequency sweep method, system, and storage medium for piezoelectric ultrasonic transducers, relating to the field of piezoelectric ultrasonic transducer technology. Specifically, it includes: acquiring the initial frequency perturbation step size and the initial perturbation time interval; extracting the inter-bridge voltage signal characterizing the mechanical branch current of the piezoelectric transducer using a bridge circuit and using its effective value as the frequency sweep observation object; applying the rated operating voltage to the piezoelectric transducer and controlling the driving frequency to linearly increase and lock the upper sweep iteration frequency, then controlling the frequency to linearly decrease and lock the lower sweep iteration frequency; determining whether the difference between the two iteration frequencies is less than a preset upper limit of the difference; if not, re-sweeping the frequency according to the difference increase time interval and updating the frequency perturbation step size. This invention aims to improve the transducer's start-up frequency locking accuracy and working efficiency by adaptively adjusting the sweep parameters and accurately selecting the observation object.