117 results about "Parasitic element" patented technology

An antenna comprising an IMD element, and one or more parasitic and active tuning elements is disclosed. The IMD element, when used in combination with the active tuning and parasitic elements, allows antenna operation at multiple resonant frequencies. In addition, the direction of antenna radiation pattern may be arbitrarily rotated in accordance with the parasitic and active tuning elements.

The invention relates to a design method of a 3G (third-generation) antenna of a full-screen intelligent mobile phone and the corresponding antenna. The design method comprises the steps of arranging a high-frequency circuit and a low-frequency circuit of the antenna on a circuit board, wherein the high-frequency circuit and the low-frequency circuit are isolated through an isolating trough, and adjusting the length and the width of the isolating trough to control resonance between the high-frequency circuit and the low-frequency circuit; and arranging a feed point and a ground point, wherein the ground point is arranged on the external side of the feed point, i.e. close to the side of the circuit board; and after an arranged second isolating trough leads out high-frequency second resonance, adjusting the length or the thickness of the second isolating trough to adjust the low-frequency band of the antenna, so as to match with a radio-frequency power amplifier to realize high frequency and high sensitivity. The antenna designed by adopting the design method provided by the invention has the advantages that the volume is small, the performance is excellent and the problem that the low-frequency radiation power and the low-frequency receiving sensitivity of the antenna are decreased because a method of adding a parasitic element to increase bandwidth is adopted can be effectively avoided.

Computer-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least ESD protection circuitry in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the respective ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the netlist evaluated under ESD conditions, the identified ESD devices being removed from the network analysis, the network analysis being used to ensure that current densities through respective conductive connections included in the identified ESD test are less than or equal to a first prescribed threshold, and/or voltage drops associated with the respective conductive connections are less than or equal to a second prescribed threshold.

In a layout data forming step and a layout outputting step after a netlist is read, layout data is formed based on the netlist. In a path sorting step in parallel with these steps, a delay for each path is calculated based on the netlist to compare with a predetermined delay. Only a path having a delay exceeding the predetermined delay is output as a target path to an extraction path file. Then in a parasitic element extracting step, parasitic elements are extracted only from a graphic pattern included in the target path in the layout data while referencing the extraction path file.

The invention relates to an S-waveband communication-in-motion double-frequency circularly polarized micro-strip antenna and an array thereof. The micro-strip antenna includes a metal floor, a dielectric substrate, a radiation metal sheet, a parasitic metal sheet and a micro-strip feeder line, and the micro-strip antenna array includes a metal floor, a dielectric substrate, a radiation metal sheet, a parasitic metal sheet and a micro-strip feed network. The S-waveband double-frequency circularly polarized micro-strip antenna and the array thereof introduces the parasitic element on the basis of a traditional double-fed circularly polarized micro-strip antenna and an array thereof, thereby greatly expanding the working bandwidth, and enabling excellent impedance characteristic and radiation characteristic to be realized in a double-frequency-band range of uplink 1.98 to 2.01 GHz and downlink 2.17 to 2.20 GHz of an S waveband.

A loop antenna includes a parasitic element arranged at a position almost concentric to a loop element and having an opening portion smaller than the half perimeter of the loop element at a position opposite to the feeding point of the loop element.

An antenna device includes a ground electrode, a feed element, and a parasitic element. The ground electrode has a substantially non-square rectangular plane shape that includes a first side extending in a first direction and a second side extending in a second direction orthogonal to the first direction. The feed element has a substantially rectangular plane shape and is formed in such a way that each side of the feed element becomes parallel to the first direction or the second direction. The parasitic element is formed in such a manner as to face a side of the feed element parallel to the first side. The feed element is configured to radiate a first polarized wave that excites in the first direction and a second polarized wave that excites in the second direction. The length of the first side is longer than the length of the second side.

A feeding element is disposed on or in a first substrate. A second substrate overlies the feeding element. The second substrate is a flexible substrate including an extending portion extending outside the first substrate. A parasitic element coupled to the feeding element is disposed on or in the second substrate. A radiating electrode connected to the parasitic element is disposed on the extending portion of the second substrate.

A patch antenna device configured to receive a radio communication signal includes a circuit board, a patch antenna, and a parasitic element. The circuit board has a signal processing circuit placed thereon. The patch antenna is stacked on the circuit board and has a quadrangular radiation element. The parasitic element is disposed above the patch antenna so as to improve antenna gain characteristics of the patch antenna and configured such that the length of the upper side of the parasitic element is shorter than the width in a plan view of the radiation element of the patch antenna and that the length between the upper and lower sides of the parasitic element is longer than the length between the upper and lower sides of the radiation element of the patch antenna.

The invention discloses a modeling method of an MOS device, and the method comprises the following steps: S01, constructing a model circuit of the MOS device, wherein the model circuit comprises an intrinsic transistor, a substrate parasitic resistor, a parasitic capacitor, a parasitic diode, a grid parasitic resistor inductance network, a source parasitic resistor inductance network and a drain parasitic resistor inductance network; S02, determining models and size parameters of an intrinsic transistor and a parasitic diode in the model circuit; S03, respectively determining parasitic elementvalues of the source parasitic resistance inductance network and the drain parasitic resistance inductance network by adopting an electromagnetic simulation method; S04, determining parasitic elementvalues of the substrate parasitic resistance, parasitic capacitance and grid parasitic resistance inductance network based on the test data; and S05, substituting the calculated parasitic element value into the model circuit. The model circuit comprises the parasitic resistance inductance network of each connection path, and the model is wider in application range and can be suitable for millimeter waves and other frequency bands.

An antenna includes a dielectric substrate, a radiating element, a parasitic element, and a ground conductor. The dielectric substrate has a plate-like shape having a top face and a back face opposite to each other. The radiating element is placed between the top face and the back face of the dielectric substrate and transmits and receives a radio frequency signal of a first frequency. The parasitic element is placed on the top face of the dielectric substrate and transmits and receives a radio frequency signal of a second frequency. The ground conductor is placed on the back face of the dielectric substrate. The second frequency is a lower frequency than the first frequency. The dielectric substrate has an electric field boundary plane that reflects a radio frequency signal of the second frequency at an intermediate position in a thickness direction orthogonal to the top face and the back face.

A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180°×N−90° where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180°×M−180° where M is a positive integer.

The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

The invention relates to wideband radiating elements including parasitic elements and related base station antennas. A radiating element for a base station antenna includes a first dipole radiator that has a first dipole arm that has a front surface and first and second extensions that project rearward from respective side edges of the front surface of the first dipole arm; a second dipole radiator that has a second dipole arm that has a front surface and first and second extensions that project rearward from respective side edges of the front surface of the second dipole arm; and a parasiticelement having a first conductive segment that is configured to capacitively couple to the first extension of the first dipole arm, a second conductive segment that is configured to capacitively couple to the second extension of the second dipole arm, and a third conductive segment that electrically connects the first conductive segment to the second conductive segment.

The embodiment of the invention discloses a filter circuit for generating an extra transmission zero point and a filter, and the filter circuit comprises a parallel resonance generation unit which isused for generating resonance, the parallel resonance unit comprises a first branch connected between an input port and an output port, a second branch and a third branch, a first end of the second branch is connected with a first end of the first branch, a first end of the third branch is connected with a second end of the first branch, a second end of the second branch is connected with a secondend of the third branch and grounded, the second branch and the third branch are connected with inductors in series or capacitors in series, and a parasitic element exists between a common connectionpoint of a second end of the second branch and a second end of the third branch and the ground. By utilizing parasitic parameters of the parasitic element, an extra transmission zero point can be generated on the premise of not increasing extra devices, the suppression degree of the filter is improved, the device cost is reduced, and the occupied space is reduced.

The invention provides a simulation method and device, a power line topology network, a test circuit and a storage medium. The method comprises the steps that a power line topology network is generated according to a power line layout, the power line topology network comprises a plurality of first-layer metal wires which are transversely arranged, a plurality of second-layer metal wires which are longitudinally arranged, power supply child nodes and parasitic elements, and the parasitic elements are located between the two power supply child nodes; the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power line topology network is determined, the power input node is one of power child nodes in each circuit module, and time sequence simulation is carried out according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist. Therefore, the influence of the voltage drop of the power line on the time sequence parameters of the integrated circuit can be evaluated through normal time sequence simulation, and the simulation precision and the simulation speed are improved.