169results about "Amplitude-modulated pulse demodulation" patented technology

Aspects of a method and system for low power IDLE signal transmission in Ethernet networks are provided. In this regard, during time periods between transmissions of actual data by a local Ethernet link partner, the local Ethernet Link partner may generate one or more signals, in place of a standard Ethernet IDLE signal, that enable synchronization between Ethernet link partners. In this manner, the generated signals may enable reducing power consumption as compared to standard Ethernet IDLE signals. Accordingly, link activity may be monitored to enable detecting periods when there may be no actual data for transmission and the generated signals may be transmitted. The generated signals may be transmitted at a reduced symbol rate as compared to standard Ethernet IDLE signals. The generated signals may be transmitted via fewer network links as compared to standard Ethernet IDLE signals.

Systems (400, 500, 600) and methods (300) for generating a chaotic amplitude modulated signal absent of cyclostationary features by preserving a constant variance. The methods involve: generating a PAM signal including pulse amplitude modulation having a periodically changing amplitude; generating a first part of a constant power envelope signal (FPCPES) by dividing the PAM signal by a square root of a magnitude of the PAM signal; generating a second part of the constant power envelope signal (SPCPES) having a magnitude equal to a square root of one minus the magnitude of the PAM signal; and generating first and second spreading sequences (FSS and SSS). The methods also involve combining the FPCPES with the FSS to generate a first product signal (FPS) and combining the SPCPES with the SSS to generate a second product signal (SPS). A constant power envelope signal is generated using the FPS and SPS.

Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols in constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N−1 comparators for comparing an input data stream to N−1 configurable thresholds, the input data stream is N-PAM modulated and the N−1 configurable thresholds are N−1 different voltage levels; a number of N−1 of edge detectors respectively connected to the N−1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.

A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling system. Such a method comprises determining a coding gain for each of a plurality of transition-limiting codes, and selecting one of the plurality of transition-limiting codes having a largest coding gain for use in the multi-level signaling system.

In a modulation system, in order to provide a two-level signal with a desired modulation which is suited to be amplified by a switching mode power amplifier, the modulation system may include a first constant envelope modulator modulating a signal according to a first control signal, a second constant envelope modulator modulating a signal according to a second control signal, and a combining portion combining the output signal of the first and said second constant envelope modulator to a single, two-level pulse-width-modulated signal. The information which is to be represented by the modulation of the single, two-level pulse-width-modulated signal is coded in the first and the second control signals. The invention relates equally to a corresponding method for generating a modulated signal.

Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase. Information from the non-mid-amplitude edge slicers and phase detectors is used to choose a phase from among the phase variants that best suits the other data slicers. In yet another implementation, a single edge slicer, single phase detector, and single VCO is used to generate a key clock which is used by the edge slicer to track the symbol timing. A clock generator provides a single optimized clock (that is offset from the key clock) that is used by the data slicers. Bit error rates from the data slicers are used to adjust the offset until the data slicer clock is optimized with respect to all the slicers. Alternatively, multiple clocks are generated via offsets from the key clock, each being optimized to the data slicer group that it drives.

Methods and apparatuses for minimizing co-channel interference in communications systems are disclosed. A method in accordance with the present invention comprises scrambling a first frame using a first scrambling code, attaching a first header to the first frame to create the first signal, scrambling a second frame using a second scrambling code, attaching a second header to the second frame to create the second signal, and transmitting the first signal and the second signal over different channels of the communication system.

A method for transmitting at least a synchronization and a data signal on a single-wire bus between a master device and at least one slave device, wherein a first transmission channel from the master device to the slave device modulates the periodic pulse width between a first level and second level of a same sign voltage relative to a reference potential, and a second transmission channel amplitude modulates at least one of the voltage levels between the level and at least one third level different from the two others and from the reference potential.

A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.

Based on a received signal y(t) received by a radiating element of an array antenna including the single radiating element and a plurality of parasitic elements, an adaptive controller calculates and sets a reactance value of a variable reactance element for directing a main beam of the array antenna in a direction of a desired wave and directing nulls in directions of interference waves so that a value of an objective function expressed by only the received signal y(t) becomes either one of the maximum and the minimum by using an iterative numerical solution of a nonlinear programming method.

A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth clock waveform ranging in phase from zero (0) to 32pi radians. An interpolator detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length, and a phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2pi radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length, and the phase detector measures a second phase increment when the second zero-crossing transition is detected. An accumulated phase difference is calculated by subtracting the initialized first phase increment from the measured second phase increment. The pulse run length is then obtained by dividing the accumulated phase difference by 2pi.

A demodulator for demodulating an amplified shift keyed (ASK) signal includes an envelope detector generating an envelope signal, a low-pass filter generating a filtered envelope signal, a switch coupled to disengage the low-pass filter in response to a first control signal, a comparator with hysteresis comparing the envelope signal and the filtered envelope signal. In operation, the switch is open or close in response to the first control signal to cause the demodulator to operate in one of multiple operation modes. In one operation mode, the demodulator uses a small capacitor to form a low-pass filter having a cut-off frequency equal to or greater than the bit-rate of the ASK signal and the demodulator receives an ASK signal having any coding pattern, including ASK signals having unequal number of 1's and 0's.

In accordance with an embodiment, a method of operating a base station configured to operate with user devices includes scheduling a first user device in a first slot, scheduling the first user device for at least one further slot, and transmitting an assignment for the at least one further slot to the first user device. The first slot has a first resource block (RB) and a first transmission time interval (TTI) and the at least one further slot has the first RB and a second TTI.

A method and apparatus is disclosed for facilitating high-speed data communication. In one embodiment a receiver is configured to include error correction coding in an interleaved environment to increase data transmission rates. In one embodiment the signal mapping scheme includes constellation shaping to reduce transmit power levels. In one embodiment 8-state Ungerboeck trellis coding is implemented with 4-dimensional PAM 10 signal mapping.

Embodiments of the present invention include a method for performing joint time synchronization and carrier frequency offset estimation in a wireless communication system, comprising steps of: on a transmitter: performing frequency domain spreading and interleaving on input data by using a predetermined spreading factor (SF) to generate a frequency domain training symbol; performing Inverse Discrete Fourier Transformation (IDFT) on the generated frequency domain training symbol to generate a first time domain training symbol; reversely copying the generated first time domain training symbol to a second time domain training symbol such that a complete training sequence is formed; and on a receiver: detecting an average power of received signals to judge the coming of a training sequence, and performing coarse frame synchronization; performing joint fine frame synchronization and carrier frequency offset estimation based on a received training sequence; and compensating for the carrier frequency offset based on the carrier frequency offset estimation result so as to eliminate the carrier frequency offset. In addition, embodiments of the present invention also include an apparatus for performing joint time synchronization and carrier frequency offset estimation and a method for generating a training sequence.

An optical processor for controlling a phased antenna array uses a frequency-shifted feedback cavity (FSFC), which includes a traveling-wave cavity. The FSFC incrementally delays and incrementally frequency shifts optical signals circulating in the traveling-wave cavity. Optical signals coupled out of the FSFC are separated by frequency, hence by delay, and processed to control either or both transmit and receive beam-forming operations. The FSFC provides a receiver with multiple receive signals which have incremental values of frequency. Each frequency corresponds to an incremental time sampling of optical signals input into the FSFC. Transmit signals coupled out of the FSFC have frequency and phase relationships that result in short time-domain pulses when combined. Controlling modulation and frequency of the transmit signals achieves carrier interference multiple access, a new type of spread-spectrum communications.

The present invention has many aspects. One aspect of the invention is to perform equalization using a sliding window approach. A second aspect reuses information derived for each window for use by a subsequent window. A third aspect utilizes a discrete Fourier transform based approach for the equalization. A fourth aspect relates to handling oversampling of the received signals and channel responses. A fifth aspect relates to handling multiple reception antennas. A sixth embodiment relates to handling both oversampling and multiple reception antennas.

An Apparatus for non-linear per-bin adaptive equalization in orthogonal multi-carrier data transmission systems with the Nyquist sub-channel spectral shaping and T/2 staggering of in-phase and quadrature components is disclosed. A previously introduced linear equalization embodiments are augmented by up to three, or more decision feed-back filters, to improve performance in presence of narrow-band interference (NBI) in wire-line and wire-less data transmission systems, and to enable exploitation of implicit diversity of multi-path fading channels, both with and without transmitter-end pre-coding. Adaptation properties of per-bin DFE equalization are analyzed by computer simulation for an intermediate number of constituent sub-channels. BER performance comparison between the conventional Orthogonal Frequency Division Multiplication-(OFDM) and (Orthogonal Quadrature Amplitude Modulation (OQAM)-based multi-carrier systems of similar modulation/demodulation complexity and transmission latency is provided and the potential advantage of using spectrally well shaped orthogonal sub-channels in wireless applications is demonstrated.

In one embodiment a method includes, collecting in-phase/quadrature (I/Q) data representing energy detected by a radio in a frequency band, performing a fast Fourier transform (FFT) on the I/Q data resulting in a stream of FFT blocks, identifying using the stream of FFT blocks a pulse in the frequency band, recording in a radio events record (RER) a plurality of radio events and corresponding timestamps that are indicative, respectively, of a type and time of individual state changes in the radio during the collecting step, and, for example, using at least two of the radio events to identify, in the time domain, a beginning time and end time of the pulse detected in the stream of FFT blocks.

The present invention is directed to communication systems. More specifically, embodiments of the present invention provide a technique and system thereof for performing eye modulation. Eye modulation is performed at the transmission side of a PAM communication system to compensate for distortion and non-linearity and generate an output waveform. Spacing among eye levels is adjusted by performing symmetric modulation using α parameter and asymmetric modulation using β parameter. A correction module measures the output waveform and sends feedback signals to a control module to adjust the α parameter and the β parameter. There are other embodiments as well.