9results about "Amplitude-modulated pulse demodulation" patented technology

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

An isolator according to one embodiment includes: a ΔΣ modulation analog-to-digital converter converts the input analog signal into a digital data signal of a pulse train corresponding to the amplitude of the input analog signal, and outputs the digital data signal; an attribute signal detection circuit detects an attribute of the input analog signal and outputs input attribute information related to the attribute of the input analog signal; a high speed feedback encoder encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder outputs a second encoded signal; an insulated transmission circuit outputs a transmission signal transmitted through the insulation unit in response to the second encoded signal; and a demodulation circuit outputs a demodulated digital data signal obtained by demodulating the second encoded signal and / or the input attribute information, based on the transmission signal.

The embodiment of the invention provides an isolator capable of realizing low power consumption and reducing delay of signal transmission. An isolator according to an embodiment includes: a [delta] [sigma] modulation analog-to-digital converter that converts a digital data signal of a pulse train corresponding to an amplitude of an input analog signal and outputs the digital data signal; an attribute signal detection circuit that outputs input attribute information relating to an attribute of the input analog signal; a high-speed feedback encoder which encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder which performs edge encoding on the first encoding signal and outputs a second encoding signal; an insulated transmission circuit that outputs a transmission signal transmitted through the insulating portion in accordance with the second encoded signal; and a demodulation circuit that, on the basis of the transmission signal, outputs a demodulated digital data signal obtained by demodulating the digital data signal and / or outputs demodulated attribute information obtained by demodulating the input attribute information.

The application belongs to the field of integrated circuits, and discloses a polarity pulse modulation and demodulation circuit applied to isolated communication, which comprises a first delay circuit, a second delay circuit, an AND gate, a NOT gate, a pulse driving circuit, a transformer, a pulse detection circuit and an SR flip-flop; the first input end of the AND gate is connected with the output end of the first delay circuit, the second input end is used for inputting a digital signal, and the output end is connected with the pulse driving circuit; the first input end of the NOT gate is connected with the output end of the second delay circuit, the second input end is used for inputting an input signal, and the output end is connected with the pulse driving circuit; the primary side of the transformer is connected with the pulse driving circuit, and the secondary side is connected with the pulse detection circuit and the SR flip-flop in sequence. The delay circuit has the characteristics of stable delay time, which guarantees the certainty of the pulse width of the transmitted pulse signal, and then the pulse amplitude of the pulse signal is controlled through the pulse driving circuit, so that the pulse signal can realize long communication distance in a typical twisted pair line.

The invention relates to a circuit for transmitting serial LED signals. The circuit comprises a modulation module and a demodulation module. The modulation module is provided with R1, R2, Q1-Q3, the drain electrode of Q1 is connected with the drain electrode of Q2, the drain electrode of Q3 is a modulation output end, the grid electrode is a first input end, and the source electrode is grounded; the grid electrode of Q2 is a second input end, and the source electrode is connected with R1; the grid electrode of Q3 is connected with the output end of U1 and the source electrode is connected with R2; the input end of U1 is connected with the second input end; the R1 is connected with the V1, and the R2 is connected with the V2. The demodulation module is provided with U2, U3, U4 and an external timing circuit; the input end of the U2 is connected with a modulation output end, and the output end of the U2 is a first demodulation output end; the in-phase end of the U3 is connected with the modulation output end, the anti-phase end is connected with the V3, and the output end is connected with the input end of the U4; the output end of the U4 is a second demodulation output end, and the external timing circuit is connected with the U4. The circuit integrates LED clock and data signals, breaks through the limitation of double signal lines, adapts to the working condition of resource shortage, is simple and easy to produce, reduces cost, ensures stable transmission of signals, ensures normal display of indicator lamps, and improves flexibility.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

The invention relates to an integrated circuit for conditioning an oscillating analog signal comprising a succession of damped oscillations, the integrated circuit comprising an input / output (IO) cell having: - a first port (PAD) configured to receive said oscillating analog signal, called input signal, - a second port (ANA) configured to deliver an analog output signal from the input signal, - control means coupled between the first port and the second port and configured to suppress at least the first oscillation from the input signal so as to deliver in the output signal oscillations of the input signal having an amplitude less than a first threshold.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives, from a processor, a bitstream including a given symbol to be transmitted on a first channel of a plurality of channels according to pulse-amplitude modulation (PAM), and transmits the given symbol to the first channel of the plurality of channels according to the PAM. A plurality of channels connect the transmitter module to a memory module in an integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk on the first channel from other channels. The parameter is identified based on a pending transition of the signal level in each other channel. The transmitter module superimposes parameters of other channels on a given symbol to adjust the given symbol on the first channel. A digital-to-analog converter (digital-to-analog converter, for short, DAC) on the first channel generates an analog output to the memory module. The analog output represents the adjusted given symbol.