58results about "Pulse amplitude modulation" patented technology

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

The invention discloses a nanosecond steep pulse excitation system and a nanosecond steep pulse excitation method. The nanosecond steep pulse excitation system comprises a high-voltage pulse generation module, a controller, an impedance detection module and a treatment electrode, the high-voltage pulse generation module is used for receiving a control signal monitored by the controller and outputting a high-voltage pulse to the treatment electrode; the impedance detection module comprises a measuring electrode, tissue impedance data are collected through the measuring electrode, and the impedance data are dynamically fed back to the controller; the controller dynamically adjusts parameters of the high-voltage pulse generation module according to impedance data to form closed-loop control, the Marx circuit is optimized, the high-voltage pulse generation efficiency is high, nanosecond-level accurate triggering is achieved through embedded control, effective deposition of high-frequency energy is ensured, transient voltage spikes are reduced, impedance changes are detected in real time through the impedance detection module, and the control precision is improved. The pulse width or amplitude is dynamically adjusted, pulse parameters are adjusted in real time based on impedance changes, and excessive ablation or insufficient treatment is avoided.

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input / output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.

A pulse amplitude modulation transition density trigger in a test and measurement instrument is provided. A test and measurement instrument comprises: an input for receiving a pulse amplitude modulated n-level (PAMn) signal; an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal; an acquisition memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform; a trigger circuit coupled to the ADC and the acquisition memory and configured to generate a trigger signal to cause the test and measurement instrument to trigger acquisition of waveforms; a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal; and a conversion detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit, and configured to detect a symbol conversion based on the decoded bits, and to cause the trigger circuit to generate a trigger signal in response to detecting a particular symbol conversion.

In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.

Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels. The transmitter includes a first driver which processes most significant bits and a second driver which processes least significant bits, in the PAM3 mode. In the NRZ mode, the second driver is turned off but resistances in the second driver are used to optimize impedance in the first driver. Switches can be turned on to couple in resistors in the first driver with resistors in the second driver, for pairs of driver slices. The switches are turned off in the PAM3 mode.

Implementations of the present disclosure relate to a system comprising an access point (AP) and a USB device operating at the same frequency as the AP. The USB device may modulate a plurality of time-sensitive signals into a current pulse amplitude modulation (PAM) signal, and a plurality of different amplitudes in the current PAM signal is associated with occurrence of high level of a plurality of different combinations of time-sensitive signals in the plurality of time-sensitive signals. That is to say, when high level occurs in different numbers of time-sensitive signals, the modulated current PAM signal will have different power levels. Accordingly, the AP comprises a decoder for demodulating the current PAM signal to obtain a digital signal representing one or more time-sensitive signals transmitted from the USB device to the AP, thereby enabling the transmission of multiple time-sensitive signals from the USB device to the AP.

Method for encoding a signal to be transmitted via a communication channel, comprising: Receiving a signal to be transmitted; Converting the signal into a converted analog signal using a digital-to-analog converter; Receiving channel status information for a channel; Calibrating a lookup table based on channel state information; Using the calibrated lookup table to generate a coded analog signal based on the converted signal; and Transmitting the encoded analog signal, whereby the encoded signal compensates for channel distortions.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

A system and method for distortion reduction. In some embodiments, a system for distortion reduction includes a transmitter comprising pulse amplitude modulation driver circuitry. The pulse amplitude modulation driver circuitry may include a main driver comprising a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier. The LSB amplifiers may include an upper arm and a lower arm, the strength of which is adjustable.

A pDBI encoding method comprising: generating sequence data; grouping the sequence data according to a predetermined burst length; generating process sequence data and pDBI (partial-Data Bus Inversion) based on the grouped sequence data; and generating PAM3 (3-level pulse amplitude modulation) output data based on the process sequence data and the pDBI.

The invention discloses a square wave pulse generator and a square wave pulse generation method, in the scheme, a pulse data memory stores parameter data of a square wave pulse sequence to be output; the square-wave pulse generation module responds to an instruction of an upper computer to read parameter data of a to-be-output square-wave pulse sequence stored in a pulse data memory, distributes the parameter data to a plurality of pulse transmission channels for processing to obtain a plurality of seed square-wave pulse sequences and transmits the seed square-wave pulse sequences to the corresponding pulse amplitude adjusting modules respectively; the pulse amplitude adjusting module performs waveform adjustment on each seed square wave pulse sequence to obtain an intermediate square wave pulse sequence and transmits the intermediate square wave pulse sequence to the corresponding master-slave pulse driving module; and the master-slave pulse driving module performs voltage gain and current gain on the intermediate square wave pulse sequence to obtain a square wave pulse sequence to be output. Compared with the prior art that performance limitation still exists in the aspects of voltage range, current driving capability, delay precision or sequence flexibility and the like, the method has obvious advantages.

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input / output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

To provide a differential interface circuit capable of receiving a multiple-value PAM signal accurately.SOLUTION: A first stage 420_1 of a differential interface circuit 400A includes a first transistor MN11, a second transistor MN12, a third transistor MN13, and a fourth transistor MN14. Gates of the first transistor MN11 and the second transistor MN12 are connected to input terminals INP, INN. The third transistor MN13 and the fourth transistor MN14 are connected in parallel to the first transistor MN11 and the second transistor MN12. A gate of the third transistor MN13 is connected to a drain of the second transistor MN12, and a gate of the fourth transistor MN14 is connected to a drain of the first transistor MN11.SELECTED DRAWING: Figure 3

The invention discloses a data encoding method, a data decoding method, a data encoding device, data decoding equipment, and a storage medium, and belongs to the technical field of communication. The method comprises the steps of obtaining a first data segment; a plurality of basic code blocks are obtained, the basic code blocks are composed of a first code block set and a second code block set, and the minimum code block distance between any basic code block in the first code block set and other code blocks in the basic code blocks is larger than the minimum Euclidean distance of PAM, the minimum code block distance between any basic code block in the second code block set and other code blocks in the multiple basic code blocks is equal to the minimum Euclidean distance, and the number of the basic code blocks in the first code block set is larger than that of the basic code blocks in the second code block set; and encoding the first data segment according to the plurality of basic code blocks. As the code block distance between any basic code block in the first code block set and other code blocks is greater than the minimum Euclidean distance, the basic code blocks in the first code block set are used for coding, and additional coding gain can be generated.

The utility model provides a radio frequency signal AM modulation and signal amplification integrated circuit. The radio frequency signal AM modulation and signal amplification integrated circuit comprises a carrier signal input end, a to-be-modulated radio frequency signal input end, a modulation amplification output end, a pulse sampling module, a radio frequency tube and an operational amplifier module used for inputting bias voltage to the radio frequency tube. The carrier signal input end is connected with the input end of the radio frequency tube; a to-be-modulated radio frequency signal input end is connected with the pulse sampling module, and the pulse sampling module is connected with an input end of the radio frequency tube through the operational amplifier module. The output end of the radio frequency tube is connected with the modulation amplification output end. The circuit can realize the integration of AM modulation and amplification, saves the volume space, can save the circuit power consumption when the radio frequency signal to be modulated is low in amplitude, and does not need to keep the bias voltage and power consumption under the peak amplitude all the time like a traditional AM modulation amplifier, thereby reducing the average power consumption.

A signal processing arrangement generates optical stimulation signals to optical stimulation contacts in an implanted cochlear implant array. An input sound signal is transformed into band pass signals that each represent an associated band of audio frequencies, with each band pass signal includes an envelope component characterizing loudness of the band pass signal, and a fine structure component characterizing temporal details of the band pass signal. One or more of the signal components of each band pass signal is half wave rectified to remove negative phase signals. Signal slope is determined that corresponds to rate of change of the rectified one or more signal components. Then constant-rate optical stimulation pulses are generated for one or more given band signals only when the rectified one or more signal components has a positive signal slope.

A method for recovering a clock signal from a data signal by using a clock recovery module (10) is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module (10) is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module (10) as well as a computer program (32) are described.

A system and method for distortion mitigation. In some embodiments, a system, includes: a transmitter, including: a pulse amplitude modulation driver circuit. The pulse amplitude modulation driver circuit may include a main driver including a most significant bit (MSB) amplifier, and a least significant bit (LSB) amplifier. The LSB amplifier may include an upper arm and a lower arm, a strength of the upper arm or a strength of the lower arm being adjustable.

The invention relates to the technical field of pulse technology, PAM code pattern generation and the like, and provides a PAM code pattern generation method based on AWG, which comprises the following steps of: receiving an M-system digital code element sequence, storing a current code element N and a previous code element L in real time, and calculating a state difference value to judge level transition; generating a phase value xphase under the driving of a sampling clock, reading a pre-stored standard rising edge waveform rise (xphase) by an index waveform lookup table, and dynamically calculating a current PAM amplitude according to a formula (N-L) * rise (xphase) + L * A; the amplitude is converted into an analog signal through a DAC after linear transformation, then denoising is carried out, and the level is adjusted to a standard range. According to the method, traditional transition waveform pre-storage is replaced by phase accumulation and a general state formula, the problems of high storage resource consumption, waveform jitter and poor expansibility are solved, and hardware resources are saved; sampling clock jitter is eliminated, and the bit error rate is reduced; pAM order seamless switching and architecture multiplexing are supported; the adjustable edge time is matched with the dynamic level, and the signal amplitude consistency is improved.

The application belongs to the field of integrated circuits, and discloses a polarity pulse modulation and demodulation circuit applied to isolated communication, which comprises a first delay circuit, a second delay circuit, an AND gate, a NOT gate, a pulse driving circuit, a transformer, a pulse detection circuit and an SR flip-flop; the first input end of the AND gate is connected with the output end of the first delay circuit, the second input end is used for inputting a digital signal, and the output end is connected with the pulse driving circuit; the first input end of the NOT gate is connected with the output end of the second delay circuit, the second input end is used for inputting an input signal, and the output end is connected with the pulse driving circuit; the primary side of the transformer is connected with the pulse driving circuit, and the secondary side is connected with the pulse detection circuit and the SR flip-flop in sequence. The delay circuit has the characteristics of stable delay time, which guarantees the certainty of the pulse width of the transmitted pulse signal, and then the pulse amplitude of the pulse signal is controlled through the pulse driving circuit, so that the pulse signal can realize long communication distance in a typical twisted pair line.

A ramp drive is disclosed. The ramp driver comprises: a ramp generator for generating a reference ramp signal and comprising a resistor string, the resistor string comprising: a first end for receiving a high ramp voltage; the second end is used for receiving the low-ramp voltage; and a ramp retarder for sequentially outputting the reference ramp signal. The ramp generator is configured to: divide a difference between a high ramp voltage and a low ramp voltage into first to k-th voltages by using a resistor string; and sequentially outputting the first to kth voltages to generate a reference ramp signal, where k is a positive integer.

A high-frequency power supply (10) uses one pulse conversion / variable gain amplification unit (23) to perform two processing steps which are converting an RF signal into pulses and controlling an output level, and uses one control signal (27) to perform the pulse conversion and the output level control by the pulse conversion / variable gain amplification unit (23), thereby obviating the need for a modulation unit, which is a factor in the generation of jitter, overshoot, and undershoot, and reducing the number of control lines (29) for sending the control signal (27) to one control line. Due to this configuration, the jitter, overshoot, and undershoot generated in an RF pulse signal can be prevented, and the RF-signal pulse conversion and output level control are performed simultaneously using one control line (29).

The application discloses a multi-level output driving circuit and method. The circuit comprises a signal selection module configured to select a to-be-transmitted signal of a corresponding channel according to an externally input signal; a weight generation module configured to generate weight data according to the weight of an output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data; a coefficient transmission module configured to perform weight control on the to-be-transmitted signal according to the weight data to generate data containing weight information; and a weight adjustment and data output module configured to perform weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the to-be-transmitted signal and the data containing weight information to generate four-level pulse amplitude modulation data PAM4. Compared with the prior art, the embodiment of the application enriches the mode of eye diagram adjustment and can be applied to eye diagram misadjustment caused by different transmission environments.

A Light Detection And Ranging (LIDAR) measurement circuit includes a control circuit configured to receive respective detection signals output from one or more single-photon detectors in response to a plurality of photons incident thereon. The control circuit includes a photon counter circuit including a digital counter circuit and an analog counter circuit, the digital counter circuit being responsive to an output of the analog counter circuit or the analog counter circuit being responsive to an output of the digital counter circuit to count detection of respective photons of the plurality of photons based on the respective detection signals, and a time integration circuit configured to output a time integration signal representative of respective times of arrival indicated by the respective detection signals. The control circuit is configured to calculate an estimated time of arrival of the plurality of photons based on a ratio of the time integration signal and the count of the detection of the respective photons of the plurality of photons.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

Device comprising the following: a first set of amplitude filters (210A) comprising input terminals for receiving a first input signal, wherein the first set of amplitude filters (210A) is configured to generate a first amplitude filter output signal comprising outputs of the first set of amplitude filters (210A), wherein the first amplitude filter output signal digitally indicates a level of the first input signal; a first speculative tap (220A) which includes input terminals coupled to output terminals of the first set of amplitude sieves (210A) for receiving the first amplitude sieve output signal, control terminals for receiving an output of a second speculative tap (220B) and output terminals for outputting an output of the first speculative tap (220A), wherein the first speculative tap (220A) is configured to select outputs of a subset of the first set of amplitude sieves (210A) based on the output of the second speculative tap (220B) received at the control terminals; a first decoder (230A) comprising input terminals coupled to the output terminals of the first speculative tap (220A), wherein the first decoder (230A) is configured to decode the selected outputs of the subset of the first set of amplitude sieves (210A), present in a first digital representation, into a second digital representation; and a first feedback generator comprising the following: Input terminals coupled to the output terminals of the first decoder (230A) and Output terminals coupled to the input terminals of the first set of amplitude filters (210A), wherein the first feedback generator is configured to generate a first feedback signal according to the decoded outputs of the subset of the first set of amplitude filters (210A) and outputs the first feedback signal at its output terminals.