A circuit (20A) for decoding a
pulse width modulated signal (PWM) comprises an input node (200) configured to receive the
pulse width modulated signal (PWM), and an output node (202) configured to provide an output
signal (DATA) switching between a first output value and a second output value as a function of the duty-cycle of the input
pulse width modulated signal (PWM). A current generating circuitry (22) is coupled between a supply
voltage node (Vdd) and a ground
voltage node (GND) . The current generating circuitry is coupled to the input node (200) to receive the input pulse width modulated signal (PWM) and is coupled to an intermediate node (204) of the circuit to inject a current (IH) therein or to sink a current (IL) therefrom as a function of the value of the input pulse width modulated signal (PWM). A
capacitance (C) has a first terminal coupled to the intermediate node (204), and it is alternatively charged and discharged by the currents (IH, IL) generated by the current generating circuitry (22). A
comparator circuit (24) is coupled between the intermediate node (204) and the output node (202). The
comparator circuit (24) is configured to sense a
voltage signal (Vc) at the intermediate node (204), compare the sensed voltage signal (Vc) to a reference voltage signal (Vref), and drive the output node (202) to the first output value or to the second output value as a function of the comparison, thereby generating the output signal (DATA).