180 results about "Least significant bit" patented technology

A system is disclosed for encoding a data string of a first modality into a hierarchical tokenized representation for processing by a text-based deep neural network (DNN) trained on a second modality. The data string comprises multiple units, each having one or more attributes. Each attribute is represented in the tokenized string as a sequence of hierarchical tokens, with a first hierarchical token encoding one or more most significant bits and a subsequent hierarchical token encoding one or more less significant bits. The DNN processes the data string bidirectionally, across the sequence of units and within the token hierarchy, to select tokens that capture attribute information. The selected hierarchical tokens output by the DNN from a representation of the original data string that preserves attribute detail while enabling cross-modal processing using models trained on text.

The invention discloses a database watermark management system and method, electronic equipment and a storage medium, and relates to the technical field of information security, and the disclosed database watermark management system comprises an intelligent decision layer which is used for analyzing data features of input data and determining a watermark embedding mode of the input data according to an analysis result; the bimodal embedding layer is used for carrying out watermark embedding operation on first data of which the watermark embedding mode is a numeric embedding mode in the input data by adopting a preset improved least significant bit algorithm, and carrying out watermark embedding operation on second data of which the watermark embedding mode is a non-numeric embedding mode in the input data by adopting a preset improved least significant bit algorithm; carrying out watermark embedding on the second data by adopting a multi-system invisible character replacement technology; and the cross-modal traceability layer is used for analyzing the watermark information from the input data embedded with the watermark through a preset double-watermark collaborative verification mechanism. According to the method, the adaptation degree of database watermark embedding can be improved.

Certain aspects of the present disclosure provide techniques and apparatus for efficiently performing operations using data compression. An example method generally includes identifying, for a block of data samples, a number of leading bits to remove from each data sample in the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits from each data sample in the block of data samples. A bitstream including the block of compressed data samples and an indication of a type of compression applied to the block of data samples is generated and output for further processing.

The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

A pixel driving circuit for a display device includes a clock generator configured to generate clock signals with different time periods for different locations of bit values of the image data, an array of a plurality of pixels, each pixel including a light-emitting element, and an in-pixel memory configured to store image data comprising a set of bit values from a most significant bit (MSB) to a least significant bit (LSB), and a controller configured to read the set of bit values of the image data in an order, starting from the LSB bit to the MSB, to generate pulse width modulation (PWM) signals.

The invention relates to the technical field of satellite communication, and discloses an efficient encoding and decoding and distribution transmission method for satellite image data, which comprises the following steps of: acquiring satellite epoch parameters, estimating a downlink channel capacity sequence, decomposing the image data into a basic feature code stream and a background residual code stream, and distributing a transmission priority, and mapping the basic feature code stream to the most significant bit of the modulation symbol, mapping the background residual code stream to the least significant bit of the modulation symbol, and implementing nonlinear displacement stretching on the coordinate of the constellation point where the modulation symbol is located according to the carrier frequency shift change rate. A core semantic bit phase tolerance boundary is expanded by compressing a background data judgment space, high-fidelity transmission of key image features in a severe phase distortion environment is ensured, and the information transparent transmission capacity in a high-dynamic link is improved.

A controller for an avalanche photodiode sensor, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

The invention discloses a test data processing method and a related device, and relates to the technical field of information encryption and hiding. In a data embedding stage, a target test screenshot is generated, and meanwhile, a binary bit stream of context information of the target test screenshot is obtained; the binary bit streams of the contextual information are used for replacing the least significant bits of the secondary pixel values of the target pixels in the target test screenshot one by one, the contextual information is embedded into the target test screenshot, the purpose of hiding and storing the contextual information in the target test screenshot is achieved, and further, in the data traceability stage, the data traceability efficiency is improved. By extracting the least significant bits of the secondary pixel values of the target pixels one by one from the steganographic image of the target test screenshot, extraction of the context information is realized, so that binding of the test screenshot and the context information is realized, efficient storage and security of the context information are ensured, and the test efficiency is improved. Therefore, the traceability and the accuracy of the context information are realized.

Systems and methods for correcting timing information associated with captured nuclear imaging data, and for reconstructing medical images based on the corrected timing information, are disclosed. In some embodiments, an image scanning system scans a subject, detects an event, and generates timing data for the detected event. The timing data includes a first number of bits, and characterizes a time that a crystal of the image scanning system detected the event. The image scanning system shifts the first number of bits by a predetermined amount to generate a second number of bits, where the second number of bits includes at least one bit representing a lower order time value than the least significant bit of the first number of bits of the timing data. Further, the image scanning system generates timing correction data for the event based on the second timing data.

A system and method for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization is presented. The method includes: receiving an input matrix comprising a plurality of values; selecting a portion of the input matrix; generating a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion; determining that the first and second values are identical in all but the determined number of LSBs; adjusting the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold; generating a new input matrix based on the adjusted first value; and processing the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

A method for measuring a time-of-flight interval in a depth sensing system includes generating a coarse time count using a global clock signal shared across a plurality of pixels and external to the sensor array, wherein the coarse time count provides the most significant bits of the time-of-flight interval free of inter-pixel process variation; generating an intermediate time count within a pixel using a local ring oscillator based on completed oscillation cycles during a measurement interval; generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides the least significant bits; and deriving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

This application relates to a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point number division. The method includes: obtaining a fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; mapping the first value and the second value to a preset fixed-point format respectively to obtain a third value and a fourth value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated; extracting a value of a preset bit width starting from the least significant bit of the fourth value, and determining the extracted value as a fifth value; performing iterative calculation on the third value and the fifth value until the current value meets a first preset condition, and stopping the iterative calculation; and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation. This can improve the efficiency of fixed-point number division calculation.

A method for calculating the N-bit square root B of a 2N-bit number X comprises: performing a multiplication of the bits b of the square root B. i Iterate starting from the most significant bit of the square root B and working your way down to the least significant bit. For each iteration, the method includes: positioning a 1 at bit b in the CHECK variable. i The bit b is determined based on the comparison of the number X with all previously found bits and a function of the previous comparison results. i shift all previously found bits in the CHECK variable right by 1 position; and i The determined value is added to its square position in the CHECK variable.

An audio decoder for providing a decoded audio information on the basis of an encoded audio information is configured to obtain decoded spectral values on the basis of an encoded information representing the spectral values. The audio decoder is configured to jointly decode two or more most significant bits per spectral value on the basis of respective symbol codes for a set of spectral values using an arithmetic decoding, wherein a respective symbol code represents two or more most significant bits per spectral value for one or more spectral values.The audio decoder is configured to decode one or more least significant bits associated with one or more of the spectral values in dependence on how much least significant bit information is available, such that one or more least significant bits associated with one or more of the spectral values are decoded, while no least significant bits are decoded for one or more other spectral values for which one or more most significant bits are decoded and which comprise more bits than the one or more most significant bits. The audio decoder is configured to provide the decoded audio information using the spectral values. Modifications of the audio decoder are possible. An audio encoder is also described.

A video coding mechanism is disclosed. [Solution] This mechanism includes receiving a bitstream containing a Gradual Decode Refresh (GDR) picture, a recovery point picture that follows the GDR picture in the decoding order, and a header associated with the GDR picture. The header contains the least significant bit (LSB) value of the Recovery Picture Order Count (POC), which is coded before the POC value. The POC of the GDR picture is determined based on the POC LSB value. The Recovery POC value is determined based on the POC of the GDR picture. The Recovery POC value indicates the POC of the Recovery Point Picture. The bitstream is decoded according to the GDR based on the GDR picture and the Recovery Point Picture.

A video coding mechanism is disclosed. The mechanism includes receiving a bitstream comprising a gradual decoding refresh (GDR) picture, a recovery point picture following the GDR picture in decoding order, and a header associated with the GDR picture. The header includes a picture order count (POC) least significant bit (LSB) value coded prior to a recovery POC value. A POC for the GDR picture is determined based on the POC LSB value. The recovery POC value is determined based on the POC for the GDR picture. The recovery POC value indicates a POC for the recovery point picture. The bitstream is decoded according to GDR based on the GDR picture and the recovery point picture.

This disclosure provides a signed adder circuit, chip, computing device, and electronic device. The circuit includes: a cascaded half-adder, at least one full-adder, and a sign processor. The half-adder performs addition on the least significant bit of a first multi-bit number and the least significant bit of a second multi-bit number, outputting a first carry-value and a least significant bit result value. The at least one full-adder performs addition on the middle bit of the first multi-bit number, the middle bit of the second multi-bit number, and the first carry-value or the second carry-value output by the previous full-adder, outputting at least one second carry-value and at least one middle bit result value. The sign processor performs addition on the most significant bit of the first multi-bit number, the most significant bit of the second multi-bit number, and the second carry-value output by the previous full-adder, outputting the most significant bit result value and a sign result value.

The invention belongs to the field of artificial intelligence hardware acceleration, and discloses a high-density single-fingered eDRAM storage and calculation integrated macro with bit-level sparse perception and kernel-level weight update, which comprises an input buffer, a weight buffer, a word line decoder, a bit line driver, a single-fingered eDRAM array and an output buffer, the weight buffer is used for writing weights from the off-chip and writing the weights into the single-finger eDRAM array line by line, and each single-finger eDRAM storage unit only stores one bit; the input buffer is used for writing an input activation value and transmitting a multi-bit input activation value into the single-fingered eDRAM array bit by bit from a low bit to a high bit, each row of single-fingered eDRAM is equipped with a bit saliency perception analog-to-digital converter BSA-ADC and is used for executing matrix vector multiplication and transmitting a calculation result to a calculation line CL, the BSA-ADC digitalizes an accumulation result on the calculation line, and the calculation line CL is connected with the input buffer. The result is transmitted to the output buffer; the output buffer is used for outputting the calculation result. The integrated macro has the advantages of high density, low energy consumption and high throughput.

The present disclosure provides a low-distortion PAM-4 optical transmitter with a piecewise compensation scheme for VCSEL-based optical communication links. The input half-rate least significant bit (LSB) and most significant bit (MSB) data streams of the transmitter are firstly encoded into half-rate unary-weighted data streams by thermometer encoders. The half-rate unary-weighted data streams are then fed into three data slices with 2-tap feed-forward equalizer (FFE), continuous-time linear equalizer (CTLE), pre-emphasis circuit for serialization and piecewise pre-distortion. Finally, outputs from the three data slices are added in the form of current and fed into VCSEL. A thermal control loop is implemented to monitor the temperature of the VCSEL as well as provide compensation to the bias current of the VCSEL.

This application discloses an in-memory computing macro device and an electronic device. The in-memory computing macro device includes an array of in-memory computing units comprising a plurality of in-memory computing units. First data is divided into at least two bit groups, the at least two bit groups including a first bit group and a second bit group, the first bit group being the most significant bit of the first data, the second bit group being the least significant bit of the first data, and the bit groups are respectively loaded into in-memory computing units in different columns of the in-memory computing unit array. The electronic device includes at least one in-memory computing macro and at least one processing circuit. The processing circuit is configured to receive parallel outputs corresponding to columns of the in-memory computing unit array and perform operations on the parallel outputs, wherein the parallel outputs include a plurality of corresponding groups, and each of the corresponding groups includes the most significant bit and the least significant bit of the output activation.

Method and device for generating a Gaussian error. This description relates to a device configured to generate an approximate value by adding noise to an output of a balanced arithmetic circuit, comprising: - the balanced arithmetic circuit configured to generate a first value; - an approximation circuit configured to generate a k-bit mask based on a first distribution; and - a logic circuit configured to generate a second value based on the first value, the k least significant bits of the second value being generated by applying the mask to the k least significant bits of the first value, the most significant bits of the second values ​​being equal to the most significant bits of the first value, the first distribution being such that the second value corresponds to the first value with an added error value having a Gaussian distribution of standard deviation.Figure for the abridged version: Fig. 1.

The application provides a memristor measurement matrix determination method, device, equipment, storage medium and product. The method comprises the following steps: determining the maximum value of the candidate measurement matrix bit width according to the conductance deviation characteristics of the target memristor and the target compression ratio; obtaining the target bit width interval based on the least significant bit width corresponding to the target memristor and the maximum value; generating the candidate measurement matrix corresponding to each bit width in the target bit width interval based on the statistical distribution characteristics of the original measurement matrix; performing signal reconstruction simulation based on the preset noise simulation model corresponding to the target memristor and each candidate measurement matrix to obtain the signal reconstruction accuracy corresponding to each candidate measurement matrix; and taking the candidate measurement matrix with the highest signal reconstruction accuracy as the measurement matrix of the memristor array corresponding to the target memristor, so as to enable the memristor array to perform compressive sensing. The measurement matrix used can meet the actual situation of the operation of the target memristor, and overcome the negative influence of the device characteristics on the reconstruction accuracy of compressive sensing.

The application provides a double-edge counting circuit, which comprises a logic circuit, a latch and a counter, the logic circuit is used for receiving a clock signal and a counting control signal, and then performing logical operation on the clock signal and the counting control signal to obtain a first reset signal and a first set signal, the latch is connected with the logic circuit, a reset end of the latch receives the first reset signal, a set end of the latch receives the first set signal, and an inverting output end of the latch outputs the least significant bit of the double-edge counting circuit, and the counter is connected with a non-inverting output end of the latch and is used for outputting other bits of the double-edge counting circuit, so that double-edge counting is realized, and power consumption and area are reduced. The application further provides a readout circuit and an image sensor.

An electronic device may include an electronic display and image processing circuitry. The image processing circuitry may receive input image data in a non-linear color space at a bit-depth, truncate one or more least-significant-digits of the input image data, generating truncated image data, and determine an alpha value indicative of how many pixel locations, of a block of pixels, to which an increase in gray level is to be applied based on an input pixel value, corresponding to a pixel of interest within the block of pixels. Additionally, the alpha value may correspond to a ratio of gray levels in a linear color space that equates to a luminance level of the input pixel value at the bit-depth. The increase in the gray level may be applied to pixel values of the truncated image data corresponding to the pixel locations to generate dithered image data.

An electronic device may include an electronic display and image processing circuitry. The image processing circuitry may receive input image data in a non-linear color space at a bit-depth, truncate one or more least-significant-digits of the input image data, generating truncated image data, and determine an alpha value indicative of how many pixel locations, of a block of pixels, to which an increase in gray level is to be applied based on an input pixel value, corresponding to a pixel of interest within the block of pixels. Additionally, the alpha value may correspond to a ratio of gray levels in a linear color space that equates to a luminance level of the input pixel value at the bit-depth. The increase in the gray level may be applied to pixel values of the truncated image data corresponding to the pixel locations to generate dithered image data.

The invention discloses an analog-to-digital converter and a resolution ratio improving method and a common-mode voltage compensation method thereof. The sampled # imgabs0 # and # imgabs1 # are subjected to pipeline-level M-level step-by-step quantization, n-bit binary digital codes are obtained through the Mth-level quantization, and n-bit non-binary digital codes are obtained through the other levels of quantization. The method comprises the following steps: under the condition of ensuring that first-stage quantization and second-stage quantization adopt # imgabs2 # with the same architecture for quantization, during first-stage quantization, adding one-bit successive approximation conversion to # imgabs3 # and # imgabs4 # after sampling; and the # imgabs5 # and the # imgabs6 # which are subjected to successive approximation conversion are converted into one-bit binary digital codes. And sequentially carrying out digital synthesis on each level of quantized digital code to form a # imgabs7 # binary digital code, and during digital synthesis, adding the 1-bit binary digital code before the highest bit of the # imgabs8 # binary digital code to form a # imgabs9 # binary digital code. The architecture improves the input swing of the analog-to-digital converter, thereby improving the least significant bit of the system.

The application discloses a method for realizing covert communication by using a terahertz high-speed data transmission, which combines information hiding technology with a terahertz high-speed data transmission system, uses original data of a terahertz high-speed data transmission channel as a carrier, carries out digital sampling on an analog signal which needs to be separately transmitted, modifies values of a data part of the carrier, matches the data to be hidden with a function value of the carrier data, hides marking information in the data containing the hidden information, and further improves quality of the carrier data at a receiving end, and saves channel resources for transmitting the analog signal. The information hiding process is carried out at a front end of the terahertz high-speed data transmission system, and does not change a terahertz wireless communication system. The hiding method is simple and flexible, and PSNR is improved by 3 dB compared with a least significant bit replacement method under the condition of the same hiding capacity.