94 results about "Least significant bit" patented technology

Certain aspects of the present disclosure provide techniques and apparatus for efficiently performing operations using data compression. An example method generally includes identifying, for a block of data samples, a number of leading bits to remove from each data sample in the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits from each data sample in the block of data samples. A bitstream including the block of compressed data samples and an indication of a type of compression applied to the block of data samples is generated and output for further processing.

The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

The invention relates to the technical field of satellite communication, and discloses an efficient encoding and decoding and distribution transmission method for satellite image data, which comprises the following steps of: acquiring satellite epoch parameters, estimating a downlink channel capacity sequence, decomposing the image data into a basic feature code stream and a background residual code stream, and distributing a transmission priority, and mapping the basic feature code stream to the most significant bit of the modulation symbol, mapping the background residual code stream to the least significant bit of the modulation symbol, and implementing nonlinear displacement stretching on the coordinate of the constellation point where the modulation symbol is located according to the carrier frequency shift change rate. A core semantic bit phase tolerance boundary is expanded by compressing a background data judgment space, high-fidelity transmission of key image features in a severe phase distortion environment is ensured, and the information transparent transmission capacity in a high-dynamic link is improved.

Systems and methods for correcting timing information associated with captured nuclear imaging data, and for reconstructing medical images based on the corrected timing information, are disclosed. In some embodiments, an image scanning system scans a subject, detects an event, and generates timing data for the detected event. The timing data includes a first number of bits, and characterizes a time that a crystal of the image scanning system detected the event. The image scanning system shifts the first number of bits by a predetermined amount to generate a second number of bits, where the second number of bits includes at least one bit representing a lower order time value than the least significant bit of the first number of bits of the timing data. Further, the image scanning system generates timing correction data for the event based on the second timing data.

A system and method for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization is presented. The method includes: receiving an input matrix comprising a plurality of values; selecting a portion of the input matrix; generating a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion; determining that the first and second values are identical in all but the determined number of LSBs; adjusting the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold; generating a new input matrix based on the adjusted first value; and processing the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

This application relates to a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point number division. The method includes: obtaining a fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; mapping the first value and the second value to a preset fixed-point format respectively to obtain a third value and a fourth value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated; extracting a value of a preset bit width starting from the least significant bit of the fourth value, and determining the extracted value as a fifth value; performing iterative calculation on the third value and the fifth value until the current value meets a first preset condition, and stopping the iterative calculation; and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation. This can improve the efficiency of fixed-point number division calculation.

A video coding mechanism is disclosed. [Solution] This mechanism includes receiving a bitstream containing a Gradual Decode Refresh (GDR) picture, a recovery point picture that follows the GDR picture in the decoding order, and a header associated with the GDR picture. The header contains the least significant bit (LSB) value of the Recovery Picture Order Count (POC), which is coded before the POC value. The POC of the GDR picture is determined based on the POC LSB value. The Recovery POC value is determined based on the POC of the GDR picture. The Recovery POC value indicates the POC of the Recovery Point Picture. The bitstream is decoded according to the GDR based on the GDR picture and the Recovery Point Picture.

A video coding mechanism is disclosed. The mechanism includes receiving a bitstream comprising a gradual decoding refresh (GDR) picture, a recovery point picture following the GDR picture in decoding order, and a header associated with the GDR picture. The header includes a picture order count (POC) least significant bit (LSB) value coded prior to a recovery POC value. A POC for the GDR picture is determined based on the POC LSB value. The recovery POC value is determined based on the POC for the GDR picture. The recovery POC value indicates a POC for the recovery point picture. The bitstream is decoded according to GDR based on the GDR picture and the recovery point picture.

This disclosure provides a signed adder circuit, chip, computing device, and electronic device. The circuit includes: a cascaded half-adder, at least one full-adder, and a sign processor. The half-adder performs addition on the least significant bit of a first multi-bit number and the least significant bit of a second multi-bit number, outputting a first carry-value and a least significant bit result value. The at least one full-adder performs addition on the middle bit of the first multi-bit number, the middle bit of the second multi-bit number, and the first carry-value or the second carry-value output by the previous full-adder, outputting at least one second carry-value and at least one middle bit result value. The sign processor performs addition on the most significant bit of the first multi-bit number, the most significant bit of the second multi-bit number, and the second carry-value output by the previous full-adder, outputting the most significant bit result value and a sign result value.

The invention belongs to the field of artificial intelligence hardware acceleration, and discloses a high-density single-fingered eDRAM storage and calculation integrated macro with bit-level sparse perception and kernel-level weight update, which comprises an input buffer, a weight buffer, a word line decoder, a bit line driver, a single-fingered eDRAM array and an output buffer, the weight buffer is used for writing weights from the off-chip and writing the weights into the single-finger eDRAM array line by line, and each single-finger eDRAM storage unit only stores one bit; the input buffer is used for writing an input activation value and transmitting a multi-bit input activation value into the single-fingered eDRAM array bit by bit from a low bit to a high bit, each row of single-fingered eDRAM is equipped with a bit saliency perception analog-to-digital converter BSA-ADC and is used for executing matrix vector multiplication and transmitting a calculation result to a calculation line CL, the BSA-ADC digitalizes an accumulation result on the calculation line, and the calculation line CL is connected with the input buffer. The result is transmitted to the output buffer; the output buffer is used for outputting the calculation result. The integrated macro has the advantages of high density, low energy consumption and high throughput.

The present disclosure provides a low-distortion PAM-4 optical transmitter with a piecewise compensation scheme for VCSEL-based optical communication links. The input half-rate least significant bit (LSB) and most significant bit (MSB) data streams of the transmitter are firstly encoded into half-rate unary-weighted data streams by thermometer encoders. The half-rate unary-weighted data streams are then fed into three data slices with 2-tap feed-forward equalizer (FFE), continuous-time linear equalizer (CTLE), pre-emphasis circuit for serialization and piecewise pre-distortion. Finally, outputs from the three data slices are added in the form of current and fed into VCSEL. A thermal control loop is implemented to monitor the temperature of the VCSEL as well as provide compensation to the bias current of the VCSEL.

This application discloses an in-memory computing macro device and an electronic device. The in-memory computing macro device includes an array of in-memory computing units comprising a plurality of in-memory computing units. First data is divided into at least two bit groups, the at least two bit groups including a first bit group and a second bit group, the first bit group being the most significant bit of the first data, the second bit group being the least significant bit of the first data, and the bit groups are respectively loaded into in-memory computing units in different columns of the in-memory computing unit array. The electronic device includes at least one in-memory computing macro and at least one processing circuit. The processing circuit is configured to receive parallel outputs corresponding to columns of the in-memory computing unit array and perform operations on the parallel outputs, wherein the parallel outputs include a plurality of corresponding groups, and each of the corresponding groups includes the most significant bit and the least significant bit of the output activation.

Method and device for generating a Gaussian error. This description relates to a device configured to generate an approximate value by adding noise to an output of a balanced arithmetic circuit, comprising: - the balanced arithmetic circuit configured to generate a first value; - an approximation circuit configured to generate a k-bit mask based on a first distribution; and - a logic circuit configured to generate a second value based on the first value, the k least significant bits of the second value being generated by applying the mask to the k least significant bits of the first value, the most significant bits of the second values ​​being equal to the most significant bits of the first value, the first distribution being such that the second value corresponds to the first value with an added error value having a Gaussian distribution of standard deviation.Figure for the abridged version: Fig. 1.

The application provides a memristor measurement matrix determination method, device, equipment, storage medium and product. The method comprises the following steps: determining the maximum value of the candidate measurement matrix bit width according to the conductance deviation characteristics of the target memristor and the target compression ratio; obtaining the target bit width interval based on the least significant bit width corresponding to the target memristor and the maximum value; generating the candidate measurement matrix corresponding to each bit width in the target bit width interval based on the statistical distribution characteristics of the original measurement matrix; performing signal reconstruction simulation based on the preset noise simulation model corresponding to the target memristor and each candidate measurement matrix to obtain the signal reconstruction accuracy corresponding to each candidate measurement matrix; and taking the candidate measurement matrix with the highest signal reconstruction accuracy as the measurement matrix of the memristor array corresponding to the target memristor, so as to enable the memristor array to perform compressive sensing. The measurement matrix used can meet the actual situation of the operation of the target memristor, and overcome the negative influence of the device characteristics on the reconstruction accuracy of compressive sensing.

An electronic device may include an electronic display and image processing circuitry. The image processing circuitry may receive input image data in a non-linear color space at a bit-depth, truncate one or more least-significant-digits of the input image data, generating truncated image data, and determine an alpha value indicative of how many pixel locations, of a block of pixels, to which an increase in gray level is to be applied based on an input pixel value, corresponding to a pixel of interest within the block of pixels. Additionally, the alpha value may correspond to a ratio of gray levels in a linear color space that equates to a luminance level of the input pixel value at the bit-depth. The increase in the gray level may be applied to pixel values of the truncated image data corresponding to the pixel locations to generate dithered image data.

Provided herein are memory devices capable of completing a foggy-fine programming operation in one ready / busy period. The memory device can include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first programming operation on a page adjacent to a selected page of the plurality of pages and a second programming operation on the selected page, and control logic configured to control the peripheral circuit to continuously receive, from a memory controller, least significant bit (LSB) page data for the page adjacent to the selected page, middle significant bit (CSB) page data for the selected page, and most significant bit (MSB) page data for the selected page, program the LSB page data for the page adjacent to the selected page to the page adjacent to the selected page, obtain the LSB page data for the selected page previously stored in the selected page, and program the LSB page data, the CSB page data, and the MSB page data for the selected page to the selected page.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

This application relates to a two-stage Gray code counter with redundant bits. An N-bit counter includes a lower counter having a first output of M bits, the lower counter operating at a first count frequency. An upper counter having a second output of N-M+L bits operates at a second count frequency. The second count frequency is equal to the first count frequency divided by 2 (M‑L) An error correction controller is coupled to receive the first and second outputs and to perform operations including comparing L least significant bits (LSBs) of the second output to at least one most significant bit (MSB) of the first output, and correcting N-M MSBs of the second output in response to the comparison. The lower bits of the N-bit counter are the M bits of the first output, and the upper bits of the N-bit counter are the corrected N-M MSBs of the second output.

Methods, systems, and devices for wireless communications are described. A wireless device may encode one or more most significant bits (MSBs) of a bit sequence according to an encoding rate to generate a set of shaped bits. The bit sequence may include the one or more MSBs and one or more least significant bits (LSBs), where a quantity of the one or more MSBs that are encoded may be based on the encoding rate. The UE may map each bit of the set of shaped bits to a respective modulation symbol of a quantity of modulation symbols according to a quadrature amplitude modulation (QAM) scheme. The UE may also map the one or more LSBs to the quantity of modulation symbols according to the QAM scheme. The UE may modulate a signal based on the mappings and transmit the signal based on the modulation.

The embodiment of the invention provides a frozen screen detection method, an electronic device, a storage medium and a program product, for at least two frame images continuously output to a display screen, according to the least significant bit of each frame image under a preset color channel, a to-be-detected image block of the frame image is determined, and according to the to-be-detected image block of the frame image and a preset watermark block, the to-be-detected image block of the frame image is detected. The watermark blocks carried by the frame images are determined, and then whether the display screen is frozen or not is determined according to the change conditions of the watermark blocks carried by at least two frame images. The to-be-detected image block is inserted into the least significant bit of the preset color channel, so that the influence on the frame image is small, and the image quality of the frame image is ensured while the frozen screen detection is realized.

The invention provides a random time slot generation method and device, a medium and an indoor unit unique communication address generation method, and belongs to the technical field of communication. The method comprises the steps that AD conversion values of an indoor temperature sensor, an inner disc temperature sensor, an air pipe temperature sensor and a liquid pipe temperature sensor are read; extracting the least significant bits of the four AD conversion values, and combining the least significant bits into a four-bit binary number according to a preset sequence; the four-bit binary number is converted, so that final random values generated by all the indoor units are evenly distributed in adjacent numerical value intervals and are not repeated; and determining the final random value as a random time slot of communication with the outdoor unit when the indoor unit has no address. By means of the scheme, the address allocation efficiency is effectively improved.

This invention discloses a signal digitization method based on an ADC circuit, comprising: inputting the analog signal to be converted into an ADC circuit, performing a first conversion process by the ADC circuit, and outputting a first ADC output value M. i According to the output value M i The value of the high output bit adjusts the least significant bit of the ADC circuit. When the output value M... i The higher-order output bits are all 0, thus lowering the least significant bit of the ADC circuit; the analog signal to be converted is then input back into the ADC circuit, and the (i+1)th ADC output value M is output. i+1 By combining all ADC output values, the final signal conversion result and the adjusted least significant bit are output. This invention can improve the accuracy of small-signal ADCs without increasing the ADC circuit area.

A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.

A system and method of digital to analog conversion including modulating a digital value DN−K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which DN−K comprises N−K least significant bits of an N-bit digital input value DN and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding DM to a value DK to provide a select value DKM in which DK includes the K remaining most significant bits of DN, and applying mismatch shaping of a total of at least P=2K elements of a P-element DAC per cycle based on DKM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.

The present disclosure relates to the field of telecommunications, and in particular to devices, methods, apparatus and computer readable storage media for indicating the periodicity of a synchronization signal and / or performing an action based on the periodicity. An aspect of aspects of the present disclosure presents an apparatus that is caused to perform at least one of: receiving a broadcast channel including system frame number (SFN) information, where at least one of least significant bits (LSB) of the SFN information is related to a periodicity of a synchronization signal; determining a periodicity based on at least one bit in the LSB; and performing at least one action based on the determined periodicity.

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

An output stream can be generated of compressed textual data. A first portion of the output stream includes an indicator that compression is used and a second portion is the compressed textual data. The textual data can be compressed by processing each byte of an input text bit-by-bit in order from most significant bit to least significant bit to generate an n-byte length context and a word context. While processing each byte, a subsequent bit is predicted based on the n-byte length context and a corresponding prediction model, and the subsequent bit is predicted based on the word context and a corresponding prediction model. The predictions can be combined to generate a final prediction. If the final prediction determines the subsequent bit, then the subsequent bit can be skipped in the output stream. The output stream can be provided to another device over a communication interface.

Converting telemetry values into a generic data format in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip includes a processor-based system configured to receive an input telemetry value from an input source circuit. The processor-based system converts the input telemetry value to a generic format telemetry value, wherein a first unit value represented by least significant bits of the generic format telemetry value is greater than one (1) and based on a quotient of a power of two (2) and a corresponding power of 10. The processor-based system then processes the generic format telemetry value.