248 results about "Least significant bit" patented technology

A system is disclosed for encoding a data string of a first modality into a hierarchical tokenized representation for processing by a text-based deep neural network (DNN) trained on a second modality. The data string comprises multiple units, each having one or more attributes. Each attribute is represented in the tokenized string as a sequence of hierarchical tokens, with a first hierarchical token encoding one or more most significant bits and a subsequent hierarchical token encoding one or more less significant bits. The DNN processes the data string bidirectionally, across the sequence of units and within the token hierarchy, to select tokens that capture attribute information. The selected hierarchical tokens output by the DNN from a representation of the original data string that preserves attribute detail while enabling cross-modal processing using models trained on text.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

The invention discloses a database watermark management system and method, electronic equipment and a storage medium, and relates to the technical field of information security, and the disclosed database watermark management system comprises an intelligent decision layer which is used for analyzing data features of input data and determining a watermark embedding mode of the input data according to an analysis result; the bimodal embedding layer is used for carrying out watermark embedding operation on first data of which the watermark embedding mode is a numeric embedding mode in the input data by adopting a preset improved least significant bit algorithm, and carrying out watermark embedding operation on second data of which the watermark embedding mode is a non-numeric embedding mode in the input data by adopting a preset improved least significant bit algorithm; carrying out watermark embedding on the second data by adopting a multi-system invisible character replacement technology; and the cross-modal traceability layer is used for analyzing the watermark information from the input data embedded with the watermark through a preset double-watermark collaborative verification mechanism. According to the method, the adaptation degree of database watermark embedding can be improved.

This disclosure provides systems, methods, and apparatuses for wireless communication that can be used to reduce the peak-to-average power ratio (PAPR) of data transmissions by increasing the degree of randomness with which data is scrambled for transmission over a wireless medium. In some implementations, a transmitting device may determine a scrambler seed value that includes at least 11 bits, where at least one of the 7 least significant bits (LSBs) of the scrambler seed value has a non-zero value. The transmitting device may generate a scrambling sequence based on the scrambler seed value and a polynomial, may construct a physical layer convergence protocol (PLCP) protocol data unit (PPDU) that includes a multi-user (MU) request-to-send (RTS) frame and the scrambler seed value, may scramble one or more portions of the PPDU based on the scrambling sequence; and may transmit the PPDU over a wireless medium.

In described examples, an integrated circuit (IC) includes a comparator, a shift calculator, an aligner, a compressor, and an adder. The comparator determines a largest one of multiple exponents. The shift calculator subtract the exponents from the determined largest exponent to provide a set of shift values. The aligner shifts a subset of a set of data values in a least significant bit direction responsive to respective ones of the shift values to generate a first number of aligned data values. The compressor generates a second number of compressed data values responsive to the first number of aligned data values. The second number is less than the first number. An adder sums the compressed data values.

A protection circuit for a Sbox, including: a first check circuit configured to determine if a most significant bit (MSB) part input into a first multiplier of the Sbox is zero; a second check circuit configured to determine if a CCn value input into the first multiplier and a second multiplier of the Sbox is zero; a third check circuit configured to determine if a least significant bit (LSB) part input into a first multiplier of the Sbox is zero; and a first Statistical Ineffective Fault Analysis (SIFA) logic circuit configured to produce a first output to indicate a SIFA attack when one of the following conditions is satisfied: both the MSB part and the LSB part are zero and the CCn value is not zero: or the CCn value is zero and either of the MSB part and LSB part are not zero.

Certain aspects of the present disclosure provide techniques and apparatus for efficiently performing operations using data compression. An example method generally includes identifying, for a block of data samples, a number of leading bits to remove from each data sample in the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits from each data sample in the block of data samples. A bitstream including the block of compressed data samples and an indication of a type of compression applied to the block of data samples is generated and output for further processing.

Power consumption is reduced in an analog-to-digital conversion circuit using a TDC. The analog-to-digital conversion circuit includes a comparator, a counter, a time-to-digital converter, and a holding unit. The comparator compares an analog signal with a predetermined reference signal and outputs a comparison result. The counter counts a predetermined count value and outputs a bit string indicating the count value. The time-to-digital converter converts, into a digital signal, a time from when the comparison result is inverted until a least significant bit of the bit string reaches a predetermined value. The holding unit holds the bit string of when the comparison result is inverted.

A computer-implemented method for compressing, an input group of m data values compresses the two least significant bits of each of the data values by mapping the two least significant bits of each of the data values in the input group of m data values collectively onto an m-bit encoding and storing the m-bit encoding, the m-bit encoding being selected from 2m m-bit encodings, the 2m m-bit encodings comprising a first group of encodings comprising (2m−4) m-bit encodings and a second group of encodings comprising four m-bit encodings, wherein if the selected encoding is an encoding from the first group of encodings then the selected encoding represents the two least significant bits for a representative group of m data values in which the second least significant bit of each of the data values is the same as a respective bit of the m-bit encoding, and wherein if the selected encoding is an encoding from the second group of encodings then the selected encoding represents the two least significant bits for a representative group of m data values in which the two least significant bits for each of the data values in the representative group are equal to the two least significant bits of the other data values in the representative group.

The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.

Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

A pixel driving circuit for a display device includes a clock generator configured to generate clock signals with different time periods for different locations of bit values of the image data, an array of a plurality of pixels, each pixel including a light-emitting element, and an in-pixel memory configured to store image data comprising a set of bit values from a most significant bit (MSB) to a least significant bit (LSB), and a controller configured to read the set of bit values of the image data in an order, starting from the LSB bit to the MSB, to generate pulse width modulation (PWM) signals.

The invention relates to the technical field of satellite communication, and discloses an efficient encoding and decoding and distribution transmission method for satellite image data, which comprises the following steps of: acquiring satellite epoch parameters, estimating a downlink channel capacity sequence, decomposing the image data into a basic feature code stream and a background residual code stream, and distributing a transmission priority, and mapping the basic feature code stream to the most significant bit of the modulation symbol, mapping the background residual code stream to the least significant bit of the modulation symbol, and implementing nonlinear displacement stretching on the coordinate of the constellation point where the modulation symbol is located according to the carrier frequency shift change rate. A core semantic bit phase tolerance boundary is expanded by compressing a background data judgment space, high-fidelity transmission of key image features in a severe phase distortion environment is ensured, and the information transparent transmission capacity in a high-dynamic link is improved.

A method for transmitting binary data using a M-ASK constellation divided into M / 2 sets of two symbols is disclosed. Each set of index i comprises the ith and ith+M / 2 symbols of the constellation and is associated with a probability pi of transmitting the first symbol of the set. First, m−1 bits are obtained from an equiprobable binary source where m=log2M. A binary source is then selected in a plurality of binary sources responsive to said m−1 bits, each binary source of index i being associated with a probability of outputting a bit zero equal to pi. A symbol of the M-ASK constellation is obtained that is associated with the binary word formed by the m−1 bits as less significant bits and a bit obtained from the selected source as most significant bit. The symbol is finally transmitted to a receiver over a communication channel.

A controller for an avalanche photodiode sensor, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

The invention discloses a test data processing method and a related device, and relates to the technical field of information encryption and hiding. In a data embedding stage, a target test screenshot is generated, and meanwhile, a binary bit stream of context information of the target test screenshot is obtained; the binary bit streams of the contextual information are used for replacing the least significant bits of the secondary pixel values of the target pixels in the target test screenshot one by one, the contextual information is embedded into the target test screenshot, the purpose of hiding and storing the contextual information in the target test screenshot is achieved, and further, in the data traceability stage, the data traceability efficiency is improved. By extracting the least significant bits of the secondary pixel values of the target pixels one by one from the steganographic image of the target test screenshot, extraction of the context information is realized, so that binding of the test screenshot and the context information is realized, efficient storage and security of the context information are ensured, and the test efficiency is improved. Therefore, the traceability and the accuracy of the context information are realized.

This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.

Systems and methods for correcting timing information associated with captured nuclear imaging data, and for reconstructing medical images based on the corrected timing information, are disclosed. In some embodiments, an image scanning system scans a subject, detects an event, and generates timing data for the detected event. The timing data includes a first number of bits, and characterizes a time that a crystal of the image scanning system detected the event. The image scanning system shifts the first number of bits by a predetermined amount to generate a second number of bits, where the second number of bits includes at least one bit representing a lower order time value than the least significant bit of the first number of bits of the timing data. Further, the image scanning system generates timing correction data for the event based on the second timing data.

A system and method for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization is presented. The method includes: receiving an input matrix comprising a plurality of values; selecting a portion of the input matrix; generating a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion; determining that the first and second values are identical in all but the determined number of LSBs; adjusting the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold; generating a new input matrix based on the adjusted first value; and processing the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

The present invention proposes a hybrid video dual-watermarking method and system. The method extracts the chrominance channel of each video frame, calculates the extreme harmonic Fourier moment of the chrominance channel frame by frame, combines the calculation results with copyright information, and obtains a robust watermarked video frame. The robust watermarked video is then divided into various color channels. An enhanced least significant bit method is used for each color channel, combined with anti-counterfeiting information, to obtain a hybrid dual-watermarked video. The present invention can effectively protect valuable video content, accurately detect forged areas in the video, and demonstrate strong resistance to various attacks such as rotation, scaling, noise, and compression. In addition, the present invention can extract watermarks without the need for auxiliary information. The extreme harmonic Fourier moment of the chrominance channel of the transmitted video is calculated frame by frame to extract the robust watermark. The fragile watermark is extracted from each color channel of the video frame through an extraction function, and subsequent copyright authentication and anti-counterfeiting authentication operations can be completed.

A method for measuring a time-of-flight interval in a depth sensing system includes generating a coarse time count using a global clock signal shared across a plurality of pixels and external to the sensor array, wherein the coarse time count provides the most significant bits of the time-of-flight interval free of inter-pixel process variation; generating an intermediate time count within a pixel using a local ring oscillator based on completed oscillation cycles during a measurement interval; generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides the least significant bits; and deriving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

This application relates to a method, apparatus, control chip, air conditioner, and storage medium for calculating fixed-point number division. The method includes: obtaining a fixed-point number to be calculated, wherein the fixed-point number to be calculated includes a first value as the dividend and a second value as the divisor; mapping the first value and the second value to a preset fixed-point format respectively to obtain a third value and a fourth value represented by the preset fixed-point format, wherein the data convergence efficiency of the preset fixed-point format is higher than the data convergence efficiency of the original format of the fixed-point number to be calculated; extracting a value of a preset bit width starting from the least significant bit of the fourth value, and determining the extracted value as a fifth value; performing iterative calculation on the third value and the fifth value until the current value meets a first preset condition, and stopping the iterative calculation; and determining the division result corresponding to the fixed-point number to be calculated based on the third value obtained from the final iterative calculation. This can improve the efficiency of fixed-point number division calculation.

A method for calculating the N-bit square root B of a 2N-bit number X comprises: performing a multiplication of the bits b of the square root B. i Iterate starting from the most significant bit of the square root B and working your way down to the least significant bit. For each iteration, the method includes: positioning a 1 at bit b in the CHECK variable. i The bit b is determined based on the comparison of the number X with all previously found bits and a function of the previous comparison results. i shift all previously found bits in the CHECK variable right by 1 position; and i The determined value is added to its square position in the CHECK variable.

An audio decoder for providing a decoded audio information on the basis of an encoded audio information is configured to obtain decoded spectral values on the basis of an encoded information representing the spectral values. The audio decoder is configured to jointly decode two or more most significant bits per spectral value on the basis of respective symbol codes for a set of spectral values using an arithmetic decoding, wherein a respective symbol code represents two or more most significant bits per spectral value for one or more spectral values.The audio decoder is configured to decode one or more least significant bits associated with one or more of the spectral values in dependence on how much least significant bit information is available, such that one or more least significant bits associated with one or more of the spectral values are decoded, while no least significant bits are decoded for one or more other spectral values for which one or more most significant bits are decoded and which comprise more bits than the one or more most significant bits. The audio decoder is configured to provide the decoded audio information using the spectral values. Modifications of the audio decoder are possible. An audio encoder is also described.

A method for changing a bitwidth of an FPGA configuration for an FPGA, the FPGA configuration having a plurality of at least 2n bit-containing data signals with nε and ≥3, and the method having the step: when a threshold of a current consumption and / or a temperature of the FPGA is exceeded and / or a replacement signal is present, replacing k least significant bits of the data signals in each case with a zero with kε and ≥2 during an execution of the FPGA configuration on the FPGA.

A video coding mechanism is disclosed. [Solution] This mechanism includes receiving a bitstream containing a Gradual Decode Refresh (GDR) picture, a recovery point picture that follows the GDR picture in the decoding order, and a header associated with the GDR picture. The header contains the least significant bit (LSB) value of the Recovery Picture Order Count (POC), which is coded before the POC value. The POC of the GDR picture is determined based on the POC LSB value. The Recovery POC value is determined based on the POC of the GDR picture. The Recovery POC value indicates the POC of the Recovery Point Picture. The bitstream is decoded according to the GDR based on the GDR picture and the Recovery Point Picture.

A method may include receiving, at a receiver, a signal comprising a symbol. The method may include performing, at the receiver, a first operation using a number of most significant bits by gating a selected number of least significant bits. The method may include detecting, at the receiver, a symbol value of the symbol using the first operation.